US20190271728A1 - Device and method for detecting a number of electrostatic discharges - Google Patents

Device and method for detecting a number of electrostatic discharges Download PDF

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Publication number
US20190271728A1
US20190271728A1 US16/348,232 US201716348232A US2019271728A1 US 20190271728 A1 US20190271728 A1 US 20190271728A1 US 201716348232 A US201716348232 A US 201716348232A US 2019271728 A1 US2019271728 A1 US 2019271728A1
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Prior art keywords
detection unit
memory block
recited
voltage
block
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Abandoned
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US16/348,232
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English (en)
Inventor
Timo Seitzinger
Franz Dietz
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Robert Bosch GmbH
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Robert Bosch GmbH
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Assigned to ROBERT BOSCH GMBH reassignment ROBERT BOSCH GMBH ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DIETZ, FRANZ, SEITZINGER, Timo
Publication of US20190271728A1 publication Critical patent/US20190271728A1/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/001—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing
    • G01R31/002—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing where the device under test is an electronic circuit
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H1/00—Details of emergency protective circuit arrangements
    • H02H1/0007—Details of emergency protective circuit arrangements concerning the detecting means
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits

Definitions

  • the present invention relates to an apparatus and a method for detecting a number of electrostatic discharges.
  • Integrated circuits contain a plurality of structures made of different materials. The sensitivity of those structures to stress is greatly increasing because the structure sizes are becoming smaller and smaller.
  • Electrostatic discharges (ESDs) in or through the chip are one type of stress. They are produced by charge separation and charge accumulation when two surfaces of materials having different electron affinities touch one another. An electrostatic charge occurs if even a small component of a machine or a package slips.
  • An electrostatic charge of this kind charges components to several thousand volts. Depending on the technology, defects in components and structures can occur in modern ASICs at a voltage of as little as 1 V.
  • Electrostatic discharges occur comparatively frequently.
  • structures that clamp, i.e. limit, the voltage at the input of the ICs are built into ASICs.
  • So-called “ESD clamps” provide the accumulated charge with a low-impedance path for dissipation of the charge carriers. These sensitive structures of the ASICs are thereby protected from high voltages and currents.
  • ESD clamps are dimensioned as economically as possible, but already have a comparatively large area.
  • the physical size of the ESD clamps is up to 30% of the total circuit size, and depends on the intensity of the electrostatic discharge assumed for the circuit. For that reason, some ESD structures can withstand only a limited number of discharges and then can no longer adequately protect the ASIC.
  • the ESD clamps are moreover dimensioned so that the ASIC is protected from overvoltage only within the context of its specification. An unexpectedly high voltage applied briefly to the ASIC can therefore still destroy components.
  • An object of the present invention is to reliably detect the number of electrostatic discharges.
  • An example apparatus for detecting a number of electrostatic discharges in accordance with the present invention encompasses a discharge protection device.
  • a detection unit is disposed or connected electrically in parallel with the discharge protection device.
  • the detection unit encompasses at least one memory block, and the memory block has a reset input.
  • the advantage here is that the detection unit can be used repeatedly and the number of memory cells required is small, so that the detection unit occupies little space.
  • the detection unit has an energy block that encompasses a linear controller.
  • the charge quantity that is delivered to the memory block is kept constant. In other words, the voltage at the memory block is limited.
  • the detection unit has a switch.
  • the switch encompasses in particular an NMOS transistor that is connected as or functions as a diode.
  • the advantage here is that an electrostatic discharge is detected only above a specific voltage swing.
  • the switch is disposed between the discharge protection device and the memory block.
  • the energy block has a first output and a second output, a capacitor being disposed between the first output and the second output.
  • the advantage here is that a capacitor having a small area can be used.
  • the memory block has a first terminal and a second terminal, a timer being disposed between the first terminal and the second terminal.
  • the memory cell can be written to. In other words, a discharge of the programming pin takes place.
  • the detection unit has an evaluation unit.
  • the advantage here is that the memory cell can be read out during the electrostatic discharge pulse.
  • the detection unit encompasses a counter.
  • the detection unit encompasses at least one bistable flip-flop.
  • the advantage here is that the memory cell is evaluated with zero current.
  • the method according to the present invention for detecting a number of electrostatic discharges encompasses detection of a voltage that is present at a discharge protection device. Depending on the voltage that is detected, an input voltage of the detection unit is generated. A switching of the detection unit becomes activated, and at least one memory cell of the memory block is written to. The number of electrostatic discharges is detected.
  • an evaluation unit reads out the state of at least one memory cell of the memory block during the occurrence of an electrostatic discharge pulse.
  • the advantage here is that no buffer capacitors are needed in order to store the energy of the electrostatic discharge pulse, so that the space requirement of the detection unit is low.
  • FIG. 1 is a block diagram of an apparatus for detecting a number of electrostatic discharges.
  • FIG. 2 shows the apparatus for detecting the number of electrostatic discharges, with an equivalent circuit diagram of the energy block
  • FIG. 3 is a block diagram of the apparatus for detecting the number of electrostatic discharges, having an evaluation unit.
  • FIG. 4 is a block diagram of the apparatus for detecting two electrostatic discharges.
  • FIG. 5 shows a circuit for generating a read signal that is generated with a time offset from the supply voltage.
  • FIG. 6 shows a level shifter
  • FIG. 7 shows a method for detecting a number of electrostatic discharges.
  • FIG. 1 is a block diagram of an apparatus 100 for detecting a number of electrostatic discharges.
  • Apparatus 100 encompasses a first terminal 101 and a second terminal 102 which are electrically connected to a discharge protection device 103 .
  • Discharge protection device 103 protects at least one component terminal of an ASIC from overvoltage, for example that component terminal of the ASIC which is electrically conductively connected to first terminal 101 .
  • a ground path of the ASIC typically is electrically conductively connected to second terminal 102 .
  • a detection unit 107 is disposed or connected electrically in parallel with discharge protection device 103 . This means that detection unit 107 recognizes or detects electrostatic discharge pulses.
  • Detection unit 107 encompasses an energy block 104 and a memory block 106 , the memory block having at least one memory cell.
  • Energy block 104 encompasses a first input 108 , a second input 109 , and a first output 110 .
  • a second input 109 of energy block 104 is connected, for example, to ground.
  • Memory block 106 encompasses a first input 111 , a second input 112 , a reset input 113 , a first output 114 , and a second output 115 .
  • Second input 112 of memory block 106 is connected, for example, to ground.
  • First output 110 of energy block 104 is electrically conductively connected to first input 111 of memory block 106 .
  • First output 114 of memory block 106 is inverted with respect to second output 115 of memory block 106 .
  • first output 114 of memory block 106 is not inverted with respect to second output 115 of the memory block.
  • FIG. 2 shows the apparatus for detecting the number of electrostatic discharges, with an equivalent circuit diagram of energy block 204 .
  • Energy block 204 is disposed between discharge protection device 203 and memory block 206 , memory block 206 encompassing, by way of example, one memory cell.
  • Energy block 204 encompasses a linear regulator that has a resistor 216 and a Zener diode 217 .
  • Energy block 204 additionally has a switching 218 and a capacitor 219 .
  • Switching 218 encompasses, for example, an NMOS transistor that is wired or interconnected as a diode.
  • Resistor 216 limits an output current of the linear regulator.
  • Zener diode 217 limits a capacitor voltage of capacitor 219 .
  • Capacitor 219 has a small inherent area and is used to stabilize the voltage during a memory operation.
  • the purpose of the linear regulator is to furnish, for the time period during which an electrostatic discharge pulse occurs, a predefined voltage at first input 211 of memory block 206 .
  • a voltage of at least 10 V is typically needed in order to program the memory cell or memory block.
  • the predefined voltage must be present for a specific time period at first input 211 of memory block 206 . This is achieved with the aid of a timer 220 that is disposed between first input 211 of memory block 206 and second input 212 of memory block 206 .
  • the specific time period that is set by way of timer 220 is, for example, 10 ms.
  • Memory block 206 encompasses a reset input 213 that can erase the memory cell of memory block 206 .
  • First input 211 of memory block 206 as well as the reset input, indicate the memory state of the memory cell. If a logical “1” is present at the first input of the memory cell, the memory cell is then programmed. If a logical “1” is present at the reset input, the memory cell is then not written to. These two inputs always have inverted states with respect to one another.
  • Memory block 206 furthermore encompasses a first output 214 and a second output 215 which output or indicate, or represent, the state of memory block 206 . If memory block 206 encompasses several memory cells, memory block 206 has either one shared reset input for all memory cells of the memory block, or one respective reset input for each memory cell.
  • FIG. 3 is a block diagram of apparatus 300 for detecting the number of electrostatic discharges, having an evaluation unit 305 .
  • Apparatus 300 encompasses a first terminal 301 and a second terminal 302 , which are electrically connected to a discharge protection device 303 .
  • a detection unit 307 is connected electrically in parallel with discharge protection device 303 .
  • Detection unit 307 encompasses an energy block 304 , an evaluation unit 305 , and a memory block 306 .
  • memory block 306 encompasses at least two memory cells.
  • the purpose of evaluation unit 305 is to evaluate the memory cells during an electrostatic discharge pulse. In other words, evaluation unit 305 can read out the state of the memory cells during an electrostatic discharge pulse. Because several memory cells are present, it is possible to ascertain the number of electrostatic discharge pulses.
  • FIG. 4 is a block diagram of apparatus 400 for detecting two electrostatic discharges.
  • Apparatus 400 has a first input 401 , a second input 402 , a discharge protection device 403 , and an energy block 404 and a memory block 406 .
  • memory block 406 encompasses two memory cells.
  • Apparatus 400 furthermore has a level shifter 421 that is connected in parallel with the first output of energy block 404 and with the second output of energy block 404 .
  • Level shifter 421 furnishes the programming voltage for first input 411 of memory block 406 .
  • the term “programming voltage” is understood here to mean the voltage that is necessary in order to allow a memory cell to be written to.
  • Apparatus 400 furthermore has a voltage divider 422 for generating a voltage for the evaluation unit.
  • the voltage of evaluation unit is in the range of ⁇ 5 V.
  • Apparatus 400 additionally encompasses a circuit 423 for generating a read signal, and a bistable flip-flop 424 for evaluating the state of a memory cell.
  • energy block 404 encompasses a resistor, a Zener diode, a MOSFET transistor connected as a diode, and a capacitor. Energy block 404 converts the voltage that is present at discharge protection device 402 during an ESD pulse into a lower voltage so that the memory cells of memory block 406 can be programmed.
  • the programming voltage is typically 20 V.
  • the output of energy block 404 is connected to a voltage divider 422 for generating the supply voltage of the evaluation unit, the evaluation unit being implemented with the aid of a bistable flip-flop.
  • the evaluation unit controls the programming and evaluation of the memory cells.
  • the evaluation unit requires, for example, a supply voltage of, in particular, 3.5 V.
  • a voltage which generates a logic signal that indicates the state of the memory cell is then applied to a read input of the evaluation unit.
  • the logic signal that represents a read signal must be applied to the flip-flop with a time offset after the supply voltage. This offset in time is generated with the aid of circuit 423 , which is described in more detail in FIG. 5 .
  • the memory cells are evaluated in almost zero-current fashion. This means that there is no load on detection unit 407 , i.e. no current is drawn out of the detection unit.
  • the circuit controls whether the evaluated memory cell is to be programmed or whether a further memory cell needs to be evaluated.
  • the first memory cell, not yet written to, is permanently programmed by way of the programming voltage generated by the energy block. Evaluation of a further memory cell requires a level shifter circuit 421 that is shown in FIG. 6 .
  • FIG. 5 shows the equivalent circuit diagram of block 423 of FIG. 4 .
  • the circuit has a first input 531 , a second input 532 , a first capacitor 533 , a second capacitor 534 , a resistor 535 , a PMOS transistor 536 , an NMOS transistor 537 , a capacitor 538 , a first output 539 , and a second output 540 .
  • first capacitor 533 and second capacitor 534 which are connected to the input of the circuit, it is possible to adjust the length of time needed, in the context of a rising supply voltage at NMOS transistor 537 , to switch PMOS transistor 536 .
  • PMOS transistor 536 connects the supply voltage to the read input of the evaluation circuit.
  • FIG. 6 shows a level shifter circuit 600 for applying the programming voltage to a further memory cell once a first memory cell has been evaluated.
  • Level shifter circuit 600 encompasses a first input 641 , a second input 642 , a PMOS transistor 644 , an NMOS transistor 645 wired as a diode, an NMOS transistor 646 for applying control to PMOS transistor 644 , a filter capacitor 647 , a first output 648 , and a second output 649 .
  • the further memory cell is written to.
  • a fast voltage edge that is applied to first input 641 of level shifter 600 causes a coupling of charge carriers via the blocked PMOS transistor 644 , so that a filter capacitor 647 is needed at first output 648 of level shifter 600 in order to filter that high-frequency interference.
  • NMOS transistor 645 wired as a diode ensures that the programming voltage is discharged via filter capacitor 647 , at the earliest, only after a predefined time.
  • FIG. 7 shows a method 700 for detecting a number of electrostatic discharges.
  • Method 700 begins with detection 710 of a voltage that is present at a discharge protection device. If the voltage exceeds a threshold value that is predefined by the discharge protection device, an input voltage is then generated in a subsequent step 720 and is applied to the detection unit. In other words, upon occurrence of an electrostatic discharge pulse, the discharge protection device reacts so that an input voltage for the detection unit is furnished. The input voltage is reduced in the energy block, for example by way of a voltage divider, so that the voltage within the detection unit protects, or does not destroy, the individual components.
  • the discharge protection device typically reacts above a threshold value of approximately 50 V.
  • That voltage is reduced by way of the discharge protection device to a voltage value of, for example, 20 V. If the threshold value is not exceeded, the method terminates or begins again with step 710 .
  • the switching of the detection unit becomes activated if sufficient voltage is present at the switching. In other words, the remainder of the detection unit, i.e., at least the memory block, becomes activated.
  • a subsequent step 740 at least one memory cell of the memory block is written to.
  • the number of electrostatic discharges is counted or detected, for example by way of a control unit.
  • an evaluation unit can read out the state of at least one memory cell of the memory block during the occurrence of an electrostatic discharge pulse. In other words, all the switching or evaluation operations occur during the occurrence of the electrostatic discharge pulse, which typically has a duration of 100 ns.
  • the evaluation unit can select, depending on the memory state of the memory cells that are present, whether, or which of, the memory cells are to be programmed next or which are to be erased. The memory cell is erased by way of the reset input. Erasure is effected, for example, by the evaluation unit in the normal operating state of the ASIC, once error-free functioning of the ASIC after a detected ESD event has been checked.
  • the check can be made, for example, by way of an additional test routine of a control device. Because the memory cells can be both programmed and erased, the memory cells can be evaluated in coded fashion, e.g. using binary code. All memory cells are programmed, read out, or erased during the electrostatic discharge pulse.

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Elimination Of Static Electricity (AREA)
US16/348,232 2016-11-09 2017-09-12 Device and method for detecting a number of electrostatic discharges Abandoned US20190271728A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102016221925.1 2016-11-09
DE102016221925.1A DE102016221925A1 (de) 2016-11-09 2016-11-09 Vorrichtung und Verfahren zur Detektion einer Anzahl von elektrostatischen Entladungen
PCT/EP2017/072854 WO2018086785A1 (de) 2016-11-09 2017-09-12 Vorrichtung und verfahren zur detektion einer anzahl von elektrostatischen entladungen

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US20190271728A1 true US20190271728A1 (en) 2019-09-05

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US (1) US20190271728A1 (de)
EP (1) EP3538904A1 (de)
JP (1) JP2020513567A (de)
CN (1) CN110178041A (de)
DE (1) DE102016221925A1 (de)
WO (1) WO2018086785A1 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115792416A (zh) * 2022-11-04 2023-03-14 深圳市华众自动化工程有限公司 一种静电检测及消除的装置及方法
US11982707B2 (en) 2021-11-02 2024-05-14 Samsung Electronics Co., Ltd. Semiconductor device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6563319B1 (en) * 1999-04-19 2003-05-13 Credence Technologies, Inc. Electrostatic discharges and transient signals monitoring system and method
US7911748B1 (en) * 2006-09-07 2011-03-22 National Semiconductor Corporation Diffusion capacitor for actively triggered ESD clamp
US8238068B2 (en) * 2009-04-24 2012-08-07 Silicon Laboratories Inc. Electrical over-stress detection circuit
US8922963B2 (en) * 2013-01-30 2014-12-30 Monolithic Power Systems, Inc. Electrostatic discharge protection circuit and method thereof
US20160172849A1 (en) * 2014-12-11 2016-06-16 Infineon Technologies Ag Esd/eos detection
US9871373B2 (en) * 2015-03-27 2018-01-16 Analog Devices Global Electrical overstress recording and/or harvesting
CN105047664B (zh) * 2015-07-09 2018-06-29 武汉新芯集成电路制造有限公司 静电保护电路及3d芯片用静电保护电路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11982707B2 (en) 2021-11-02 2024-05-14 Samsung Electronics Co., Ltd. Semiconductor device
CN115792416A (zh) * 2022-11-04 2023-03-14 深圳市华众自动化工程有限公司 一种静电检测及消除的装置及方法

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WO2018086785A1 (de) 2018-05-17
DE102016221925A1 (de) 2018-05-09
CN110178041A (zh) 2019-08-27
EP3538904A1 (de) 2019-09-18
JP2020513567A (ja) 2020-05-14

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