US20190189811A1 - Photovoltaic device and photovoltaic unit - Google Patents
Photovoltaic device and photovoltaic unit Download PDFInfo
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- US20190189811A1 US20190189811A1 US16/326,182 US201716326182A US2019189811A1 US 20190189811 A1 US20190189811 A1 US 20190189811A1 US 201716326182 A US201716326182 A US 201716326182A US 2019189811 A1 US2019189811 A1 US 2019189811A1
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- H—ELECTRICITY
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022433—Particular geometry of the grid contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02002—Arrangements for conducting electric current to or from the device in operations
- H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
- H01L31/02008—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier for solar cells or solar cell modules
- H01L31/02013—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier for solar cells or solar cell modules comprising output lead wires elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
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- H—ELECTRICITY
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention relates to photovoltaic devices and photovoltaic units.
- the present application claims priority to Japanese Patent Application, Tokugan, No. 2016-159105 filed on Aug. 15, 2016, the entire contents of which are incorporated herein by reference.
- Solar cells are capable of directly converting solar energy to electric energy and increasingly expected as a next-generation energy source, particularly in view of global environmental problems.
- the solar cells that are currently most popularly manufactured and sold have electrodes formed on both sides: a light-receiving face through which sunlight enters the cell and a back face opposite the light-receiving face.
- the electrodes on the light-receiving face reflect and absorb sunlight. Incident light available for conversion decreases by as much as the light that hits the area occupied by the electrodes. Development is therefore underway for a back-contacted solar cell that includes electrodes only on the back face thereof (see, for example, Patent Literature 1).
- Back-contacted solar cells are expected to improve their current collection efficiency.
- the present disclosure in an embodiment thereof, is directed to a photovoltaic device including: a p- or n-type semiconductor substrate; a p-type amorphous semiconductor film on a first-face side of the semiconductor substrate; an n-type amorphous semiconductor film on the first-face side of the semiconductor substrate; p-electrodes on the p-type amorphous semiconductor film; and n-electrodes on the n-type amorphous semiconductor film, wherein: the p-electrodes and the n-electrodes are arranged at intervals; the p-type amorphous semiconductor film surrounds the n-type amorphous semiconductor film in an in-plane direction of the semiconductor substrate; the n-type amorphous semiconductor film has an edge portion providing an overlapping region where the n-type amorphous semiconductor film overlaps the p-type amorphous semiconductor film; and the n-electrodes are disposed in areas of the n-type
- the present disclosure in an embodiment thereof, is directed to a photovoltaic unit including: the photovoltaic device; and a wiring sheet, wherein: the wiring sheet includes an insulating base member, first wires on the insulating base member, and second wires on the insulating base member; the p-electrodes are electrically connected to the first wires; and the n-electrodes are electrically connected to the second wires.
- the present disclosure in an embodiment thereof: can collect current with improved efficiency.
- FIG. 1A is a schematic plan view of a back face of a heterojunction back-contact cell in accordance with Embodiment 1.
- FIG. 1B is a schematic enlarged plan view of the back face of the heterojunction back-contact cell in accordance with Embodiment 1.
- FIG. 2A is a schematic enlarged partial cross-sectional view of the heterojunction back-contact cell in accordance with Embodiment 1 taken along line I-I′.
- FIG. 2B is a schematic enlarged partial cross-sectional view of the heterojunction back-contact cell in accordance with Embodiment 1 taken along line II-II′.
- FIG. 3 is a schematic cross-sectional view illustrating an example method of manufacturing the heterojunction back-contact cell in accordance with Embodiment 1.
- FIG. 4 is a schematic cross-sectional view illustrating the example method of manufacturing the heterojunction back-contact cell in accordance with Embodiment 1.
- FIG. 5 is a schematic cross-sectional view illustrating the example method of manufacturing the heterojunction back-contact cell in accordance with Embodiment 1.
- FIG. 6 is a schematic cross-sectional view illustrating the example method of manufacturing the heterojunction back-contact cell in accordance with Embodiment 1.
- FIG. 7 is a schematic cross-sectional view illustrating the example method of manufacturing the heterojunction back-contact cell in accordance with Embodiment 1.
- FIG. 8 is a schematic cross-sectional view illustrating the example method of manufacturing the heterojunction back-contact cell in accordance with Embodiment 1.
- FIG. 9 is a schematic cross-sectional view illustrating the example method of manufacturing the heterojunction back-contact cell in accordance with Embodiment 1.
- FIG. 10 is a schematic plan view of heterojunction back-contact cells on a wiring sheet in accordance with Embodiment 1.
- FIG. 11 is a schematic plan view of a wiring sheet for use with heterojunction back-contact cells in accordance with Embodiment 1.
- FIG. 12 is a schematic cross-sectional view of a heterojunction back-contact cell complete with a wiring sheet in accordance with Embodiment 1.
- FIG. 13A is a schematic plan view of a back face of a heterojunction back-contact cell in accordance with Embodiment 2.
- FIG. 13B is a schematic enlarged plan view of the back face of the heterojunction back-contact cell in accordance with Embodiment 2.
- FIG. 14 is a schematic cross-sectional view illustrating an example method of removing parts of a first laminate by laser irradiation in Embodiment 3.
- FIG. 15 is a schematic cross-sectional view illustrating an example method of removing parts of a second laminate by laser irradiation in Embodiment 3.
- FIG. 16A is a schematic plan view of a back face of a heterojunction back-contact cell in accordance with Embodiment 4.
- FIG. 16B is a schematic enlarged plan view of the back face of the heterojunction back-contact cell in accordance with Embodiment 4.
- FIG. 17 is a schematic enlarged cross-sectional view of a peripheral part of a heterojunction back-contact cell in accordance with Embodiment 5.
- FIG. 18 is a schematic enlarged cross-sectional view of a peripheral part of a heterojunction back-contact cell in accordance with Embodiment 6.
- FIG. 19 is a schematic enlarged cross-sectional view of a peripheral part of a heterojunction back-contact cell in accordance with Embodiment 7.
- FIG. 20 is a schematic enlarged cross-sectional view of a peripheral part of a heterojunction back-contact cell in accordance with Embodiment 8.
- heterojunction back-contact cells in accordance with Embodiments 1 to 8 as examples of the photovoltaic device in accordance with embodiments of this disclosure and also describe heterojunction back-contact cells complete with a wiring sheet as an example of the photovoltaic unit in accordance with embodiments of this disclosure.
- the same reference numerals in the drawings referred to in the description of embodiments denote identical or equivalent members.
- FIG. 1A is a schematic plan view of a back face of a heterojunction back-contact cell 10 in accordance with Embodiment 1.
- FIG. 1B is a schematic enlarged plan view of the back face of the heterojunction back-contact cell 10 in accordance with Embodiment 1.
- the heterojunction back-contact cell 10 in accordance with Embodiment 1 includes p-electrodes 7 and n-electrodes 8 on the back face of an n-type semiconductor substrate 1 .
- the p-electrodes 7 are disposed on a p-type amorphous semiconductor film 3
- the n-electrodes 8 are disposed on an n-type amorphous semiconductor film 5 .
- the p-electrodes 7 and the n-electrodes 8 are arranged at intervals and extended in the same direction toward the periphery of the n-type semiconductor substrate 1 .
- Each p-electrode 7 is extended toward the periphery of the n-type semiconductor substrate 1 beyond proximate ends 8 a of the adjacent n-electrodes 8 .
- An end 7 a of the p-electrode 7 is separated from the periphery of the n-type semiconductor substrate 1 by a distance L 1 that may be from 0 mm to 1 mm inclusive.
- the end 7 a of the p-electrode 7 is separated from the proximate ends 8 a of the adjacent n-electrodes 8 by a distance L 2 that may be from 0.3 mm to 2 mm inclusive.
- the distance L 1 refers to the shortest distance from the end 7 a of the p-electrode 7 to the periphery of the n-type semiconductor substrate 1 .
- the distance L 2 refers to a difference between the shortest distance from the end 7 a of the p-electrode 7 to the periphery of the n-type semiconductor substrate 1 (L 1 ) and the shortest distance from the proximate end 8 a of the adjacent n-electrode 8 to the periphery of the n-type semiconductor substrate 1 .
- each p-electrode 7 is extended toward the periphery of the n-type semiconductor substrate 1 beyond the ends 8 a of the adjacent n-electrodes 8 , may not be applied, for example, to parts of the n-type semiconductor substrate 1 where alignment and/or other marks exist and to the corners of the substrate 1 where the substrate 1 may have a curved edge.
- FIGS. 1A and 1B show the structure of the p-electrodes 7 and the n-electrodes 8 near an edge of the back face of the heterojunction back-contact cell 10 in accordance with Embodiment 1.
- the p-electrodes 7 and the n-electrodes 8 have the same structure on the opposite edge as the structure shown in FIGS. 1A and 1B . Therefore, neither the p-electrodes 7 nor the n-electrodes 8 are shaped like a comb.
- FIG. 2A is a schematic enlarged partial cross-sectional view of the heterojunction back-contact cell 10 in accordance with Embodiment 1 taken along line I-I′.
- an i-type amorphous semiconductor film 4 and the n-type amorphous semiconductor film 5 are provided in this sequence on parts of the back face (“first face 1 a ”) of the n-type semiconductor substrate 1 .
- an i-type amorphous semiconductor film 2 and the p-type amorphous semiconductor film 3 are provided in this sequence on other parts of the first face 1 a of the n-type semiconductor substrate 1 .
- the p-electrodes 7 are disposed on the p-type amorphous semiconductor film 3 .
- the n-electrodes 8 are disposed on the n-type amorphous semiconductor film 5 .
- the n-type amorphous semiconductor film 5 has an edge portion 5 a thereof located above an edge portion 3 a of the p-type amorphous semiconductor film 3 .
- the i-type amorphous semiconductor film 4 has an edge portion 4 a thereof located between the edge portion 3 a of the p-type amorphous semiconductor film 3 and the edge portion 5 a of the n-type amorphous semiconductor film 5 .
- the edge portion 5 a of the n-type amorphous semiconductor film 5 is an “overlapping region” where the n-type amorphous semiconductor film 5 overlaps the edge portion 3 a of the p-type amorphous semiconductor film 3 .
- FIG. 2B is a schematic cross-sectional view of the heterojunction back-contact cell 10 in accordance with Embodiment 1 taken along line II-II′. Similarly to FIG. 2A , FIG. 2B shows the edge portion 5 a of the n-type amorphous semiconductor film 5 being an overlapping region where the n-type amorphous semiconductor film 5 overlaps the edge portion 3 a of the p-type amorphous semiconductor film 3 .
- the n-type semiconductor substrate 1 has texture or a like irregular structure on a light-receiving face thereof (“second face 1 b ”). There may be provided a dielectric film (not shown) on the second face 1 b of the n-type semiconductor substrate 1 .
- the p-type amorphous semiconductor film 3 surrounds the n-type amorphous semiconductor film 5 in the in-plane direction of the semiconductor substrate as can be understood in FIGS. 1A, 1B, 2A, and 2B .
- the n-electrodes 8 are disposed in the areas of the n-type amorphous semiconductor film 5 that are surrounded by the edge portion 5 a (overlapping region) of the n-type amorphous semiconductor film 5 .
- the n-type semiconductor substrate 1 has texture or a like irregular structure formed on the second face 1 b in advance.
- the i-type amorphous semiconductor film 2 is first formed in such a manner as to come into contact with the entire first face 1 a of the n-type semiconductor substrate 1 .
- the p-type amorphous semiconductor film 3 is then formed in such a manner as to come into contact with an entire face of the i-type amorphous semiconductor film 2 .
- a first laminate 51 is thus formed that is a laminate of the i-type amorphous semiconductor film 2 and the p-type amorphous semiconductor film 3 .
- the i-type amorphous semiconductor film 2 and the p-type amorphous semiconductor film 3 may be formed by any method (e.g., plasma CVD (chemical vapor deposition)).
- the n-type semiconductor substrate 1 is preferably, but not necessarily, an n-type monocrystalline silicon substrate and may be, for example, any conventionally known appropriate n-type semiconductor substrate.
- the i-type amorphous semiconductor film 2 is preferably, but not necessarily, an i-type amorphous silicon film and may be, for example, any conventionally known i-type amorphous semiconductor film.
- the “i-type” semiconductor in the present embodiment does not only refer to a completely intrinsic semiconductor, but also encompasses semiconductors contaminated with an n- or p-type impurity of sufficiently low concentration (both the n-type impurity concentration and the p-type impurity concentration are lower than 1 ⁇ 10 15 atoms/cm 3 ).
- amorphous silicon in the present embodiment does not only refer to amorphous silicon containing silicon atoms with a dangling bond (i.e., an unhydrogenated end), but also encompasses hydrogenated amorphous silicon and other like silicon containing no atoms with a dangling bond.
- the p-type amorphous semiconductor film 3 is preferably, but not necessarily, a p-type amorphous silicon film and may be, for example, any conventionally known p-type amorphous semiconductor film.
- the p-type amorphous semiconductor film 3 may contain, for example, boron as a p-type impurity.
- the “p-type” semiconductor in the present embodiment has a p-type impurity concentration of at least 1 ⁇ 10 15 atoms/cm 3 .
- an etching paste 31 is applied onto the p-type amorphous semiconductor film 3 .
- the etching paste 31 may be any material capable of etching the first laminate 51 .
- the etching paste 31 is then heated to etch out parts of the first laminate 51 in the thickness direction thereof. This etching exposes parts of the first face 1 a of the n-type semiconductor substrate 1 , for example, as shown in FIG. 5 .
- the i-type amorphous semiconductor film 4 is formed so as to come into contact with both the first laminate 51 and the exposed parts of the first face 1 a of the n-type semiconductor substrate 1 as shown in FIG. 6 .
- the n-type amorphous semiconductor film 5 is formed so as to come into contact with an entire face of the i-type amorphous semiconductor film 4 .
- a second laminate 52 is thus formed that is a laminate of the i-type amorphous semiconductor film 4 and the n-type amorphous semiconductor film 5 .
- the i-type amorphous semiconductor film 4 and the n-type amorphous semiconductor film 5 may be formed by any method (e.g., plasma CVD).
- the i-type amorphous semiconductor film 4 is preferably, but not necessarily, an i-type amorphous silicon film and may be, for example, any conventionally known i-type amorphous semiconductor film.
- the n-type amorphous semiconductor film 5 is preferably, but not necessarily, an n-type amorphous silicon film and may be, for example, any conventionally known n-type amorphous semiconductor film.
- the n-type amorphous silicon film constituting the n-type amorphous semiconductor film 5 may contain, for example, phosphorus as an n-type impurity.
- the “n-type” semiconductor in the present embodiment has an n-type impurity concentration of at least 1 ⁇ 10 15 atoms/cm 3 .
- an etching mask 32 is placed on the n-type amorphous semiconductor film 5 .
- the etching mask 32 may be made of any material that is capable of serving as a mask in the etching of the second laminate 52 .
- parts of the second laminate 52 are etched out in the thickness direction thereof using the etching mask 32 as a mask.
- the etching mask 32 is then removed. This etching exposes parts of the surface of the p-type amorphous semiconductor film 3 , for example, as shown in FIG. 8 .
- the p-electrodes 7 are formed on the p-type amorphous semiconductor film 3
- the n-electrodes 8 are formed on the n-type amorphous semiconductor film 5 as shown in FIG. 9 , which completes the manufacture of the heterojunction back-contact cell 10 in accordance with Embodiment 1.
- the p-electrodes 7 and the n-electrodes 8 may be formed, for example, by sputtering using a mask.
- FIG. 10 is a schematic plan view of heterojunction back-contact cells on a wiring sheet in accordance with Embodiment 1.
- the heterojunction back-contact cells complete with a wiring sheet in accordance with Embodiment 1 includes a plurality of electrically series-connected heterojunction back-contact cells 10 in accordance with Embodiment 1 on a wiring sheet 20 , for example, as shown in FIG. 10 .
- FIG. 11 is a schematic plan view of the wiring sheet 20 for use with heterojunction back-contact cells in accordance with Embodiment 1.
- the wiring sheet 20 includes an insulating base member 21 and first wires 22 and second wires 23 provided on the insulating base member 21 . Both the first wires 22 and the second wires 23 are formed like strips arranged at intervals on the insulating base member 21 .
- the first wires 22 and the second wires 23 are arranged alternately in such a manner as to match the lengthwise directions thereof.
- the first wires 22 and the second wires 23 each have an end thereof electrically connected to one of strip-shaped power collection wires 24 .
- the power collection wires 24 are disposed on the insulating base member 21 in such a manner as to have a lengthwise direction perpendicular to the lengthwise direction of the first wires 22 and the second wires 23 .
- the power collection wires 24 collect electric current from the first wires 22 or the second wires 23 and electrically connect the heterojunction back-contact cells 10 in accordance with Embodiment 1 in series.
- the insulating base member 21 may be made of any insulating base material including a film of polyester, polyethylene naphthalate, or polyimide.
- the first wires 22 , the second wires 23 , and the power collection wires 24 may be made of any electrically conductive material including copper.
- the first wires 22 , the second wires 23 , and the power collection wires 24 may be formed, for example, by forming an electrically conductive film, such as a metal film, across the entire surface of the insulating base member 21 and then removing parts of the film (i.e., patterning the film) by etching or a like method.
- FIG. 12 is a schematic cross-sectional view of a heterojunction back-contact cell complete with a wiring sheet in accordance with Embodiment 1.
- the first wires 22 on the wiring sheet 20 are electrically connected via a conductive layer 41 to the n-electrodes 8 in the heterojunction back-contact cell 10 in accordance with Embodiment 1 along the lengthwise directions thereof.
- the second wires 23 on the wiring sheet 20 are electrically connected via the conductive layer 41 to the p-electrodes 7 in the heterojunction back-contact cell 10 in accordance with Embodiment 1 along the lengthwise directions thereof.
- the p-type amorphous semiconductor film 3 surrounds the n-type amorphous semiconductor film 5 in the in-plane direction of the semiconductor substrate, the edge portion 5 a of the n-type amorphous semiconductor film 5 is an overlapping region where the n-type amorphous semiconductor film 5 overlaps the p-type amorphous semiconductor film 3 , and the n-electrodes 8 are disposed in the areas of the n-type amorphous semiconductor film 3 that are surrounded by the overlapping region. Therefore, the n-type semiconductor substrate 1 efficiently collects electric current at the periphery thereof by reducing leakage caused by the unstable shape of the periphery of the n-type semiconductor substrate 1 .
- Embodiment 1 if each p-electrode 7 is extended toward the periphery of the n-type semiconductor substrate 1 beyond the proximate ends 8 a of the adjacent n-electrodes 8 , the end 7 a of the p-electrode 7 is separated from the periphery of the n-type semiconductor substrate 1 by the distance L 1 , which is from 0 mm to 1 mm inclusive, and the end 7 a of the p-electrode 7 is separated from the proximate ends 8 a of the adjacent n-electrodes 8 by the distance L 2 , which is from 0.3 mm to 2 mm inclusive, the p-electrodes 7 can collect current with improved efficiency, and improper patterning of electrodes (e.g., the n-electrodes 8 extending beyond the periphery of the n-type semiconductor substrate 1 ) becomes less likely to occur.
- L 1 which is from 0 mm to 1 mm inclusive
- FIG. 13A is a schematic plan view of a back face of a heterojunction back-contact cell 10 in accordance with Embodiment 2.
- FIG. 13B is a schematic enlarged plan view of the back face of the heterojunction back-contact cell 10 in accordance with Embodiment 2.
- the heterojunction back-contact cell 10 in accordance with Embodiment 2 is characterized in that the p-electrodes 7 have, near the periphery of the n-type semiconductor substrate 1 , an end 7 b where the p-electrodes 7 are broadened in a direction that differs from the extension direction of the p-electrodes 7 . Since the p-electrodes 7 are not shaped like a comb, adjacent ends 7 b of the p-electrodes 7 are separated by a distance from each other.
- Embodiment 2 is the same as Embodiment 1 unless explicitly stated above. No such description is repeated here.
- a heterojunction back-contact cell 10 in accordance with Embodiment 3 is characterized in that the first laminate 51 and the second laminate 52 are partially removed under laser radiation instead of using the etching paste 31 and the etching mask 32 respectively.
- FIG. 14 is a schematic cross-sectional view illustrating an example method of removing parts of the first laminate 51 by laser irradiation.
- laser light 61 is shone onto parts of the p-type amorphous semiconductor film 3 in the first laminate 51 to heat and evaporate the parts of the first laminate 51 .
- the first laminate 51 is thus partially removed.
- FIG. 15 is a schematic cross-sectional view illustrating an example method of removing parts of the second laminate 52 by laser irradiation.
- laser light 62 is shone onto parts of the n-type amorphous semiconductor film 5 in the second laminate 52 to heat and evaporate the parts of the second laminate 52 .
- the second laminate 52 is thus partially removed.
- Embodiment 3 is the same as Embodiments 1 and 2 unless explicitly stated above. No such description is repeated here.
- FIG. 16A is a schematic plan view of a back face of a heterojunction back-contact cell 10 in accordance with Embodiment 4.
- FIG. 16B is a schematic enlarged plan view of the back face of the heterojunction back-contact cell 10 in accordance with Embodiment 4.
- the heterojunction back-contact cell 10 in accordance with Embodiment 4 is characterized in that the ends 7 a of the p-electrodes 7 near the periphery of the n-type semiconductor substrate 1 are aligned with the ends 8 a of the n-electrodes 8 near the periphery of the n-type semiconductor substrate 1 .
- Embodiment 4 is the same as Embodiments 1 to 3 unless explicitly stated above. No such description is repeated here.
- FIG. 17 is a schematic enlarged cross-sectional view of a peripheral part of a heterojunction back-contact cell 10 in accordance with Embodiment 5.
- the i-type amorphous semiconductor film 4 and the n-type amorphous semiconductor film 5 are extended covering all the way from the second face 1 a (i.e., light-receiving face) to a side face 1 c of the n-type semiconductor substrate 1
- the i-type amorphous semiconductor film 2 and the p-type amorphous semiconductor film 3 are extended covering all the way from the first face 1 b (i.e., back face) to the side face 1 c of the n-type semiconductor substrate 1 .
- the heterojunction back-contact cell 10 in accordance with Embodiment 5 is characterized in that the p-electrodes 7 are extended short of reaching the side face 1 c of the n-type semiconductor substrate 1 and that the i-type amorphous semiconductor film 2 reaches beyond the i-type amorphous semiconductor film 4 .
- Embodiment 5 is the same as Embodiments 1 to 4 unless explicitly stated above. No such description is repeated here.
- FIG. 18 is a schematic enlarged cross-sectional view of a peripheral part of a heterojunction back-contact cell 10 in accordance with Embodiment 6.
- the heterojunction back-contact cell 10 in accordance with Embodiment 6 is characterized in that the p-electrodes 7 are extended short of reaching the side face 1 c of the n-type semiconductor substrate 1 and that the i-type amorphous semiconductor film 4 reaches beyond the i-type amorphous semiconductor film 2 .
- Embodiment 6 is the same as Embodiments 1 to 5 unless explicitly stated above. No such description is repeated here.
- FIG. 19 is a schematic enlarged cross-sectional view of a peripheral part of a heterojunction back-contact cell 10 in accordance with Embodiment 7.
- the heterojunction back-contact cell 10 in accordance with Embodiment 7 is characterized in that the ends 7 a of the p-electrodes 7 are aligned with the side face 1 c of the n-type semiconductor substrate 1 and that the i-type amorphous semiconductor film 2 reaches beyond the i-type amorphous semiconductor film 4 .
- Embodiment 7 is the same as Embodiments 1 to 6 unless explicitly stated above. No such description is repeated here.
- FIG. 20 is a schematic enlarged cross-sectional view of a peripheral part of a heterojunction back-contact cell 10 in accordance with Embodiment 8.
- the heterojunction back-contact cell 10 in accordance with Embodiment 8 is characterized in that the ends 7 a of the p-electrodes 7 are aligned with the side face 1 c of the n-type semiconductor substrate 1 and that the i-type amorphous semiconductor film 4 reaches beyond the i-type amorphous semiconductor film 2 .
- Embodiment 8 is the same as Embodiments 1 to 7 unless explicitly stated above. No such description is repeated here.
- the present disclosure in an embodiment thereof, is directed to a photovoltaic device including: a p- or n-type semiconductor substrate; a p-type amorphous semiconductor film on a first-face side of the semiconductor substrate; an n-type amorphous semiconductor film on the first-face side of the semiconductor substrate; p-electrodes on the p-type amorphous semiconductor film; and n-electrodes on the n-type amorphous semiconductor film, wherein: the p-electrodes and the n-electrodes are arranged at intervals; the p-type amorphous semiconductor film surrounds the n-type amorphous semiconductor film in an in-plane direction of the semiconductor substrate; the n-type amorphous semiconductor film has an edge portion providing an overlapping region where the n-type amorphous semiconductor film overlaps the p-type amorphous semiconductor film; and the n-electrodes are disposed in areas of the n-
- the p-type amorphous semiconductor film may be extended so as to cover a side face of the semiconductor substrate.
- the p-electrodes may be extended closer to a periphery of the semiconductor substrate than are those n-electrodes that are adjacent to the p-electrodes.
- the p-electrodes may have ends thereof separated from the semiconductor substrate by a distance of from 0 mm to 1 mm inclusive.
- the p-electrodes may have ends thereof separated from proximate ends of the n-electrodes by a distance of from 0.3 mm to 2 mm inclusive.
- the p-electrodes may have, near a periphery of the semiconductor substrate, ends thereof where the p-electrodes are broadened in a direction that differs from an extension direction of the p-electrodes.
- the p-electrodes and the n-electrodes may be extended in a single direction.
- the p-electrodes and the n-electrodes may be arranged like islands.
- the present disclosure in an embodiment thereof, is directed to a photovoltaic unit including: any one of the foregoing photovoltaic devices; and a wiring sheet, wherein: the wiring sheet includes an insulating base member, first wires on the insulating base member, and second wires on the insulating base member; the p-electrodes are electrically connected to the first wires; and the n-electrodes are electrically connected to the second wires.
- the embodiments in this disclosure are applicable to photovoltaic devices and photovoltaic units and may be preferably applicable to solar cells, methods of manufacturing solar cells, and solar cell modules, in particular, to heterojunction back-contact cells and heterojunction back-contact cells complete with a wiring sheet.
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Abstract
Description
- The present invention relates to photovoltaic devices and photovoltaic units. The present application claims priority to Japanese Patent Application, Tokugan, No. 2016-159105 filed on Aug. 15, 2016, the entire contents of which are incorporated herein by reference.
- Solar cells are capable of directly converting solar energy to electric energy and increasingly expected as a next-generation energy source, particularly in view of global environmental problems. The solar cells that are currently most popularly manufactured and sold have electrodes formed on both sides: a light-receiving face through which sunlight enters the cell and a back face opposite the light-receiving face.
- The electrodes on the light-receiving face, however, reflect and absorb sunlight. Incident light available for conversion decreases by as much as the light that hits the area occupied by the electrodes. Development is therefore underway for a back-contacted solar cell that includes electrodes only on the back face thereof (see, for example, Patent Literature 1).
-
- Patent Literature 1: PCT International Application Publication No. WO2013/027591
- Back-contacted solar cells are expected to improve their current collection efficiency.
- The present disclosure, in an embodiment thereof, is directed to a photovoltaic device including: a p- or n-type semiconductor substrate; a p-type amorphous semiconductor film on a first-face side of the semiconductor substrate; an n-type amorphous semiconductor film on the first-face side of the semiconductor substrate; p-electrodes on the p-type amorphous semiconductor film; and n-electrodes on the n-type amorphous semiconductor film, wherein: the p-electrodes and the n-electrodes are arranged at intervals; the p-type amorphous semiconductor film surrounds the n-type amorphous semiconductor film in an in-plane direction of the semiconductor substrate; the n-type amorphous semiconductor film has an edge portion providing an overlapping region where the n-type amorphous semiconductor film overlaps the p-type amorphous semiconductor film; and the n-electrodes are disposed in areas of the n-type amorphous semiconductor film that are surrounded by the overlapping region.
- The present disclosure, in an embodiment thereof, is directed to a photovoltaic unit including: the photovoltaic device; and a wiring sheet, wherein: the wiring sheet includes an insulating base member, first wires on the insulating base member, and second wires on the insulating base member; the p-electrodes are electrically connected to the first wires; and the n-electrodes are electrically connected to the second wires.
- The present disclosure, in an embodiment thereof: can collect current with improved efficiency.
-
FIG. 1A is a schematic plan view of a back face of a heterojunction back-contact cell in accordance withEmbodiment 1. -
FIG. 1B is a schematic enlarged plan view of the back face of the heterojunction back-contact cell in accordance withEmbodiment 1. -
FIG. 2A is a schematic enlarged partial cross-sectional view of the heterojunction back-contact cell in accordance withEmbodiment 1 taken along line I-I′. -
FIG. 2B is a schematic enlarged partial cross-sectional view of the heterojunction back-contact cell in accordance withEmbodiment 1 taken along line II-II′. -
FIG. 3 is a schematic cross-sectional view illustrating an example method of manufacturing the heterojunction back-contact cell in accordance withEmbodiment 1. -
FIG. 4 is a schematic cross-sectional view illustrating the example method of manufacturing the heterojunction back-contact cell in accordance withEmbodiment 1. -
FIG. 5 is a schematic cross-sectional view illustrating the example method of manufacturing the heterojunction back-contact cell in accordance withEmbodiment 1. -
FIG. 6 is a schematic cross-sectional view illustrating the example method of manufacturing the heterojunction back-contact cell in accordance withEmbodiment 1. -
FIG. 7 is a schematic cross-sectional view illustrating the example method of manufacturing the heterojunction back-contact cell in accordance withEmbodiment 1. -
FIG. 8 is a schematic cross-sectional view illustrating the example method of manufacturing the heterojunction back-contact cell in accordance withEmbodiment 1. -
FIG. 9 is a schematic cross-sectional view illustrating the example method of manufacturing the heterojunction back-contact cell in accordance withEmbodiment 1. -
FIG. 10 is a schematic plan view of heterojunction back-contact cells on a wiring sheet in accordance withEmbodiment 1. -
FIG. 11 is a schematic plan view of a wiring sheet for use with heterojunction back-contact cells in accordance withEmbodiment 1. -
FIG. 12 is a schematic cross-sectional view of a heterojunction back-contact cell complete with a wiring sheet in accordance withEmbodiment 1. -
FIG. 13A is a schematic plan view of a back face of a heterojunction back-contact cell in accordance withEmbodiment 2. -
FIG. 13B is a schematic enlarged plan view of the back face of the heterojunction back-contact cell in accordance withEmbodiment 2. -
FIG. 14 is a schematic cross-sectional view illustrating an example method of removing parts of a first laminate by laser irradiation inEmbodiment 3. -
FIG. 15 is a schematic cross-sectional view illustrating an example method of removing parts of a second laminate by laser irradiation inEmbodiment 3. -
FIG. 16A is a schematic plan view of a back face of a heterojunction back-contact cell in accordance withEmbodiment 4. -
FIG. 16B is a schematic enlarged plan view of the back face of the heterojunction back-contact cell in accordance withEmbodiment 4. -
FIG. 17 is a schematic enlarged cross-sectional view of a peripheral part of a heterojunction back-contact cell in accordance withEmbodiment 5. -
FIG. 18 is a schematic enlarged cross-sectional view of a peripheral part of a heterojunction back-contact cell in accordance with Embodiment 6. -
FIG. 19 is a schematic enlarged cross-sectional view of a peripheral part of a heterojunction back-contact cell in accordance withEmbodiment 7. -
FIG. 20 is a schematic enlarged cross-sectional view of a peripheral part of a heterojunction back-contact cell in accordance withEmbodiment 8. - The following will describe heterojunction back-contact cells in accordance with
Embodiments 1 to 8 as examples of the photovoltaic device in accordance with embodiments of this disclosure and also describe heterojunction back-contact cells complete with a wiring sheet as an example of the photovoltaic unit in accordance with embodiments of this disclosure. The same reference numerals in the drawings referred to in the description of embodiments denote identical or equivalent members. -
FIG. 1A is a schematic plan view of a back face of a heterojunction back-contact cell 10 in accordance withEmbodiment 1.FIG. 1B is a schematic enlarged plan view of the back face of the heterojunction back-contact cell 10 in accordance withEmbodiment 1. Referring toFIGS. 1A and 1B , the heterojunction back-contact cell 10 in accordance withEmbodiment 1 includes p-electrodes 7 and n-electrodes 8 on the back face of an n-type semiconductor substrate 1. The p-electrodes 7 are disposed on a p-typeamorphous semiconductor film 3, and the n-electrodes 8 are disposed on an n-typeamorphous semiconductor film 5. The p-electrodes 7 and the n-electrodes 8, each shaped like a rectangular island, are arranged at intervals and extended in the same direction toward the periphery of the n-type semiconductor substrate 1. Each p-electrode 7 is extended toward the periphery of the n-type semiconductor substrate 1 beyondproximate ends 8 a of the adjacent n-electrodes 8. Anend 7 a of the p-electrode 7 is separated from the periphery of the n-type semiconductor substrate 1 by a distance L1 that may be from 0 mm to 1 mm inclusive. Theend 7 a of the p-electrode 7 is separated from the proximate ends 8 a of the adjacent n-electrodes 8 by a distance L2 that may be from 0.3 mm to 2 mm inclusive. The distance L1 refers to the shortest distance from theend 7 a of the p-electrode 7 to the periphery of the n-type semiconductor substrate 1. The distance L2 refers to a difference between the shortest distance from theend 7 a of the p-electrode 7 to the periphery of the n-type semiconductor substrate 1 (L1) and the shortest distance from theproximate end 8 a of the adjacent n-electrode 8 to the periphery of the n-type semiconductor substrate 1. - This structure, in which each p-
electrode 7 is extended toward the periphery of the n-type semiconductor substrate 1 beyond theends 8 a of the adjacent n-electrodes 8, may not be applied, for example, to parts of the n-type semiconductor substrate 1 where alignment and/or other marks exist and to the corners of thesubstrate 1 where thesubstrate 1 may have a curved edge. -
FIGS. 1A and 1B show the structure of the p-electrodes 7 and the n-electrodes 8 near an edge of the back face of the heterojunction back-contact cell 10 in accordance withEmbodiment 1. The p-electrodes 7 and the n-electrodes 8 have the same structure on the opposite edge as the structure shown inFIGS. 1A and 1B . Therefore, neither the p-electrodes 7 nor the n-electrodes 8 are shaped like a comb. -
FIG. 2A is a schematic enlarged partial cross-sectional view of the heterojunction back-contact cell 10 in accordance withEmbodiment 1 taken along line I-I′. Referring toFIG. 2A , an i-typeamorphous semiconductor film 4 and the n-typeamorphous semiconductor film 5 are provided in this sequence on parts of the back face (“first face 1 a”) of the n-type semiconductor substrate 1. Meanwhile, an i-typeamorphous semiconductor film 2 and the p-typeamorphous semiconductor film 3 are provided in this sequence on other parts of thefirst face 1 a of the n-type semiconductor substrate 1. The p-electrodes 7 are disposed on the p-typeamorphous semiconductor film 3. The n-electrodes 8 are disposed on the n-typeamorphous semiconductor film 5. There may be no i-typeamorphous semiconductor film 4 between the n-type semiconductor substrate 1 and the n-typeamorphous semiconductor film 5. There may be no i-typeamorphous semiconductor film 2 between the n-type semiconductor substrate 1 and the p-typeamorphous semiconductor film 3. - Still referring to
FIG. 2A , the n-typeamorphous semiconductor film 5 has anedge portion 5 a thereof located above anedge portion 3 a of the p-typeamorphous semiconductor film 3. The i-typeamorphous semiconductor film 4 has anedge portion 4 a thereof located between theedge portion 3 a of the p-typeamorphous semiconductor film 3 and theedge portion 5 a of the n-typeamorphous semiconductor film 5. Theedge portion 5 a of the n-typeamorphous semiconductor film 5 is an “overlapping region” where the n-typeamorphous semiconductor film 5 overlaps theedge portion 3 a of the p-typeamorphous semiconductor film 3. -
FIG. 2B is a schematic cross-sectional view of the heterojunction back-contact cell 10 in accordance withEmbodiment 1 taken along line II-II′. Similarly toFIG. 2A ,FIG. 2B shows theedge portion 5 a of the n-typeamorphous semiconductor film 5 being an overlapping region where the n-typeamorphous semiconductor film 5 overlaps theedge portion 3 a of the p-typeamorphous semiconductor film 3. - Referring to
FIGS. 2A and 2B , the n-type semiconductor substrate 1 has texture or a like irregular structure on a light-receiving face thereof (“second face 1 b”). There may be provided a dielectric film (not shown) on thesecond face 1 b of the n-type semiconductor substrate 1. - The p-type
amorphous semiconductor film 3 surrounds the n-typeamorphous semiconductor film 5 in the in-plane direction of the semiconductor substrate as can be understood inFIGS. 1A, 1B, 2A, and 2B . The n-electrodes 8 are disposed in the areas of the n-typeamorphous semiconductor film 5 that are surrounded by theedge portion 5 a (overlapping region) of the n-typeamorphous semiconductor film 5. - The following will describe an example method of manufacturing of the heterojunction back-
contact cell 10 in accordance withEmbodiment 1 in reference to the schematic cross-sectional views inFIGS. 3 to 9 . The n-type semiconductor substrate 1 has texture or a like irregular structure formed on thesecond face 1 b in advance. As shown inFIG. 3 , the i-typeamorphous semiconductor film 2 is first formed in such a manner as to come into contact with the entirefirst face 1 a of the n-type semiconductor substrate 1. The p-typeamorphous semiconductor film 3 is then formed in such a manner as to come into contact with an entire face of the i-typeamorphous semiconductor film 2. Afirst laminate 51 is thus formed that is a laminate of the i-typeamorphous semiconductor film 2 and the p-typeamorphous semiconductor film 3. The i-typeamorphous semiconductor film 2 and the p-typeamorphous semiconductor film 3 may be formed by any method (e.g., plasma CVD (chemical vapor deposition)). - The n-
type semiconductor substrate 1 is preferably, but not necessarily, an n-type monocrystalline silicon substrate and may be, for example, any conventionally known appropriate n-type semiconductor substrate. - The i-type
amorphous semiconductor film 2 is preferably, but not necessarily, an i-type amorphous silicon film and may be, for example, any conventionally known i-type amorphous semiconductor film. - The “i-type” semiconductor in the present embodiment does not only refer to a completely intrinsic semiconductor, but also encompasses semiconductors contaminated with an n- or p-type impurity of sufficiently low concentration (both the n-type impurity concentration and the p-type impurity concentration are lower than 1×1015 atoms/cm3).
- The “amorphous silicon” in the present embodiment does not only refer to amorphous silicon containing silicon atoms with a dangling bond (i.e., an unhydrogenated end), but also encompasses hydrogenated amorphous silicon and other like silicon containing no atoms with a dangling bond.
- The p-type
amorphous semiconductor film 3 is preferably, but not necessarily, a p-type amorphous silicon film and may be, for example, any conventionally known p-type amorphous semiconductor film. - The p-type
amorphous semiconductor film 3 may contain, for example, boron as a p-type impurity. The “p-type” semiconductor in the present embodiment has a p-type impurity concentration of at least 1×1015 atoms/cm3. - Next, as shown in
FIG. 4 , an etching paste 31 is applied onto the p-typeamorphous semiconductor film 3. The etching paste 31 may be any material capable of etching thefirst laminate 51. - The etching paste 31 is then heated to etch out parts of the
first laminate 51 in the thickness direction thereof. This etching exposes parts of thefirst face 1 a of the n-type semiconductor substrate 1, for example, as shown inFIG. 5 . - Subsequently, the i-type
amorphous semiconductor film 4 is formed so as to come into contact with both thefirst laminate 51 and the exposed parts of thefirst face 1 a of the n-type semiconductor substrate 1 as shown inFIG. 6 . Thereafter, the n-typeamorphous semiconductor film 5 is formed so as to come into contact with an entire face of the i-typeamorphous semiconductor film 4. Asecond laminate 52 is thus formed that is a laminate of the i-typeamorphous semiconductor film 4 and the n-typeamorphous semiconductor film 5. The i-typeamorphous semiconductor film 4 and the n-typeamorphous semiconductor film 5 may be formed by any method (e.g., plasma CVD). - The i-type
amorphous semiconductor film 4 is preferably, but not necessarily, an i-type amorphous silicon film and may be, for example, any conventionally known i-type amorphous semiconductor film. - The n-type
amorphous semiconductor film 5 is preferably, but not necessarily, an n-type amorphous silicon film and may be, for example, any conventionally known n-type amorphous semiconductor film. - The n-type amorphous silicon film constituting the n-type
amorphous semiconductor film 5 may contain, for example, phosphorus as an n-type impurity. The “n-type” semiconductor in the present embodiment has an n-type impurity concentration of at least 1×1015 atoms/cm3. - Next, as shown in
FIG. 7 , anetching mask 32 is placed on the n-typeamorphous semiconductor film 5. Theetching mask 32 may be made of any material that is capable of serving as a mask in the etching of thesecond laminate 52. - Next, parts of the
second laminate 52 are etched out in the thickness direction thereof using theetching mask 32 as a mask. Theetching mask 32 is then removed. This etching exposes parts of the surface of the p-typeamorphous semiconductor film 3, for example, as shown inFIG. 8 . - Thereafter, the p-
electrodes 7 are formed on the p-typeamorphous semiconductor film 3, and the n-electrodes 8 are formed on the n-typeamorphous semiconductor film 5 as shown inFIG. 9 , which completes the manufacture of the heterojunction back-contact cell 10 in accordance withEmbodiment 1. The p-electrodes 7 and the n-electrodes 8 may be formed, for example, by sputtering using a mask. - Heterojunction Back-Contact Cell Complete with Wiring Sheet
-
FIG. 10 is a schematic plan view of heterojunction back-contact cells on a wiring sheet in accordance withEmbodiment 1. The heterojunction back-contact cells complete with a wiring sheet in accordance withEmbodiment 1 includes a plurality of electrically series-connected heterojunction back-contact cells 10 in accordance withEmbodiment 1 on awiring sheet 20, for example, as shown inFIG. 10 . -
FIG. 11 is a schematic plan view of thewiring sheet 20 for use with heterojunction back-contact cells in accordance withEmbodiment 1. Thewiring sheet 20 includes an insulatingbase member 21 andfirst wires 22 andsecond wires 23 provided on the insulatingbase member 21. Both thefirst wires 22 and thesecond wires 23 are formed like strips arranged at intervals on the insulatingbase member 21. Thefirst wires 22 and thesecond wires 23 are arranged alternately in such a manner as to match the lengthwise directions thereof. Thefirst wires 22 and thesecond wires 23 each have an end thereof electrically connected to one of strip-shapedpower collection wires 24. Thepower collection wires 24 are disposed on the insulatingbase member 21 in such a manner as to have a lengthwise direction perpendicular to the lengthwise direction of thefirst wires 22 and thesecond wires 23. Thepower collection wires 24 collect electric current from thefirst wires 22 or thesecond wires 23 and electrically connect the heterojunction back-contact cells 10 in accordance withEmbodiment 1 in series. - The insulating
base member 21 may be made of any insulating base material including a film of polyester, polyethylene naphthalate, or polyimide. - The
first wires 22, thesecond wires 23, and thepower collection wires 24 may be made of any electrically conductive material including copper. Thefirst wires 22, thesecond wires 23, and thepower collection wires 24 may be formed, for example, by forming an electrically conductive film, such as a metal film, across the entire surface of the insulatingbase member 21 and then removing parts of the film (i.e., patterning the film) by etching or a like method. -
FIG. 12 is a schematic cross-sectional view of a heterojunction back-contact cell complete with a wiring sheet in accordance withEmbodiment 1. Referring toFIG. 12 , thefirst wires 22 on thewiring sheet 20 are electrically connected via aconductive layer 41 to the n-electrodes 8 in the heterojunction back-contact cell 10 in accordance withEmbodiment 1 along the lengthwise directions thereof. Meanwhile, thesecond wires 23 on thewiring sheet 20 are electrically connected via theconductive layer 41 to the p-electrodes 7 in the heterojunction back-contact cell 10 in accordance withEmbodiment 1 along the lengthwise directions thereof. - In
Embodiment 1, the p-typeamorphous semiconductor film 3 surrounds the n-typeamorphous semiconductor film 5 in the in-plane direction of the semiconductor substrate, theedge portion 5 a of the n-typeamorphous semiconductor film 5 is an overlapping region where the n-typeamorphous semiconductor film 5 overlaps the p-typeamorphous semiconductor film 3, and the n-electrodes 8 are disposed in the areas of the n-typeamorphous semiconductor film 3 that are surrounded by the overlapping region. Therefore, the n-type semiconductor substrate 1 efficiently collects electric current at the periphery thereof by reducing leakage caused by the unstable shape of the periphery of the n-type semiconductor substrate 1. - In
Embodiment 1, if each p-electrode 7 is extended toward the periphery of the n-type semiconductor substrate 1 beyond the proximate ends 8 a of the adjacent n-electrodes 8, theend 7 a of the p-electrode 7 is separated from the periphery of the n-type semiconductor substrate 1 by the distance L1, which is from 0 mm to 1 mm inclusive, and theend 7 a of the p-electrode 7 is separated from the proximate ends 8 a of the adjacent n-electrodes 8 by the distance L2, which is from 0.3 mm to 2 mm inclusive, the p-electrodes 7 can collect current with improved efficiency, and improper patterning of electrodes (e.g., the n-electrodes 8 extending beyond the periphery of the n-type semiconductor substrate 1) becomes less likely to occur. -
FIG. 13A is a schematic plan view of a back face of a heterojunction back-contact cell 10 in accordance withEmbodiment 2.FIG. 13B is a schematic enlarged plan view of the back face of the heterojunction back-contact cell 10 in accordance withEmbodiment 2. Referring toFIGS. 13A and 13B , the heterojunction back-contact cell 10 in accordance withEmbodiment 2 is characterized in that the p-electrodes 7 have, near the periphery of the n-type semiconductor substrate 1, anend 7 b where the p-electrodes 7 are broadened in a direction that differs from the extension direction of the p-electrodes 7. Since the p-electrodes 7 are not shaped like a comb, adjacent ends 7 b of the p-electrodes 7 are separated by a distance from each other. -
Embodiment 2 is the same asEmbodiment 1 unless explicitly stated above. No such description is repeated here. - A heterojunction back-
contact cell 10 in accordance withEmbodiment 3 is characterized in that thefirst laminate 51 and thesecond laminate 52 are partially removed under laser radiation instead of using the etching paste 31 and theetching mask 32 respectively. -
FIG. 14 is a schematic cross-sectional view illustrating an example method of removing parts of thefirst laminate 51 by laser irradiation. Referring toFIG. 14 ,laser light 61 is shone onto parts of the p-typeamorphous semiconductor film 3 in thefirst laminate 51 to heat and evaporate the parts of thefirst laminate 51. Thefirst laminate 51 is thus partially removed. -
FIG. 15 is a schematic cross-sectional view illustrating an example method of removing parts of thesecond laminate 52 by laser irradiation. Referring toFIG. 15 ,laser light 62 is shone onto parts of the n-typeamorphous semiconductor film 5 in thesecond laminate 52 to heat and evaporate the parts of thesecond laminate 52. Thesecond laminate 52 is thus partially removed. -
Embodiment 3 is the same asEmbodiments -
FIG. 16A is a schematic plan view of a back face of a heterojunction back-contact cell 10 in accordance withEmbodiment 4.FIG. 16B is a schematic enlarged plan view of the back face of the heterojunction back-contact cell 10 in accordance withEmbodiment 4. The heterojunction back-contact cell 10 in accordance withEmbodiment 4 is characterized in that theends 7 a of the p-electrodes 7 near the periphery of the n-type semiconductor substrate 1 are aligned with theends 8 a of the n-electrodes 8 near the periphery of the n-type semiconductor substrate 1. -
Embodiment 4 is the same asEmbodiments 1 to 3 unless explicitly stated above. No such description is repeated here. -
FIG. 17 is a schematic enlarged cross-sectional view of a peripheral part of a heterojunction back-contact cell 10 in accordance withEmbodiment 5. In the heterojunction back-contact cell 10 in accordance withEmbodiment 5, the i-typeamorphous semiconductor film 4 and the n-typeamorphous semiconductor film 5 are extended covering all the way from thesecond face 1 a (i.e., light-receiving face) to a side face 1 c of the n-type semiconductor substrate 1, and the i-typeamorphous semiconductor film 2 and the p-typeamorphous semiconductor film 3 are extended covering all the way from thefirst face 1 b (i.e., back face) to the side face 1 c of the n-type semiconductor substrate 1. - The heterojunction back-
contact cell 10 in accordance withEmbodiment 5 is characterized in that the p-electrodes 7 are extended short of reaching the side face 1 c of the n-type semiconductor substrate 1 and that the i-typeamorphous semiconductor film 2 reaches beyond the i-typeamorphous semiconductor film 4. -
Embodiment 5 is the same asEmbodiments 1 to 4 unless explicitly stated above. No such description is repeated here. -
FIG. 18 is a schematic enlarged cross-sectional view of a peripheral part of a heterojunction back-contact cell 10 in accordance with Embodiment 6. The heterojunction back-contact cell 10 in accordance with Embodiment 6 is characterized in that the p-electrodes 7 are extended short of reaching the side face 1 c of the n-type semiconductor substrate 1 and that the i-typeamorphous semiconductor film 4 reaches beyond the i-typeamorphous semiconductor film 2. - Embodiment 6 is the same as
Embodiments 1 to 5 unless explicitly stated above. No such description is repeated here. -
FIG. 19 is a schematic enlarged cross-sectional view of a peripheral part of a heterojunction back-contact cell 10 in accordance withEmbodiment 7. The heterojunction back-contact cell 10 in accordance withEmbodiment 7 is characterized in that theends 7 a of the p-electrodes 7 are aligned with the side face 1 c of the n-type semiconductor substrate 1 and that the i-typeamorphous semiconductor film 2 reaches beyond the i-typeamorphous semiconductor film 4. -
Embodiment 7 is the same asEmbodiments 1 to 6 unless explicitly stated above. No such description is repeated here. -
FIG. 20 is a schematic enlarged cross-sectional view of a peripheral part of a heterojunction back-contact cell 10 in accordance withEmbodiment 8. The heterojunction back-contact cell 10 in accordance withEmbodiment 8 is characterized in that theends 7 a of the p-electrodes 7 are aligned with the side face 1 c of the n-type semiconductor substrate 1 and that the i-typeamorphous semiconductor film 4 reaches beyond the i-typeamorphous semiconductor film 2. -
Embodiment 8 is the same asEmbodiments 1 to 7 unless explicitly stated above. No such description is repeated here. - (1) The present disclosure, in an embodiment thereof, is directed to a photovoltaic device including: a p- or n-type semiconductor substrate; a p-type amorphous semiconductor film on a first-face side of the semiconductor substrate; an n-type amorphous semiconductor film on the first-face side of the semiconductor substrate; p-electrodes on the p-type amorphous semiconductor film; and n-electrodes on the n-type amorphous semiconductor film, wherein: the p-electrodes and the n-electrodes are arranged at intervals; the p-type amorphous semiconductor film surrounds the n-type amorphous semiconductor film in an in-plane direction of the semiconductor substrate; the n-type amorphous semiconductor film has an edge portion providing an overlapping region where the n-type amorphous semiconductor film overlaps the p-type amorphous semiconductor film; and the n-electrodes are disposed in areas of the n-type amorphous semiconductor film that are surrounded by the overlapping region.
- (2) In the photovoltaic device of an embodiment disclosed here, the p-type amorphous semiconductor film may be extended so as to cover a side face of the semiconductor substrate.
- (3) In the photovoltaic device of an embodiment disclosed here, the p-electrodes may be extended closer to a periphery of the semiconductor substrate than are those n-electrodes that are adjacent to the p-electrodes. The p-electrodes may have ends thereof separated from the semiconductor substrate by a distance of from 0 mm to 1 mm inclusive. The p-electrodes may have ends thereof separated from proximate ends of the n-electrodes by a distance of from 0.3 mm to 2 mm inclusive.
- (4) In the photovoltaic device of an embodiment disclosed here, the p-electrodes may have, near a periphery of the semiconductor substrate, ends thereof where the p-electrodes are broadened in a direction that differs from an extension direction of the p-electrodes.
- (5) In the photovoltaic device of an embodiment disclosed here, the p-electrodes and the n-electrodes may be extended in a single direction.
- (6) In the photovoltaic device of an embodiment disclosed here, the p-electrodes and the n-electrodes may be arranged like islands.
- (7) The present disclosure, in an embodiment thereof, is directed to a photovoltaic unit including: any one of the foregoing photovoltaic devices; and a wiring sheet, wherein: the wiring sheet includes an insulating base member, first wires on the insulating base member, and second wires on the insulating base member; the p-electrodes are electrically connected to the first wires; and the n-electrodes are electrically connected to the second wires.
- It is envisaged that the embodiments described in the foregoing may be combined where appropriate.
- The embodiments and examples disclosed herein are for illustrative purposes only in every respect and provide no basis for restrictive interpretations. The scope of the present invention is defined only by the claims and never bound by the embodiments or examples. Those modifications and variations that may lead to equivalents of claimed elements are all included within the scope of the invention.
- The embodiments in this disclosure are applicable to photovoltaic devices and photovoltaic units and may be preferably applicable to solar cells, methods of manufacturing solar cells, and solar cell modules, in particular, to heterojunction back-contact cells and heterojunction back-contact cells complete with a wiring sheet.
-
- 1 N-type Semiconductor Substrate
- 1 a First Face
- 1 b Second Face
- 1 c Side Face
- 2 I-type Amorphous Semiconductor Film
- 3 P-type Amorphous Semiconductor Film
- 3 a Edge Portion
- 4 I-type Amorphous Semiconductor Film
- 4 a Edge Portion
- 5 N-type Amorphous Semiconductor Film
- 5 a Edge Portion
- 7 P-electrode
- 7 a End
- 7 b End
- 8 N-electrode
- 8 a End
- 10 Heterojunction Back-contact Cell
- 20 Wiring Sheet
- 21 Insulating Base Member
- 22 First Wire
- 23 Second Wire
- 24 Power Collection Wire
- 31 Etching Paste
- 32 Etching Mask
- 41 Conductive Layer
- 51 First Laminate
- 52 Second Laminate
- 61, 62 Laser Light
Claims (9)
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JP2016159105 | 2016-08-15 | ||
PCT/JP2017/029280 WO2018034266A1 (en) | 2016-08-15 | 2017-08-14 | Photoelectric conversion element and photoelectric conversion device |
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US17/668,058 Division US11515436B2 (en) | 2016-08-15 | 2022-02-09 | Photovoltaic device and photovoltaic unit |
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US20150357491A1 (en) * | 2013-03-28 | 2015-12-10 | Sharp Kabushiki Kaisha | Photoelectric conversion element |
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WO2013027591A1 (en) | 2011-08-25 | 2013-02-28 | 三洋電機株式会社 | Solar cell and solar cell module |
US20150214398A1 (en) | 2012-08-29 | 2015-07-30 | Mitsubishi Electric Corporation | Photovoltaic element and manufacturing method thereof |
CN102931269A (en) * | 2012-11-29 | 2013-02-13 | 山东力诺太阳能电力股份有限公司 | N-type silicon substrate based back contact type HIT (Heterojunction with Intrinsic Thin layer) solar cell structure and preparation method thereof |
JP6360471B2 (en) * | 2013-03-04 | 2018-07-18 | シャープ株式会社 | Photoelectric conversion element, photoelectric conversion module, and photovoltaic power generation system |
KR101627204B1 (en) * | 2013-11-28 | 2016-06-03 | 엘지전자 주식회사 | Solar cell and method for manufacturing the same |
JP2015162483A (en) * | 2014-02-26 | 2015-09-07 | シャープ株式会社 | Solar battery cell, solar battery sub cell and solar battery module |
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US11515436B2 (en) | 2022-11-29 |
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