JP5219977B2 - Solar cell element and solar cell module - Google Patents

Description

  The present invention relates to a solar cell element and a solar cell module.

  One type of solar cell element is a back contact type solar cell element (see, for example, Patent Document 1).

  A conventional back-contact solar cell element includes a semiconductor substrate having one conductivity type, a semiconductor layer having a conductivity type opposite to that of the semiconductor substrate, a first electrode, and a first electrode. And a second electrode having different polarities. The semiconductor substrate includes a plurality of through holes penetrating between the light receiving surface and the back surface. The reverse conductivity type semiconductor layer is provided on the light receiving surface of the semiconductor substrate, the second semiconductor layer provided on the surface of the through hole of the semiconductor substrate, and the back surface side of the semiconductor substrate. It consists of a third semiconductor layer. The first electrode is formed on the light-receiving surface electrode portion formed on the light-receiving surface side of the semiconductor substrate, the through-hole electrode portion formed in the through-hole, and the through-hole electrode portion on the back surface of the semiconductor substrate. It consists of a bus bar electrode part. The light-receiving surface electrode part, the through-hole electrode part, and the bus bar electrode part are electrically connected to each other. The second electrode is formed on a portion of the back surface of the semiconductor substrate where the third semiconductor layer is not formed.

International Publication No. 2008/078741

  However, while the above-described solar cell element and the solar cell module using the solar cell element are expected to further spread, it is important to improve the conversion efficiency of sunlight with a simple configuration. In order to improve the conversion efficiency, it is important to reduce the loss of photovoltaic power.

  This invention is made | formed based on the said problem, and it aims at providing a highly efficient solar cell element and solar cell module with a simple structure.

  The solar cell element of this invention is equipped with the semiconductor substrate which has the 1st surface which receives light, and the 2nd surface on the back side of this 1st surface which exhibits a 1 conductivity type. Further, the solar cell element of the present invention is derived from the first surface side to the second surface side and arranged in one direction, and an array of the plurality of first conduction portions. A plurality of second conductive parts provided on the second surface along the direction and connected to the first conductive parts so as to cover a part of the plurality of first conductive parts, and along the arrangement direction And a plurality of first output extraction parts connected to the second conduction part. In addition, the solar cell element of the present invention includes the one conductivity type, which includes a dopant having a concentration higher than that of the semiconductor substrate, and is provided in a non-formation region of the first electrode on the second surface side. A semiconductor layer is provided. Moreover, the solar cell element of this invention is equipped with the 2nd electrode which has a current collection part provided on the said semiconductor layer. In the solar cell element of the present invention, the length of the first output extraction portion in the arrangement direction is shorter than the length of the second conduction portion, and the semiconductor layers are adjacent to each other in the arrangement direction. It is provided between one output extraction part.

  Moreover, the solar cell module of the present invention includes a plurality of the above-described solar cell elements of the present invention arranged so as to be adjacent to each other, and the first of the solar cell elements between the adjacent solar cell elements. Wiring which connects an electrode and the second electrode of the other solar cell element.

  Since the solar cell element and the solar cell module of the present invention can increase the formation region of the semiconductor layer, the BSF effect is enhanced, and the output characteristics of the solar cell element and the solar cell module can be improved.

It is the top view seen from the 1st surface side which shows the structure of the solar cell element which concerns on embodiment of this invention. It is the top view seen from the 2nd surface side which shows the structure of the solar cell element which concerns on embodiment of this invention. (A) is the cross-sectional schematic diagram seen from the cross section AA of FIG. 1, (b) is the cross-sectional schematic diagram seen from the cross section BB of FIG. FIG. 3 is an enlarged plan view of a portion C in FIG. 2. It is a figure which shows typically the structure of the solar cell module which concerns on embodiment of this invention. It is a figure shown in detail about the mode of the connection by the wiring of solar cell elements in the solar cell module which concerns on embodiment of this invention. It is the enlarged plan view seen from the 2nd surface side which shows the modification of the solar cell module which concerns on embodiment of this invention. It is the enlarged plan view seen from the 2nd surface side which shows the modification of the solar cell element which concerns on embodiment of this invention.

  Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

≪Structure of solar cell element≫
A solar cell element 10 according to an embodiment of the present invention includes a semiconductor substrate 1 exhibiting one conductivity type, a reverse conductivity type layer 2 having a conductivity type different from that of the semiconductor substrate 1, a through hole 3, and a first electrode 4. And a second electrode 5.

  As shown in FIGS. 1 to 4, the solar cell element 10 includes a first surface 1F (upper surface side in FIG. 3) and a second surface 1S on the back side of the first surface 1F (lower surface side in FIG. 3). ) Including a semiconductor substrate 1. In the solar cell element 10, the first surface 1F serves as a light receiving surface (for convenience of explanation, the first surface 1F is referred to as the light receiving surface of the semiconductor substrate 1, the second surface 1S is referred to as the back surface of the semiconductor substrate 1, etc. There is also.)

  As the semiconductor substrate 1, a crystalline silicon substrate such as a single crystal silicon substrate or a polycrystalline silicon substrate having a predetermined dopant element (impurity for conductivity control) and exhibiting one conductivity type (for example, p-type) is used. . The thickness of the semiconductor substrate 1 is more preferably, for example, 250 μm or less, and further preferably 150 μm or less. Although the shape of the semiconductor substrate 1 is not particularly limited, a rectangular shape as in the present embodiment is suitable from the viewpoint of the manufacturing method.

  In this embodiment, an example in which a crystalline silicon substrate exhibiting p-type conductivity is used as the semiconductor substrate 1 will be described. When the semiconductor substrate 1 made of a crystalline silicon substrate is p-type, it is preferable to use, for example, boron or gallium as the dopant element.

  On the first surface 1F side of the semiconductor substrate 1, as shown in FIG. 3, a large number of solar beams are absorbed into the semiconductor substrate 1 by reducing the reflection of incident light on the first surface 1 F. A texture structure (concavo-convex structure) 1a composed of the fine protrusions 1b is formed. Note that the texture structure 1a is not an essential component in the present embodiment, and may be formed as necessary.

  In addition, as shown in FIG. 3, the semiconductor substrate 1 has a plurality of through holes 3 between the first surface 1F and the second surface 1S. As will be described later, the second reverse conductivity type layer 2b is formed on the surface of the through hole 3. In addition, a first conduction part 4 b of the first electrode 4 is formed inside the through hole 3. The through holes 3 are preferably formed at a constant pitch in the range of 50 μm to 300 μm in diameter. The through hole 3 may have different diameters that open to the first surface 1F and the second surface 1S. For example, as shown in FIG. 3, the second surface 1S is formed from the first surface 1F side. The shape may be such that the diameter decreases toward the side.

  The reverse conductivity type layer 2 is a layer having a conductivity type opposite to that of the semiconductor substrate 1. The reverse conductivity type layer 2 includes a first reverse conductivity type layer 2a formed on the first surface 1F side of the semiconductor substrate 1, a second reverse conductivity type layer 2b formed on the surface of the through hole 3, and a semiconductor substrate. And a third reverse conductivity type layer 2c formed on the first second surface 1S side. If a silicon substrate exhibiting a p-type conductivity is used as the semiconductor substrate 1, the reverse conductivity type layer 2 is formed to exhibit an n-type conductivity. On the other hand, when a silicon substrate having n-type conductivity is used as the semiconductor substrate 1, the reverse conductivity type layer 2 is formed to exhibit p-type conductivity.

The first reverse conductivity type layer 2a is preferably formed as an n ⁺ type having a sheet resistance of about 60 to 300Ω / □. By setting it as this range, increase in surface recombination and increase in surface resistance on the first surface 1F can be suppressed. The first reverse conductivity type layer 2a is preferably formed on the first surface 1F of the semiconductor substrate 1 to a depth of about 0.2 μm to 0.5 μm. The third opposite conductivity type layer 2c is formed in the second electrode 1S of the semiconductor substrate 1 in the formation region of the first electrode 4 and its peripheral part. By having the reverse conductivity type layer 2, in the solar cell element 10, a pn junction is formed between the reverse conductivity type layer 2 and the bulk region of the semiconductor substrate 1 (a region where the reverse conductivity type layer 2 is not formed). Is done.

  The solar cell element 10 has a semiconductor layer 6 on the second surface 1S of the semiconductor substrate 1. The semiconductor layer 6 is for the purpose of forming an internal electric field inside the solar cell element 10 in order to suppress a decrease in power generation efficiency due to the occurrence of carrier recombination in the vicinity of the second surface 1S of the semiconductor substrate 1. It is a layer provided (for the purpose of obtaining the so-called BSF effect). The semiconductor layer 6 is formed on substantially the entire surface of the semiconductor substrate 1 on the second surface 1S side where the third reverse conductivity type layer 2c and the first electrode 4 are not provided (non-formation region). More specifically, the semiconductor layer 6 is formed on the second surface 1S side so as not to contact the third reverse conductivity type layer 2c and the first electrode 4. Further, a pn isolation region is provided between the third reverse conductivity type layer 2c and the semiconductor layer 6 and at the peripheral portion of the second surface 1S of the semiconductor substrate 1, and the semiconductor substrate is provided in such a pn isolation region. There is one bulk region.

The semiconductor layer 6 has the same conductivity type as the semiconductor substrate 1, but has a concentration higher than the concentration of the dopant contained in the semiconductor substrate 1. Here, “high concentration” means that the dopant element is present at a concentration higher than the concentration of the dopant element doped to exhibit one conductivity type in the semiconductor substrate 1. If the semiconductor substrate 1 exhibits a p-type, the semiconductor layer 6 has a concentration of these dopant elements of 1 × 10 ^{18 to} 5, for example, by diffusing a dopant element such as boron or aluminum into the second surface 1S. It is preferably formed so as to be about × 10 ²¹ atoms / cm ³ . As a result, the semiconductor layer 6 exhibits a p ⁺ type conductivity type containing a dopant at a higher concentration than the p type conductivity type exhibited by the semiconductor substrate 1, and a first current collector described later Ohmic contact is realized between 5b.

  The semiconductor layer 6 is preferably formed in 70% or more of the entire region of the second surface 1S when the second surface 1S of the semiconductor substrate 1 is viewed in plan. When it is 70% or more, more BSF effects that improve the output characteristics of the solar cell element 10 can be obtained.

  The solar cell element 10 has an antireflection film 7 on the first surface 1F side of the semiconductor substrate 1. The antireflection film 7 has a role of reducing the reflection of incident light on the surface (first surface 1F) of the semiconductor substrate 1, and is formed on the first reverse conductivity type layer 2a. The antireflection film 7 is preferably formed of a silicon nitride film or an oxide material film. The thickness of the antireflection film 7 is set to a value that realizes a non-reflection condition for incident light, although a suitable value varies depending on the constituent material. For example, when a silicon substrate is used as the semiconductor substrate 1, the antireflection film 7 may be formed to a thickness of about 500 to 1200 mm with a material having a refractive index of about 1.8 to 2.3. The provision of the antireflection film 7 is not an essential component in the present embodiment, and may be formed as necessary.

  As shown in FIG. 3A, the first electrode 4 includes a main electrode portion 4a formed on the first surface 1F of the semiconductor substrate 1 and a through-hole electrically connected to the main electrode portion 4a. 3 is formed on the second surface 1S, and is electrically connected to the second conduction portion 4c and the second conduction portion 4c that are connected to the first conduction portion 4b. And a first output extraction portion 4d. The main electrode portion 4a has a function of collecting carriers generated on the first surface 1F side. The 1st conduction | electrical_connection part 4b and the 2nd conduction | electrical_connection part 4c have a function which guide | induces the carrier collected by the main electrode part 4a to the 1st output extraction part 4d provided in the 2nd surface 1S side. 4 d of 1st output extraction parts have a function as a wiring connection part connected with the wiring which electrically connects adjacent solar cell elements.

  On the other hand, the second electrode 5 has a polarity different from that of the first electrode 4 and is disposed so as to be insulated from the first electrode 4. As shown in FIGS. 2 and 4, such a second electrode 5 is formed on the second output extraction portion 5a, the first current collecting portion 5b, and the first current collecting portion 5b by, for example, a grid of thin lines. A second current collecting part 5c provided in a shape, and a connecting part 5d that electrically connects the second current collecting part 5c and the second output extraction part 5a located on both sides of the second conducting part 4d. Have. That is, in the present embodiment, the first current collector 5 b is provided on the semiconductor layer 2. The provision of the second current collector 5c is not an essential component in the present embodiment, and may be formed as necessary. Therefore, in the case where the second current collecting portion 5c is not formed, the connecting portion 5d has the first current collecting portions 5b positioned on both sides of the second conducting portion 4d or the first current collecting portion 5b and the second output extraction portion. Can be electrically connected to each other.

  The first current collector 5b is formed on the semiconductor layer 6 provided on the second surface 1S side of the semiconductor substrate 1, and collects the carriers generated on the second surface 1S side. The 2nd output extraction part 5a has a role as a wiring connection part connected with the wiring which electrically connects adjacent solar cell elements. Moreover, it is preferable that the 2nd output extraction part 5a is comprised so that at least one part may overlap with the 1st current collection part 5b. Moreover, in the solar cell element 10, by providing the connection part 5d, the 2nd electrode 5 (1st current collection part 5b, 1st) on the other side across the 2nd conduction | electrical_connection part 4c adjacent to the 2nd output extraction part 5a The carriers collected by the second current collector 5c) can be efficiently transmitted to the second output extraction unit 5a through the first current collector 5b and the second current collector 5c or directly.

  The first current collector 5b is made of, for example, aluminum, and the second output extraction part 5a, the second current collector 5c, and the connecting part 5d are made of, for example, silver. Note that the connecting portion 5d may be formed of aluminum, for example, or may be formed of silver on aluminum.

  By having the above-described configuration, the solar cell element 10 according to the present embodiment is realized.

  Next, the structure of the 1st and 2nd electrode of this Embodiment is explained in full detail.

  As shown in FIG. 1, the first electrode 4 has a plurality of first conductive portions 4 b corresponding to the plurality of through holes 3 formed in the semiconductor substrate 1. As shown in FIG. 3, the first conductive portion 4b is provided so as to be led out from the first surface 1F side of the semiconductor substrate 1 to the second surface 1S side. In FIG. 1, the formation position of the first conduction part 4 b illustrated in a black circle shape corresponds to the formation position of the through hole 3. In the present embodiment, the plurality of first conductive portions 4b are arranged in a predetermined direction. In this solar cell element 10, as shown in FIG. 1, a plurality of first conductive portions 4b are arranged in a plurality of rows (in FIG. 1, in a direction parallel to the reference side BS of the first surface 1F of the semiconductor substrate 1). 3 rows). The reference side BS is a side that is parallel to the arrangement direction when the solar cell module 20 is formed by arranging a plurality of solar cell elements 10. Hereinafter, a direction along the reference side BS (a direction parallel to the reference side BS) may be referred to as an arrangement direction. In the solar cell element 10, the 1st conduction | electrical_connection part 4b is provided in linear form along the said arrangement direction, and is provided in the substantially equal space | interval. In this specification, it is needless to say that “parallel” should not be strictly understood as in mathematical definition.

  The main electrode portion 4a of the first electrode 4 has a plurality of linear patterns (a plurality of line patterns) connecting the first conductive portions 4b belonging to different columns on the first surface 1F of the semiconductor substrate 1. A conductor). For example, in the solar cell element 10 shown in FIG. 1, the main electrode portion 4a has three first conducting portions positioned in a direction perpendicular to the arrangement direction of the first conducting portions 4b arranged in three rows. It has a linear conductor that connects 4b. That is, in the present embodiment, the number of linear conductors is the same as the number of first conductive parts 4b belonging to one column arranged in one direction. According to such a form, carriers collected by a smaller number of linear conductors can be guided to the first conductive portion 4b without being concentrated on one first conductive portion 4b, so that a light receiving area is secured. The increase in excessive resistance loss of the main electrode portion 4a can be reduced. Therefore, the output characteristics of the solar cell element are unlikely to deteriorate.

  The main electrode portion 4a is preferably formed to have a line width of about 50 to 100 μm. In addition, it is preferable from the viewpoint of improving the aesthetic appearance that the plurality of linear conductors as described above are formed so as to be substantially equidistant from each other. In addition, the space | interval of each linear conductor should just be about 1-3 mm, for example.

  Further, the main electrode portion 4 a may have a circular pattern that covers the through hole 3 and is larger than the diameter of the through hole 3. According to such a form, it becomes possible to connect with the 1st conduction | electrical_connection part 4b even if the formation position of the main electrode part 4a shifts | deviates a little. In addition, the pattern of the main electrode part 4a is not restricted to what was shown in FIG. 1, A various pattern can be formed.

  In the solar cell element 10 having the main electrode portion 4a as described above, the proportion of the main electrode portion 4a constituting the first electrode 4 is very large compared to the entire surface of the first surface 1F that is the light receiving surface. Since the main electrode portion 4a is uniformly formed, the carriers generated on the first surface 1F can be efficiently collected. .

  As shown in FIGS. 3B and 4, the first electrode 4 is located on the second surface 1 </ b> S of the semiconductor substrate 1 at a position directly below the plurality of first conductive portions 4 b (through holes 3). It has the 2nd conduction | electrical_connection part 4c. The second conducting portion 4c has a long shape having a longitudinal direction in the arrangement direction of the first conducting portions 4b (the direction along the reference side BS). That is, the 2nd conduction | electrical_connection part 4c is provided along the sequence direction of the 1st conduction | electrical_connection part 4b. In the present embodiment, a plurality of second conductive portions 4c configured to be connected to a plurality of first conductive portions 4b by one second conductive portion 4c are arranged. In addition, since the 2nd conduction | electrical_connection part 4c should just be electrically connected with the 1st conduction | electrical_connection part 4b, what is necessary is just to form it in contact so that a part of 1st conduction | electrical_connection part 4b may be covered.

  Furthermore, the first electrode 4 has a plurality of first output extraction portions 4d that are adjacent to each second conduction portion 4c and connected to each second conduction portion 4c on the second surface 1S. . The second conduction portion 4c and the first output extraction portion 4d are formed in a plurality of rows (three rows in FIG. 2) corresponding to the number of columns of the first conduction portions 4b arranged. The first output extraction portion 4d is arranged so as to be connected to the second conduction portion 4c along the arrangement direction of the first conduction portion 4b. The first output extraction portion 4d has a long shape having a longitudinal direction along the arrangement direction of the first conduction portions 4b.

  The first current collecting part 5b of the second electrode 5 is a peripheral part of the second conducting part 4c, the first output extracting part 4d, the second conducting part 4c, and the first output extracting part 4d on the second surface 1S. The second electrode 5 is provided on substantially the entire second surface 1S excluding a part of the second output extraction portion 5a. Here, “substantially the entire surface” means that the first current collector 5b is formed in 70% or more of the entire area of the second surface 1S when the second surface 1S of the semiconductor substrate 1 is viewed in plan. Say. Providing the first current collector 5b on substantially the entire surface other than the region where the first electrode 4 is formed can shorten the moving distance of the carriers collected by the first current collector 5b, and hence the second output. Since the amount of carriers taken out from the take-out part 5a is increased, it contributes to the improvement of the output characteristics of the solar cell element 10.

  The 2nd output extraction part 5a of a 2nd electrode has a role as a wiring connection part connected with the wiring which electrically connects adjacent solar cell elements. The second output extraction unit 5a may be configured so that at least a part of the second output extraction unit 5a overlaps the first current collection unit 5b. With such a configuration, the carrier collected by the first current collection unit 5b is used. Can be output externally. Therefore, as shown in FIG. 3A, the second output extraction portion 5a may be arranged in a region where the first current collector 5b is not formed. The plurality of second output extraction units 5a (in FIG. 2, corresponding to the first output extraction unit 4d in three rows) are arranged in parallel with each of the plurality of first output extraction units 4d. It has the same long shape as the portion 4d. In FIG. 2, a plurality of second output extraction portions 5a are formed in the direction along the reference side BS, but may be formed as a single strip.

  And in this Embodiment, as shown in FIG. 4, the length of the 1st output extraction part 4d is shorter than the length of the 2nd conduction | electrical_connection part 4c in the sequence direction of the 1st conduction | electrical_connection part 4b. Therefore, in the present embodiment, the semiconductor layer 6 can be provided up to the first output extraction portions 4d adjacent in the arrangement direction, and the formation region of the semiconductor layer 6 can be expanded. As a result, in the present embodiment, since the BSF effect generated at the interface between the semiconductor substrate 1 and the semiconductor layer 6 can be enhanced, the output characteristics of the solar cell element 10 can be improved. Furthermore, in the present embodiment, since the first current collector 5b can be formed on the semiconductor layer 6 between the first output extraction parts 4d in the arrangement direction, only the connection part 5d having a narrow line width exists. Therefore, the resistance loss of the second electrode 5 is reduced, which can contribute to the improvement of the output characteristics of the solar cell element 10. Note that the length of the second conductive portion 4c in the longitudinal direction only needs to be able to cover the plurality of first conductive portions 4b (in FIG. 4, one second conductive portion 4c includes six first conductive portions. 4b), which is not particularly limited, but is set to 8 to 15 mm, for example. Moreover, the width | variety of the 2nd conduction | electrical_connection part 4c should just have the length which can cover the 1st conduction | electrical_connection part 4b, for example, is set by 0.1-1 mm. The length of the first output extraction portion 4d in the longitudinal direction is such that the wiring connecting adjacent solar cell elements can be connected and shorter than the first conduction portion 4b, for example, 4 to 10 mm. Is set. Moreover, the width | variety of 4 d of 1st output extraction parts should just be the same as that of the width | variety of the wiring mentioned later, or larger than it, for example, is set to 1.5-4 mm.

≪Solar cell module≫
Solar cell element 10 according to the present embodiment can be used alone, but is arranged such that a plurality of solar cell elements 10 having the same structure are adjacent to each other, and further connected in series. When configuring a module, it has a suitable structure. Then, the solar cell module formed using the several solar cell element 10 is demonstrated below.

  As shown in FIG. 5A, the solar cell module 20 includes a translucent member 11 made of glass or the like, a front side filler 12 made of a transparent ethylene vinyl acetate copolymer (EVA) or the like, and a plurality of solar cells. It mainly includes a battery element 10, a back side filler 13 made of EVA or the like, and a back surface protective material 14 in which polyethylene terephthalate (PET) or metal foil is sandwiched between polyvinyl fluoride resin (PVF) or the like. As shown in FIG. 5B, the plurality of solar cell elements 10 are formed by connecting the adjacent solar cell elements 10 to each other in series by a wiring 15 having a function as a connecting member.

  As shown in FIG. 6, the solar cell module 20 has one first output extraction portion 4 d of adjacent solar cell elements 10 and a second output extraction portion 5 a of the other solar cell element 10, one long. Connected by a straight (linear) wiring 15. In the form shown in FIG. 6, the connection is made at three places. For convenience, in the following, in FIG. 6, of the two solar cell elements 10 connected by the wiring 15, the solar cell element 10 in which the wiring 15 is connected to the first output extraction portion 4 d is referred to as a first solar cell. The solar cell element 10 will be referred to as a battery element 10α, and the solar cell element 10 whose wiring is connected to the second output extraction portion 5a will be referred to as a second solar cell element 10β.

  More specifically, in the solar cell module 20, the first solar cell element 10α and the second solar cell element 10β are positioned so that the respective reference sides BS are parallel and not on the same straight line, and Are arranged so as to have a rotationally symmetric relationship (more specifically, point symmetry). By doing in this way, all the 1st output extraction parts 4d and all the 2nd output extraction parts 5a which are located on the same straight line are connected by the one wiring 15. FIG. In this case, the relative arrangement relationship between the plurality of first output extraction units 4d and the plurality of second output extraction units 5a connected by the single wiring 15 is equivalent (the plurality of first output extraction units 5a). 4d and the plurality of second output extraction portions 5a are all in translational symmetry), so that the same wiring 15 is used for connecting each of the first output extraction portion 4d and the second output extraction portion 5a. Shaped ones can be used.

  As the wiring 15, for example, a strip-shaped copper foil having a thickness of about 0.1 to 0.4 mm and a width of about 2 mm and whose entire surface is coated with a solder material is cut into a predetermined length in the longitudinal direction. Can be used. In the case of the wiring 15 covered with the solder material, soldering is performed on the first output extraction portion 4d and the second output extraction portion 5a of the solar cell element 10 using hot air, a soldering iron, or the like, or using a reflow furnace or the like. Attached.

  In addition, as shown in FIG. 7, it is preferable to provide an insulating layer 8 such as an oxide film, resin, insulating tape or the like in a region other than the first output extraction portion 4d on the arrangement of the first output extraction portions 4d. It is possible to prevent 15 from coming into contact with the second electrode 5 or the like and short-circuiting. At this time, the pn isolation region is also preferably covered with an insulating layer. Note that the insulating layer may be provided on the wiring 15.

  Further, the wiring 15 may have a concavo-convex shape so as to be separated from the semiconductor substrate 1 in a non-connection region other than a connection region between the plurality of first output extraction portions 4d and the plurality of second output extraction portions 5a. Since the second electrode 5 and the wiring 15 existing between the first output extraction parts 4d do not contact each other, a short circuit can be suppressed.

  If a material having a high reflectance such as white is used as the back surface protection material 14, the light irradiated between the solar cell elements 10 is diffusely reflected by the back surface protection material 14 and irradiated to the solar cell elements 10. Therefore, the amount of received light in the solar cell element 10 is further increased.

≪Method for manufacturing solar cell element≫
Next, the manufacturing method of a solar cell element is demonstrated.

<Preparation process of semiconductor substrate>
First, a semiconductor substrate 1 exhibiting a p-type conductivity is prepared.

  In the case of using a single crystal silicon substrate as the semiconductor substrate 1, the semiconductor substrate 1 can be obtained by cutting a single crystal silicon ingot produced by a known manufacturing method such as FZ or CZ method into a predetermined thickness. If a polycrystalline silicon substrate is used as the semiconductor substrate 1, the semiconductor substrate 1 is obtained by cutting a polycrystalline silicon ingot produced by a known manufacturing method such as a casting method or a solidification method in a mold into a predetermined thickness. be able to.

In the following, a crystalline silicon substrate that exhibits p-type conductivity by doping B (boron) or Ga (gallium) as a dopant element to about 1 × 10 ¹⁵ to 1 × 10 ¹⁷ atoms / cm ³ is used as a semiconductor substrate. The case of using as 1 will be described as an example.

  In addition, in order to remove the mechanical damage layer and the contamination layer of the surface layer portion of the semiconductor substrate 1 due to the cutting (slicing), the surface layer portions on the front surface side and the back surface side of the cut semiconductor substrate 1 are NaOH, KOH, or hydrofluoric acid Etching is about 10 to 20 μm each with a mixed solution of nitric acid and nitric acid, and then washed with pure water to remove organic components and metal components.

<Through-hole formation process>
Next, the through hole 3 is formed between the first surface 1F and the second surface 1S of the semiconductor substrate 1.

  The through hole 3 is formed using a mechanical drill, a water jet, a laser processing apparatus, or the like. The through-hole 3 is formed so as to process from the second surface 1S side of the semiconductor substrate 1 toward the first surface 1F side in order to avoid damage to the first surface 1F serving as the light receiving surface. To. However, if there is little damage to the semiconductor substrate 1 due to the processing, the processing may be performed from the first surface 1F side to the second surface 1S side.

<Texture structure forming process>
Next, a texture structure 1 a having fine protrusions (convex portions) 1 b for effectively reducing the light reflectance is formed on the light receiving surface side of the semiconductor substrate 1 in which the through holes 3 are formed.

  As a method for forming the texture structure 1a, a wet etching method using an alkaline aqueous solution such as NaOH or KOH, or a dry etching method using an etching gas having a property of etching silicon which is a material of the semiconductor substrate 1 can be used.

<Reverse conductivity type layer formation process>
Next, the reverse conductivity type layer 2 is formed. That is, the first reverse conductivity type layer 2a is formed on the first surface 1F of the semiconductor substrate 1, the second reverse conductivity type layer 2b is formed on the surface of the through hole 3, and the third reverse conductivity is formed on the second surface 1S. A mold layer 2c is formed.

  When a crystalline silicon substrate exhibiting p-type conductivity is used as the semiconductor substrate 1, it is preferable to use P (phosphorus) as an n-type doping element for forming the reverse conductivity type layer 2.

The reverse conductivity type layer 2 is a coating thermal diffusion method in which P ₂ O ₅ in a paste state is applied to the formation target portion of the semiconductor substrate 1 for thermal diffusion, and POCl ₃ (phosphorus oxychloride) in a gas state is a diffusion source. As described above, it is formed by a gas phase thermal diffusion method for diffusing to a formation target location, an ion implantation method for diffusing directly to a formation planned location, or the like. It is preferable to use the vapor phase diffusion method because the opposite conductivity type layer 2 can be formed at the same time on both main surfaces of the semiconductor substrate 1 and the surface of the through hole 3.

  Note that, under conditions where a diffusion region is formed in addition to the formation target portion, a diffusion prevention layer is formed in advance on the portion, and then the reverse conductivity type layer 2 is formed, thereby partially diffusing. Can be prevented. Further, without forming the diffusion preventing layer, the diffusion region formed at a portion other than the formation target portion may be etched and removed later. In addition, after forming the reverse conductivity type layer 2, when the semiconductor layer 6 is formed with an aluminum paste as will be described later, aluminum as a p-type dopant element can be diffused to a sufficient depth at a sufficient concentration. The existence of shallow diffusion regions that have already been formed can be ignored. That is, it is not necessary to remove the reverse conductivity type layer 2 present at the planned formation location of the semiconductor layer 6. Further, pn separation may be performed by a known method such as laser irradiation around the region where the first electrode 4 is formed or the peripheral portion of the second surface 1S of the semiconductor substrate 1.

<Antireflection film formation process>
Next, the antireflection film 7 is formed on the first reverse conductivity type layer 2a.

As a method for forming the antireflection film 7, a PECVD method, a vapor deposition method, a sputtering method, or the like can be used. For example, when the antireflection film 7 made of a SiNx film is formed by PECVD, the reaction chamber is set to about 500 ° C. and a mixed gas of silane (Si ₃ H ₄ ) and ammonia (NH ₃ ) is nitrogen (N ₂ The anti-reflective film 7 is formed by diluting with (), and plasma-depositing by glow discharge decomposition. The antireflection film 7 may also be formed on the second reverse conductivity type layer 2b.

<Semiconductor layer formation process>
Next, the semiconductor layer 6 is formed on the second surface 1S of the semiconductor substrate 1.

When boron is used as a dopant element, it can be formed at a temperature of about 800 to 1100 ° C. by a thermal diffusion method using BBr ₃ (boron tribromide) as a diffusion source. In this case, prior to the formation of the semiconductor layer 6, a diffusion prevention layer made of an oxide film or the like, for example, on a region other than the portion where the semiconductor layer 6 is to be formed, for example, on the reverse conductivity type layer 2 or the like already formed. It is desirable to remove the semiconductor layer 6 after the semiconductor layer 6 is formed.

  When aluminum is used as the dopant element, an aluminum paste made of aluminum powder and an organic vehicle or the like is applied to the second surface 1S of the semiconductor substrate 1 by a printing method, followed by heat treatment (baking at a temperature of about 700 to 850 ° C. The semiconductor layer 6 can be formed by diffusing aluminum toward the semiconductor substrate 1. In this case, the semiconductor layer 6 that is a desired diffusion region can be formed only on the second surface 1S that is the printing surface of the aluminum paste. In addition, the layer made of aluminum formed on the second surface 1S after firing can be used as it is as the first current collector 5b without being removed.

<Method for forming electrode>
Next, the main electrode portion 4a and the first conduction portion 4b constituting the first electrode 4 are formed.

  The main electrode portion 4a and the first conductive portion 4b are formed using, for example, a coating method. Specifically, 10 to 30 parts by weight of an organic vehicle and 0.1 to 10 parts by weight of glass frit are added to the first surface 1F of the semiconductor substrate 1 with respect to 100 parts by weight of metal powder made of, for example, silver. After forming a coating film by applying the conductive paste formed in the formation pattern of the main electrode portion 4a shown in FIG. 1, the coating film is tens of seconds to several tens of minutes at a maximum temperature of 500 to 850 ° C. The main electrode part 4a and the 1st conduction | electrical_connection part 4b can be formed by baking to some extent. In this case, when the conductive paste is applied, the first conductive portion 4b can also be formed by filling the through hole 3 with the conductive paste. However, also when forming the 2nd conduction | electrical_connection part 4c so that it may mention later, after the conductive paste is apply | coated from the 2nd surface 1S side and the conductive paste is again filled with the conductive paste in that case at that time Since the baking is performed, the through-hole 3 may not be sufficiently filled with the conductive paste when the conductive paste is applied to the first surface 1F.

  In addition, after apply | coating an electrically conductive paste, it is preferable to evaporate the solvent in a coating film at predetermined temperature and to dry this coating film before baking. In addition, the conductive paste is filled and dried only in the through holes 3 in advance, and then the conductive paste is applied in the pattern of the main electrode portion 4a shown in FIG. The electrode portion 4a and the first conductive portion 4b may be formed by separately applying and firing.

  As described above, when the antireflection film 7 is formed prior to the formation of the main electrode portion 4a, the main electrode portion 4a is formed in the patterned region, or the main electrode portion is formed by a fire-through method. 4a will be formed. On the other hand, the antireflection film 7 may be formed after the main electrode portion 4a is formed. In this case, it is not necessary to pattern the antireflection film 7, and it is not necessary to use the fire-through method, so that the conditions for forming the main electrode portion 4a are moderate. If it is such a process, the main electrode part 4a can be formed, without baking at the high temperature of about 800 degreeC, for example.

  Subsequently, the first current collector 5 b is formed on the second surface 1 </ b> S of the semiconductor substrate 1.

  The first current collector 5b can also be formed using a coating method. Specifically, 10 to 30 parts by weight of an organic vehicle and 0.1 to 5 parts by weight of a glass frit are formed on the second surface 1S of the semiconductor substrate 1 with respect to 100 parts by weight of metal powder made of, for example, aluminum or silver. 2 is applied in the formation pattern of the current collecting portion 5b shown in FIG. 2, and then the coating film is formed at a maximum temperature of 500 to 850 ° C. for several tens of seconds to several By baking to a sufficient extent, the first current collector 5b can be formed. As described above, when the aluminum paste is used, the semiconductor layer 6 and the first current collector 5b can be formed simultaneously.

  Further, the second conduction portion 4c, the first output extraction portion 4d, the second output extraction portion 5a, the second current collection portion 5c, and the connection portion 5d are formed on the second surface 1S of the semiconductor substrate 1.

  The 2nd conduction | electrical_connection part 4c, the 1st output extraction part 4d, the 2nd output extraction part 5a, the 2nd current collection part 5c, and the connection part 5d can be formed simultaneously using the apply | coating method, for example. Specifically, 10 to 30 parts by weight of organic vehicle and 0.1 to 10 parts by weight of glass frit are added to the second surface 1S of the semiconductor substrate 1 with respect to 100 parts by weight of metal powder made of, for example, silver. After forming the coating film by applying the conductive paste with the electrode pattern as shown in FIGS. 2 and 4, the coating film is tens of seconds to several tens of minutes at the maximum temperature of 500 to 850 ° C. It can be formed by baking to a certain extent. In addition, you may form each structure part separately, or you may form using the electrically conductive paste of a different composition. Further, when the semiconductor layer 6 and the first current collector 5b are simultaneously formed using aluminum paste, the second output extraction portion 5a is formed on the third reverse conductivity type layer 2c, but there is no particular problem.

  The solar cell element 10 according to the present embodiment can be manufactured by the procedure as described above.

  If necessary, a solder region (not shown) may be formed on the first output extraction portion 4d and the second output extraction portion 5a by a solder dipping process.

  The insulating layer 8 may be formed by using a thin film forming technique such as CVD, for example, or may be formed by applying and baking an insulating paste made of a resin paste or the like. Alternatively, it may be formed by attaching a commercially available insulating tape. Note that when the insulating paste is fired, it may be fired at the same time as the electrodes are formed.

≪Solar cell module manufacturing method≫
Next, a method for manufacturing the solar cell module 20 using the solar cell element 10 formed as described above will be described.

  First, a wiring 15 is produced by cutting a copper foil having a thickness of about 0.1 to 0.4 mm and a width of about 2 mm covered with a solder material into a predetermined length in the longitudinal direction. deep.

  Then, as shown in FIG. 6, the plurality of solar cell elements 10 are placed with the second surface 1S facing upward and spaced apart by a predetermined distance, and the first output extraction portion of the first solar cell element 10α is placed. The wiring 15 is brought into contact between 4d and the second output extraction portion 5a of the second solar cell element 10β from above. In this state, the wiring 15 and the first output extraction section 4d and the second output extraction section 5a are connected by melting the solder on the surface of the wiring 15 using hot air, soldering iron, or a reflow furnace. Connect. According to this method, the solar cell elements 10 can be connected with high productivity.

  Then, on the translucent member 11, by laminating | stacking sequentially the front side filler 12, the several solar cell element 10 mutually connected by the wiring 15, the back side filler 14, and the back surface protective material 15. The obtained module base is integrated by degassing, heating and pressing in a laminator, whereby the solar cell module 20 is obtained.

  And as shown in FIG.5 (b), the frames 16, such as aluminum, are inserted in the outer periphery of the solar cell module 20 mentioned above as needed. Moreover, as shown to Fig.5 (a), the terminal which is an output extraction part is connected to the end of the electrode of the 1st solar cell element 10 and the last solar cell element 10 among several solar cell elements 10 connected in series. It is connected to the box 17 by an output extraction wiring 18.

  The solar cell module 20 according to the present embodiment can be obtained by the procedure described above.

<Modification>
As shown in FIG. 1, when n rows (n is an integer of 2 or more) of arrays of through holes 3 (first conductive portions 4 b) are provided in parallel to the reference side BS of the first surface 1 F of the semiconductor substrate 1. The through holes 3 (first conductive portions 4b) are formed at odd positions among (2n-1) dividing lines DS that equally divide one side of the semiconductor substrate 1 perpendicular to the reference side BS into 2n pieces. By providing the row, the resistance loss of the main electrode portion 4a can be more efficiently reduced and the aesthetics can be improved. By providing the second conductive portion 4c, it is possible to connect the wiring 15 by arranging adjacent solar cell elements so as to have a rotationally symmetric relationship with each other even in the above shape. In addition, if the arrangement | sequence 3 of the through-hole 3 is less than 2 mm from a dividing line, it may be considered to be located on a dividing line.

  Further, as shown in FIG. 4, the second output extraction portion 5 a located at the peripheral portion of the semiconductor substrate 1 is connected to the semiconductor substrate 1 without being connected to the first current collecting portion 5 b on the peripheral portion side of the semiconductor substrate 1. It is preferable to reduce the possibility that the second output extraction portion 5a is peeled off due to the expansion and contraction of the wiring 15 due to the daily temperature cycle when the solar cell module is installed outdoors.

  Also, as shown in FIG. 4, the alignment mark 9a for alignment is provided on the second surface 1S of the semiconductor substrate 1, and the alignment mark 9b for direction identification having a different shape of the alignment mark 9a for alignment is provided in another part. Is preferred. The direction identification alignment mark 9b makes it easy to determine the orientation of the solar cell element 10, and the alignment alignment mark 9a not only facilitates alignment when the wiring 15 is connected, but also includes the alignment alignment mark 9a. By providing the direction identification alignment mark 9b in the vicinity and providing the identification device on the alignment camera, the solar cell elements 10 to which the wiring 15 is connected are securely arranged or confirmed so as to have a rotationally symmetric relationship. Therefore, productivity can be improved. In addition, the alignment mark 9a for alignment may also serve as the alignment mark 9 for direction identification, and the alignment marks 9 provided at both ends may have different shapes. The alignment mark 9 is preferably formed simultaneously with the formation of the electrode on the second surface 1S of the semiconductor substrate 1.

  Further, the lengths of the first output extraction portion 4d and the second output extraction portion 5a in the direction along the reference side BS may be different or the same.

  Further, in the embodiment of the present invention, as shown in FIG. 8, the connection portion 5d may be directly connected to the second output extraction portion 5a. Further, in the embodiment of the present invention, as shown in FIG. 8, the first current collector 5b between the first output extraction parts 4d in the arrangement direction of the first conduction parts 4b (direction along the reference side BS). A second current collector 5c may be formed on the top. With such a configuration, it is possible to efficiently collect carriers.

  In the solar cell element 10, the first output extraction portion 4 d and the second output extraction portion 5 a are different from those described above as long as the arrangement state described above is satisfied and the connection mode by the wiring 15 can be realized. It may be formed in a shape (for example, a trapezoidal shape, a circular shape, an elliptical shape, a semicircular shape, a fan shape, or a composite shape thereof).

1: Semiconductor substrate 2: Reverse conductivity type layer 2a: 1st reverse conductivity type layer 2b: 2nd reverse conductivity type layer 2c: 3rd reverse conductivity type layer 3: Through-hole 4: 1st electrode 4a: Main electrode part 4b : 1st conduction | electrical_connection part 4c: 2nd conduction | electrical_connection part 4d: 1st output extraction part 5: 2nd electrode 5a: 2nd output extraction part 5b: 1st current collection part 5c: 2nd current collection part 5d: Connection part 6 : Semiconductor layer 10: Solar cell element 11: Translucent substrate 12: Front side filler 13: Back side filler 14: Back side protective material 15: Wiring 16: Frame 17: Terminal box 18: Output extraction wiring 20: Solar cell module

Claims (7)

A semiconductor substrate of one conductivity type, having a first surface for receiving light and a second surface on the back side of the first surface;
A plurality of first conductive portions led out from the first surface side to the second surface side and arranged in one direction; and on the second surface along an arrangement direction of the plurality of first conductive portions A plurality of second conduction parts connected to the first conduction part so as to cover a part of the plurality of first conduction parts, and connected to the second conduction part along the arrangement direction. A first electrode having a plurality of first output extraction parts;
A semiconductor layer exhibiting the one conductivity type, comprising a dopant having a higher concentration than the semiconductor substrate, and provided in a non-formation region of the first electrode on the second surface side;
A second electrode having a current collector provided on the semiconductor layer,
The length in the arrangement direction of the first output extraction portion is shorter than the length of the second conduction portion,
The solar cell element, wherein the semiconductor layer is provided between the first output extraction portions adjacent to each other in the arrangement direction.   2. The solar cell element according to claim 1, wherein the current collector is provided on the semiconductor layer located between the adjacent first output extraction portions in the arrangement direction.   A plurality of the second electrodes are provided so that the second surface is seen in plan view so that the current collectors sandwich the second conductive part, and the adjacent current collectors are electrically connected to each other. The solar cell element according to claim 2, further comprising a connecting portion. The first electrode includes a plurality of linear conductors provided on the first surface at substantially equal intervals,
4. The solar cell element according to claim 1, wherein the number of the linear conductors is the same as the number of the first conductive portions arranged in the one direction. 5.   The solar cell element according to claim 1, further comprising a plurality of alignment marks having different shapes from each other on the second surface.   The first conductive portions are provided in n rows (n is an integer of 2 or more), and the dividing lines (2n−1) that equally divide one side of the semiconductor substrate perpendicular to the arrangement direction into 2n pieces. The solar cell element according to any one of claims 1 to 5, wherein a row of the first conduction parts is provided at odd positions. A plurality of solar cell elements according to any one of claims 1 to 6 arranged so as to be adjacent to each other,
A solar cell module comprising: a wiring for connecting the first electrode of one solar cell element and the second electrode of the other solar cell element between adjacent solar cell elements.

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