US20180337274A1 - Device and fabrication of mos device with island region - Google Patents
Device and fabrication of mos device with island region Download PDFInfo
- Publication number
- US20180337274A1 US20180337274A1 US16/051,016 US201816051016A US2018337274A1 US 20180337274 A1 US20180337274 A1 US 20180337274A1 US 201816051016 A US201816051016 A US 201816051016A US 2018337274 A1 US2018337274 A1 US 2018337274A1
- Authority
- US
- United States
- Prior art keywords
- gate
- trench
- active region
- contact trench
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000000463 material Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 239000007943 implant Substances 0.000 claims description 43
- 238000000034 method Methods 0.000 claims description 35
- 230000004888 barrier function Effects 0.000 claims description 27
- 239000002019 doping agent Substances 0.000 claims description 16
- 238000005468 ion implantation Methods 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 27
- 230000008569 process Effects 0.000 description 26
- 210000000746 body region Anatomy 0.000 description 20
- 229910052681 coesite Inorganic materials 0.000 description 13
- 229910052906 cristobalite Inorganic materials 0.000 description 13
- 239000000377 silicon dioxide Substances 0.000 description 13
- 229910052682 stishovite Inorganic materials 0.000 description 13
- 229910052905 tridymite Inorganic materials 0.000 description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 238000005530 etching Methods 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 229910052796 boron Inorganic materials 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 7
- 230000004048 modification Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- 230000002265 prevention Effects 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- -1 Boron ions Chemical class 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 230000001965 increasing effect Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000004557 technical material Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
Definitions
- Power MOS devices are commonly used in electronic circuits. Depending on the application, different device characteristics may be desirable.
- a DC-DC converter which includes a power MOS device as a synchronous rectifier (also referred to as the low side FET) and another power MOS device as a control switch (also referred to as the high side FET).
- the low side FET typically requires a small on-resistance to achieve good power switch efficiency.
- the high side FET typically requires a small gate capacitance for fast switching and good performance.
- R dson The value of a transistor's on-resistance (R dson ) is typically proportional to the channel length (L) and inversely proportional to the number of active cells per unit area (W).
- R dson the channel length
- W the number of active cells per unit area
- the channel length L is typically limited because of the punch-through phenomenon.
- the number of cells per unit area is limited by manufacturing technology and by the need to make a good contact to both the source and body regions of the cell.
- gate capacitance As the channel length and the cell density increase, gate capacitance also increases. Lower device capacitance is preferred for reduced switching losses. In some applications such as synchronous rectification, the stored charge and forward drop of the body diode also result in efficiency loss. These factors together tend to limit the performance of DMOS power devices.
- FIGS. 1A-1F illustrate several double-diffused metal oxide semiconductor (DMOS) device embodiments.
- DMOS metal oxide semiconductor
- FIG. 2 is a diagram illustrating a buck converter circuit example.
- FIG. 3 is a flowchart illustrating an embodiment of a fabrication process for constructing a DMOS device.
- FIGS. 4A-4U are device cross-sectional views illustrating in detail an example fabrication process used for fabricating an MOS device.
- FIGS. 5A-6B illustrates additional alternative embodiments of fabrication steps.
- FIGS. 7-10 illustrate optional modifications to the fabrication process that are used in some embodiments to further enhance device performance.
- the invention can be implemented in numerous ways, including as a process, an apparatus, a system, a composition of matter, a computer readable medium such as a computer readable storage medium or a computer network wherein program instructions are sent over optical or communication links.
- these implementations, or any other form that the invention may take, may be referred to as techniques.
- a component such as a processor or a memory described as being configured to perform a task includes both a general component that is temporarily configured to perform the task at a given time or a specific component that is manufactured to perform the task.
- the order of the steps of disclosed processes may be altered within the scope of the invention.
- MOS metal oxide semiconductor
- FIGS. 1A-1F illustrate several double-diffused metal oxide semiconductor (DMOS) device embodiments.
- FIG. 1A is a cross sectional view of an embodiment of a DMOS device.
- device 100 includes a drain that is formed on the back of an N + -type semiconductor substrate 103 .
- the drain region extends into an epitaxial (epi) layer 104 of N ⁇ -type semiconductor that overlays substrate 103 .
- Gate trenches such as 111 , 113 , and 115 are etched in epi layer 104 .
- a gate oxide layer 121 is formed inside the gate trenches.
- Gates 131 , 133 and 135 are disposed inside gate trenches 111 , 113 and 115 , respectively, and are insulated from the epi layer by the oxide layer.
- the gates are made of a conductive material such as polycrystalline silicon (poly) and the oxide layer is made of an insulating material such as thermal oxide.
- gate trench 111 is located in a termination region disposed with a gate runner 131 for connection to gate contact metal.
- gate runner trench 111 may be wider and deeper compared to active gate trenches 113 and 115 . Further the spacing between the gate runner trench 111 from the active trench next to it, in this case trench 113 , may be larger than the spacing between the active gate trenches 113 and 115 .
- Source regions 150 a - d are embedded in body regions 140 a - d , respectively.
- the source regions extend downward from the top surface of the body into the body itself. While body regions are implanted along side of all gate trenches, source regions are only implanted next to active gate trenches and not gate runner trenches.
- gates such as 133 have a gate top surface that extends substantially above the top surface of the body where the source is embedded. Such a configuration guarantees the overlap of the gate and the source, allowing the source region to be shallower than the source region of a device with a recessed gate, and increases device efficiency and performance.
- the amount by which the gate poly top surface extends above the source-body junction may vary for different embodiments. In some embodiments, the gates of the device do not extend above the top surface of the source/body region, rather recess from the top surface of the source/body region.
- a dielectric material layer 160 is disposed over the gate to insulate the gate from source-body contact.
- the dielectric material forms insulating regions such as 160 a - c on top of the gates as well as on top of the body and source regions.
- Appropriate dielectric materials include thermal oxide, low temperature oxide (LTO), boro-phospho-silicate glass (BPSG), etc.
- a number of contact trenches 112 a - b are formed between the active gate trenches near the source and body regions. These trenches are referred to as active region contact trenches since the trenches are adjacent to the device's active region that is formed by the source and body regions. For example, contact trench 112 a extends through the source and the body, forming source regions 150 a - b and body regions 140 a - b adjacent to the trench. In contrast, trench 117 , which is formed on top of gate runner 131 , is not located next to an active region, and therefore is not an active region contact trench.
- Trench 117 is referred to as a gate contact trench or gate runner trench since a metal layer 172 a connected to the gate signal is deposited within the trench.
- Gate signal is fed to active gates 133 and 135 through interconnections between trenches 111 , 113 and 115 in the third dimension (not shown).
- Metal layer 172 a is separated from metal layer 172 b , which connects to source and body regions through contact trenches 112 a - b to supply a power source.
- the active region contact trenches and gate contact trench have approximately the same depth.
- Device 100 has active region contact trenches 112 a - b that are shallower than the body. This configuration provides good breakdown characteristics as well as lower resistance and leakage current. Additionally, since the active contact trenches and gate contact trench are formed using a one step process therefore have the same depth, having active contact trenches that are shallower than the body prevents the gate runner such as 131 from being penetrated by the gate contact trench.
- the FET channel is formed along the active region gate trench sidewall between the source/body and body/drain junctions.
- the depletion region expands and may eventually reach the source junction. This phenomenon, referred to as punch through, limits the extent to which the channel may be shortened.
- regions such as 170 a - d along the walls of the active region contact trench are heavily doped with P type material to form P + -type regions.
- the P + -type regions prevent the depletion region from encroaching upon the source region.
- these implants are sometimes referred to as anti-punch through implants or punch through prevention implants.
- the P + regions are disposed as close as possible to the channel region and/or as close as it is allowed by manufacturing alignment capability and P + sidewall dopant penetration control.
- the misalignment between the trench contact and the trench is minimized by self-aligning the contact, and the trench contact is placed as closely centered between the trenches as possible.
- contact trenches 112 a - b are shallower than body regions 140 a - d and do not extend all the way through the body regions.
- the device's on-resistance R dson as well as the gate capacitance are reduced.
- a conductive material is disposed in contact trenches 112 a - b as well as gate trench 117 to form contact electrodes.
- the contact electrodes are in contact with N drain region 104 .
- the contact electrodes and the drain region form Schottky diodes that are in parallel with the body diode. The Schottky diodes reduce the body diode forward drop and minimize the stored charge, making the MOSFET more efficient.
- a single metal that is capable of simultaneously forming a Schottky contact to the N ⁇ drain and forming good Ohmic contact to the P + body and N + source is used to form electrodes 180 a - b .
- Metals such as titanium (Ti), platinum (Pt), palladium (Pd), tungsten (W) or any other appropriate material may be used.
- metal layer 172 is made of aluminum (Al) or made of a Ti/TiN/A 1 stack.
- the leakage current of the Schottky diode is related to the Schottky barrier height. As the barrier height increases, the leakage current decreases, and the forward drop voltage also increases.
- optional Schottky barrier controlling layers 190 a - b also known as Shannon layers
- the dopants have opposite polarity as the epi layer and are of P type in this example.
- the Shannon implant is shallow and low dosage; therefore, it is completely depleted regardless of bias.
- the Schottky barrier controlling layer is used to control the Schottky barrier height, thus allowing for better control over the leakage current and improving the reverse recovery characteristics of the Schottky diode. Details of the formation of the Schottky barrier controlling layer are described below.
- FIG. 1B is a cross sectional view of another embodiment of a DMOS device.
- Device 102 also includes Schottky barrier controlling layers 190 a - b around the bottoms of the active region contact trenches.
- the depth of gate contact trench 117 is different from that of active region contact trenches 112 - b .
- the active region contact trenches are deeper than body regions 140 a - d and extend beyond the body regions. Since the active contact trench is deeper, it provides more area for making Ohmic contact along the sidewalls and results in better unclamped inductive switching (UIS) capability.
- UAS unclamped inductive switching
- the gate contact trench shallower than the active contact trenches, it is unlikely that the gate contact trench would penetrate the gate runner poly during the etching process, which is useful for devices with relatively shallow gate polys (such as devices fabricated using processes that result in gate polys that do not extend above the body top surface).
- FIG. 1C is another embodiment of a DMOS device.
- gate contact trench 117 and active region contact trenches 112 a - b have different depths. Further, the depth of each of the active region contact trenches is non-uniform since the trench depth varies in the direction parallel to the substrate surface.
- the active region contact trenches are formed using a 2-step process, resulting in a first contact opening (e.g. 112 a - b ) that is wider than a second contact opening (e.g. 119 a - b ).
- the shape of the profile of the active region contact trench allows for greater Ohmic contact area and better punch-through prevention by anti-punch through implants 170 a - d , and improves the device's UIS capability. Shannon implants distribute around the sidewall and bottom of the second contact opening, forming a Schottky barrier controlling layer 190 a - b.
- FIGS. 1D-1F illustrate embodiments of DMOS devices with integrated low injection body diode.
- Devices 106 , 108 , and 110 have active region contact trenches that are shallower than the body regions.
- a body layer of approximately 0.01 ⁇ 0.5 ⁇ m separates the bottom of the active region trench from the epi, forming a low injection diode below the body/drain junction.
- the thickness and the doping level of the thin body layer, which lies between the active region contact trench and the drain, are adjusted so that in reverse bias this thin body layer is almost completely depleted while in forward bias the body layer is not depleted.
- a low injection body diode may provide comparable performance as the Schottky diode, with the advantage of simplified process as formation of Schottky barrier controlling layer can be omitted.
- FIG. 2 is a diagram illustrating a buck converter circuit example.
- circuit 200 is shown to employ a high side FET device 201 and a low side FET device 207 .
- High side device 201 includes a transistor 202 and a body diode 204 .
- Low side device 207 can be implemented using devices such as 100 , 102 , or 104 shown in FIGS. 1A-1F .
- Device 207 includes a transistor 208 , a body diode 210 and a Schottky diode 212 .
- the load includes an inductor 214 , a capacitor 216 and a resistor 218 .
- device 201 is turned on to transfer power from the input source to the load.
- FIG. 3 is a flowchart illustrating an embodiment of a fabrication process for constructing a DMOS device.
- gate trenches are formed in the epi layer overlaying the semiconductor substrate.
- gate material is deposited in the gate trenches.
- the body and the source are formed.
- contact trenches are formed.
- the active region contact trenches and the gate region trenches are formed in a single step; in some embodiments, the trenches are formed in multiple steps to achieve different depth.
- contact electrodes are disposed within the contact trenches. Process 300 and its steps can be modified to produce different embodiments of MOS devices such as 102 - 110 shown in FIGS. 1A-1F .
- FIGS. 4A-4V are device cross-sectional views illustrating in detail an example fabrication process used for fabricating an MOS device.
- an N type substrate i.e., an N silicon wafer with an N epi layer grown on it
- the drain of the device is used as the drain of the device.
- FIGS. 4A-4J shows the formation of the gate.
- a SiO 2 layer 402 is formed on N type substrate 400 by deposition or thermal oxidation.
- the thickness of the silicon oxide ranges from 100 ⁇ to 30000 ⁇ in various embodiments. Other thicknesses can be used. The thickness is adjusted depending on the desired height of the gate.
- a photoresist layer 404 is spun on top of the oxide layer and patterned using a trench mask.
- SiO 2 in the exposed areas is removed, leaving a SiO 2 hard mask 410 for silicon etching.
- the silicon is etched anisotropically, leaving trenches such as 420 .
- the gate material is deposited in the trenches. Gates that are later formed within the trench have sides that are substantially perpendicular to the top surface of the substrate.
- SiO 2 hard mask 410 is etched back by an appropriate amount so that the trench walls remain approximately aligned with the edge of the hard mask after later etching steps.
- SiO 2 is the mask material used in this embodiment because etching using a SiO 2 hard mask leaves relatively straight trench walls that mutually align with the sides of the mask. Other material may be used as appropriate. Certain other types of material traditionally used for hard mask etching, such as Si 3 N 4 , may leave the etched trench walls with a curvature that is less desirable for gate formation in the following steps.
- the substrate is etched isotropically to round out the bottoms of the trenches.
- the trench is approximately between 0.5-2.5 ⁇ m deep and approximately between 0.2-1.5 ⁇ m wide in some embodiments; other dimensions can also be used.
- a sacrificial layer of SiO 2 430 is grown in the trenches. This layer is then removed by the process of wet etching.
- a layer of SiO 2 432 is grown thermally in the trenches as dielectric material.
- poly 440 is deposited to fill up the trenches.
- the poly is doped to obtain the appropriate gate resistance.
- doping takes place as the poly layer is deposited (in situ).
- the poly is doped after the deposition.
- the poly layer on top of the SiO 2 is etched back to form gates such as 442 .
- top surface 444 of the gate is still recessed relative to top surface 448 of the SiO 2 , however, top surface 444 of the gate may be higher than top layer 446 of the silicon, depending on the thickness of hard mask layer 410 .
- no mask is used in poly etch back.
- a mask is used in poly etch back to eliminate the use of an additional mask in the following body implanting process.
- the SiO 2 hard mask is removed.
- dry etch is used for hard mask removal. The etching process stops when the top silicon surface is encountered, leaving the poly gate extending beyond the substrate surface where source and body dopants will be implanted.
- the gate extends beyond the substrate surface by approximately between 300 ⁇ to 20000 ⁇ . Other values can also be used.
- a SiO 2 hard mask is used in these embodiments since it provides the desired amount of gate extension beyond the Si surface in a controllable fashion. A screen oxide may then be grown across the wafer.
- the above processing steps may be simplified for fabricating devices with recessed gate poly. For example, in some embodiments a photoresist mask or a very thin SiO 2 hard mask is used during trench formation, and thus the resulting gate poly does not extend beyond the Si surface.
- FIGS. 4K-4N illustrate the formation of the source and the body.
- a photoresist layer 450 is patterned on the body surface using a body mask. The unmasked regions are implanted with body dopants. Dopants such as Boron ions are implanted. In some embodiments that are not shown here, the body implant is carried out without body block 450 , forming a continuous body region between active trenches.
- the photoresist is removed and the wafer is heated to thermally diffuse the implanted body dopants via a process sometimes referred to as body drive. Body regions 460 a - d are then formed.
- the energy used for implanting the body dopants is approximately between 30 ⁇ 600 keV
- the dose is approximately between 5e12-4e13 ions/cm 2
- the resulting final body depth is approximately between 0.3-2.4 ⁇ m. Different depths can be achieved by varying factors including the implant energy, dose and diffusion temperature.
- An oxide layer 462 is formed during the diffusion process.
- a photoresist layer 464 is patterned using a source mask.
- source mask 464 does not block any area between active trenches.
- source mask 464 also blocks a center area of between active trenches (not shown).
- the unmasked region 466 is implanted with source dopants.
- arsenic ions penetrate the silicon in the unmasked areas to form N + type source.
- the energy used for implanting the source dopants is approximately between 10-100 keV, the dose is approximately between 1e15-1e16 ions/cm 2 , and the resulting source depth is approximately between 0.05-0.5 ⁇ m.
- FIG. 4N the photoresist is removed and the wafer is heated to thermally diffuse the implanted source dopants via a source drive process.
- a dielectric (e.g. BPSG) layer 465 is disposed on the top surface of the device after source drive, and optionally densified in some embodiments.
- FIGS. 4O-4T illustrate the formation of the contact trench and various implants along the contact trench.
- a photoresist layer 472 is deposited on the dielectric layer and patterned using a contact mask.
- a first contact etch is performed to form trenches 468 and 470 .
- the depth of the first contact trench is between 0.2-2.5 ⁇ m.
- the photoresist layer is removed, and the area around the bottom of trench 470 is bombarded with implant ions to form a punch-through prevention layer.
- Boron ions with a dose of approximately 1-5e15 ions/cm 2 are used in some embodiments.
- the implant energy is approximately 10-60 kEv.
- BF 2 ions with a dose of approximately 1-5e15 ions/cm 2 and implant energy of 40-100 kEv are used.
- both BF 2 and Boron are implanted to form the form the punch-through prevention layer.
- the implantation tilt is approximately between 0-45°.
- the implant is thermally diffused.
- a second contact etch takes place. Since the etching process does not affect the dielectric layer, the second contact etch does not require an extra mask. The depth of the trenches is increased by 0.2-0.5 ⁇ m in some embodiments.
- the punch-through prevention layer is etched through, leaving the anti-punch-through implants 474 a - b along the trench wall.
- a low dose shallow P type Schottky barrier controlling layer 476 is formed using ion implantation. In some embodiments, Boron or BF2 with a dosage between 2e11-3e13 ions/cm 2 and implant energy between 10-100 kEv are used. In FIG. 4T , the Schottky barrier controlling layer is activated by thermal diffusion.
- the Schottky barrier controlling layer In comparison to the anti-punch through implant, the Schottky barrier controlling layer requires a lower dose and thus results in a lower doping and thinner layer of implant. In some embodiments, the Schottky barrier controlling layer is approximately 0.01 ⁇ 0.05 ⁇ m thick. The Schottky barrier controlling layer can adjust the barrier height because the implant adjusts the surface energy between the contact electrode and the semiconductor.
- completed device 490 is shown.
- Metal layer 478 is deposited, etched where appropriate, and annealed. Passivation openings are made after a passivation layer 480 is deposited. Additional steps required to complete the fabrication such as wafer grinding and back metal deposition are also performed.
- the body implant process shown in FIG. 4K is modified and no body block in active area.
- Body dopants are directly implanted, blanketing the exposed areas and forming continuous body regions between gates.
- trenches are etched to a depth that is shallower than the bottom of the body region, leaving a body layer below the contact trench.
- active contact trench may be etched just through the body to expose epi drain region followed by an additional body dopant implant with well controlled energy and dopant to form a thin body layer through the contact trench sidewall and bottom.
- a narrow bandgap material such as SiGe is deposited by chemical vapor deposition (CVD) to form a layer on the top surface of an epitaxial layer.
- the thickness of narrow bandgap material layer is in the range from 100 ⁇ to 1000 ⁇ in some embodiments.
- a 200 ⁇ silicon rich SiGe layer is used in some embodiments.
- the silicon rich SiGe layer comprises 80% Si and 20% Ge.
- the narrow bandgap material layer is in-situ doped with N type dopant at a concentration between 2e17 to 2e18/cm 3 .
- a low temperature oxide layer is then deposited over the narrow bandgap layer, and patterned to form a hard mask for dry etching trenches into the epitaxial layer.
- the hard mask protects portions of the narrow bandgap layer underneath during the dry etching process.
- FIGS. 5A-6B illustrates additional alternative embodiments of fabrication steps.
- FIG. 5A follows the punch-through prevention layer diffusion (see FIG. 4Q ).
- a photoresist layer 502 is patterned using a second contact mask to block gate trench 504 .
- a second etch takes place to increase the depth of active region contact trench 506 .
- the photoresist is then removed, and Schottky barrier controlling layer is implanted in a manner similar to FIGS. 4S and 4T . Additional finishing steps including metal deposition and passivation still apply (see FIG. 4U ).
- the resulting device is similar to device 102 of FIG. 1B , where the gate trench has a different depth than the active region contact trench.
- the gate trench contact can be made shallower and alleviate concerns over puncturing the gate poly during etching.
- the process is often used to fabricate devices with short gate polys, including embodiments with gate polys that do not extend above the substrate surface.
- FIG. 6A also follows the punch-through prevention layer diffusion (see FIG. 4Q ).
- a photoresist layer 602 is patterned using a second contact mask to block gate trench 604 and to form a contact opening over active region contact trench 606 that is smaller than the contact opening from the first etch.
- a second contact etch is performed to form a deeper, narrower trench portion 608 .
- the photo resist is removed and remaining steps from FIGS. 4S-4U apply.
- the resulting device is similar to 103 of FIG. 1C .
- FIGS. 7-10 illustrate optional modifications to the fabrication process that are used in some embodiments to further enhance device performance.
- a blanket implant 702 having the opposite polarity as the epitaxial layer is deposited throughout the epi.
- a high energy, low dose of Boron (5e11-1e13, 200-600 keV) is used to form blanket implant 702 before the formation of the main body implant.
- the blanket implant is used to adjust epi profile without resulting in polarity changing in the epi.
- the blanket implant changes the body profile in the body bottom region, and enhances the breakdown voltage without noticeably increasing R dson .
- the optional modification shown in FIG. 8 may take place after the Shannon implant has been deposited ( FIG. 4S ) but prior to its activation ( FIG. 4T ).
- An epitaxial layer profile tuning implant is implanted under the active region contact trench.
- the epitaxial layer profile tuning implant has the opposite polarity as the epi.
- a high energy, low dose of Boron or BF 2 e.g., 5e11-1e13, 60-300 keV
- the implant tunes the epi profile without changing the epi polarity, and enhances the breakdown voltage.
- the optional modification shown in FIG. 9 may take place after the Shannon implant has been deposited ( FIG. 4S ) but prior to its activation ( FIG. 4T ).
- a high energy, medium dose of Boron (1e12-5e13, 60-300 keV) is implanted to form a P type island 902 that is located in the n-type epi under contact trench and disconnected from the body region.
- the floating P type island also enhances breakdown voltage.
- the optional modification shown in FIG. 10 may take place after the contact trench has been made ( FIG. 4O ) and prior to making the Shannon implant ( FIG. 4P ). Since sharp corners tend to accumulate electric charges, creates high electric fields, and lower breakdown voltage, corners of the trench bottom 1002 a - b are rounded to reduce charge accumulation and improve breakdown voltage.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
- This application is a continuation of co-pending U.S. patent application Ser. No. 14/961,582, entitled MOS DEVICE WITH ISLAND REGION filed Dec. 7, 2015 which is incorporated herein by reference for all purposes, which is a continuation of U.S. patent application Ser. No. 14/300,529, now U.S. Pat. No. 9,236,450, entitled FABRICATION OF MOS DEVICE WITH SCHOTTKY BARRIER CONTROLLING LAYER filed Jun. 10, 2014 which is incorporated herein by reference for all purposes, which is a continuation of U.S. patent application Ser. No. 13/725,789, now U.S. Pat. No. 8,809,143, entitled FABRICATION OF MOS DEVICE WITH SCHOTTKY BARRIER CONTROLLING LAYER filed Dec. 21, 2012 which is incorporated herein by reference for all purposes, which is a continuation of U.S. patent application Ser. No. 12/005,166, now U.S. Pat. No. 8,362,547, entitled MOS DEVICE WITH SCHOTTKY BARRIER CONTROLLING LAYER filed Dec. 21, 2007, which is incorporated herein by reference for all purposes, which is a continuation in part of U.S. patent application Ser. No. 11/900,616, now U.S. Pat. No. 7,605,425, entitled POWER MOS DEVICE filed Sep. 11, 2007, which is incorporated herein by reference for all purposes, and which is a continuation of U.S. patent application Ser. No. 11/056,346, now U.S. Pat. No. 7,285,822, entitled POWER MOS DEVICE filed Feb. 11, 2005, which is incorporated herein by reference for all purposes.
- Power MOS devices are commonly used in electronic circuits. Depending on the application, different device characteristics may be desirable. One example application is a DC-DC converter, which includes a power MOS device as a synchronous rectifier (also referred to as the low side FET) and another power MOS device as a control switch (also referred to as the high side FET). The low side FET typically requires a small on-resistance to achieve good power switch efficiency. The high side FET typically requires a small gate capacitance for fast switching and good performance.
- The value of a transistor's on-resistance (Rdson) is typically proportional to the channel length (L) and inversely proportional to the number of active cells per unit area (W). When choosing a value for Rdson, consideration should be given to the tradeoff between performance and breakdown voltage. To reduce the value of Rdson, the channel length can be reduced by using shallower source and body, and the number of cells per unit area can be increased by reducing the cell size. However, the channel length L is typically limited because of the punch-through phenomenon. The number of cells per unit area is limited by manufacturing technology and by the need to make a good contact to both the source and body regions of the cell. As the channel length and the cell density increase, gate capacitance also increases. Lower device capacitance is preferred for reduced switching losses. In some applications such as synchronous rectification, the stored charge and forward drop of the body diode also result in efficiency loss. These factors together tend to limit the performance of DMOS power devices.
- It would be desirable if the on-resistance and the gate capacitance of DMOS power devices could be reduced from the levels currently achievable, so that the reliability and power consumption of the power switch could be improved. It would also be useful to develop a practical process that could reliably manufacture the improved DMOS power devices.
- Various embodiments of the invention are disclosed in the following detailed description and the accompanying drawings.
-
FIGS. 1A-1F illustrate several double-diffused metal oxide semiconductor (DMOS) device embodiments. -
FIG. 2 is a diagram illustrating a buck converter circuit example. -
FIG. 3 is a flowchart illustrating an embodiment of a fabrication process for constructing a DMOS device. -
FIGS. 4A-4U are device cross-sectional views illustrating in detail an example fabrication process used for fabricating an MOS device. -
FIGS. 5A-6B illustrates additional alternative embodiments of fabrication steps. -
FIGS. 7-10 illustrate optional modifications to the fabrication process that are used in some embodiments to further enhance device performance. - The invention can be implemented in numerous ways, including as a process, an apparatus, a system, a composition of matter, a computer readable medium such as a computer readable storage medium or a computer network wherein program instructions are sent over optical or communication links. In this specification, these implementations, or any other form that the invention may take, may be referred to as techniques. A component such as a processor or a memory described as being configured to perform a task includes both a general component that is temporarily configured to perform the task at a given time or a specific component that is manufactured to perform the task. In general, the order of the steps of disclosed processes may be altered within the scope of the invention.
- A detailed description of one or more embodiments of the invention is provided below along with accompanying figures that illustrate the principles of the invention. The invention is described in connection with such embodiments, but the invention is not limited to any embodiment. The scope of the invention is limited only by the claims and the invention encompasses numerous alternatives, modifications and equivalents. Numerous specific details are set forth in the following description in order to provide a thorough understanding of the invention. These details are provided for the purpose of example and the invention may be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the invention has not been described in detail so that the invention is not unnecessarily obscured.
- A metal oxide semiconductor (MOS) device and its fabrication are described. For the purpose of example, N-channel devices with source and drain made of N-type material and body made of P-type material are discussed in detail throughout this specification. The techniques and structures disclosed herein are also applicable to P-channel devices.
-
FIGS. 1A-1F illustrate several double-diffused metal oxide semiconductor (DMOS) device embodiments.FIG. 1A is a cross sectional view of an embodiment of a DMOS device. In this example,device 100 includes a drain that is formed on the back of an N+-type semiconductor substrate 103. The drain region extends into an epitaxial (epi)layer 104 of N−-type semiconductor that overlayssubstrate 103. Gate trenches such as 111, 113, and 115 are etched inepi layer 104. Agate oxide layer 121 is formed inside the gate trenches.Gates gate trenches gate trench 111 is located in a termination region disposed with agate runner 131 for connection to gate contact metal. For that purposegate runner trench 111 may be wider and deeper compared toactive gate trenches gate runner trench 111 from the active trench next to it, in thiscase trench 113, may be larger than the spacing between theactive gate trenches - Source regions 150 a-d are embedded in body regions 140 a-d, respectively. The source regions extend downward from the top surface of the body into the body itself. While body regions are implanted along side of all gate trenches, source regions are only implanted next to active gate trenches and not gate runner trenches. In the embodiment shown, gates such as 133 have a gate top surface that extends substantially above the top surface of the body where the source is embedded. Such a configuration guarantees the overlap of the gate and the source, allowing the source region to be shallower than the source region of a device with a recessed gate, and increases device efficiency and performance. The amount by which the gate poly top surface extends above the source-body junction may vary for different embodiments. In some embodiments, the gates of the device do not extend above the top surface of the source/body region, rather recess from the top surface of the source/body region.
- During operation, the drain region and the body regions together act as a diode, referred to as the body diode. A dielectric material layer 160 is disposed over the gate to insulate the gate from source-body contact. The dielectric material forms insulating regions such as 160 a-c on top of the gates as well as on top of the body and source regions. Appropriate dielectric materials include thermal oxide, low temperature oxide (LTO), boro-phospho-silicate glass (BPSG), etc.
- A number of contact trenches 112 a-b are formed between the active gate trenches near the source and body regions. These trenches are referred to as active region contact trenches since the trenches are adjacent to the device's active region that is formed by the source and body regions. For example,
contact trench 112 a extends through the source and the body, forming source regions 150 a-b and body regions 140 a-b adjacent to the trench. In contrast,trench 117, which is formed on top ofgate runner 131, is not located next to an active region, and therefore is not an active region contact trench.Trench 117 is referred to as a gate contact trench or gate runner trench since ametal layer 172 a connected to the gate signal is deposited within the trench. Gate signal is fed toactive gates trenches Metal layer 172 a is separated frommetal layer 172 b, which connects to source and body regions through contact trenches 112 a-b to supply a power source. In the example shown, the active region contact trenches and gate contact trench have approximately the same depth. -
Device 100 has active region contact trenches 112 a-b that are shallower than the body. This configuration provides good breakdown characteristics as well as lower resistance and leakage current. Additionally, since the active contact trenches and gate contact trench are formed using a one step process therefore have the same depth, having active contact trenches that are shallower than the body prevents the gate runner such as 131 from being penetrated by the gate contact trench. - In the example shown, the FET channel is formed along the active region gate trench sidewall between the source/body and body/drain junctions. In a device with a short channel region, as the voltage between the source and the drain increases, the depletion region expands and may eventually reach the source junction. This phenomenon, referred to as punch through, limits the extent to which the channel may be shortened. In some embodiments, to prevent punch through, regions such as 170 a-d along the walls of the active region contact trench are heavily doped with P type material to form P+-type regions. The P+-type regions prevent the depletion region from encroaching upon the source region. Thus, these implants are sometimes referred to as anti-punch through implants or punch through prevention implants. In some embodiments, to achieve pronounced anti-punch through effects, the P+ regions are disposed as close as possible to the channel region and/or as close as it is allowed by manufacturing alignment capability and P+ sidewall dopant penetration control. In some embodiments, the misalignment between the trench contact and the trench is minimized by self-aligning the contact, and the trench contact is placed as closely centered between the trenches as possible. These structural enhancements allow the channel to be shortened such that the net charge in the channel per unit area is well below the minimum charge needed to prevent punch through in an ideal unprotected structure. In addition to improving body contact resistance, the anti-punch through implants also makes it possible to construct very shallow trench short-channel devices. In the embodiment shown, contact trenches 112 a-b are shallower than body regions 140 a-d and do not extend all the way through the body regions. The device's on-resistance Rdson as well as the gate capacitance are reduced.
- A conductive material is disposed in contact trenches 112 a-b as well as
gate trench 117 to form contact electrodes. In the active region, since the punch-through implants are disposed along the sidewalls of the contact trenches but not along the bottoms of the contact trenches, the contact electrodes are in contact withN drain region 104. Together, the contact electrodes and the drain region form Schottky diodes that are in parallel with the body diode. The Schottky diodes reduce the body diode forward drop and minimize the stored charge, making the MOSFET more efficient. A single metal that is capable of simultaneously forming a Schottky contact to the N− drain and forming good Ohmic contact to the P+ body and N+ source is used to form electrodes 180 a-b. Metals such as titanium (Ti), platinum (Pt), palladium (Pd), tungsten (W) or any other appropriate material may be used. In some embodiments, metal layer 172 is made of aluminum (Al) or made of a Ti/TiN/A1 stack. - The leakage current of the Schottky diode is related to the Schottky barrier height. As the barrier height increases, the leakage current decreases, and the forward drop voltage also increases. In the example shown, optional Schottky barrier controlling layers 190 a-b (also known as Shannon layers) are formed below the contact electrode, by implanting thin layers of dopants around the bottoms of active region trenches 112 a-b. The dopants have opposite polarity as the epi layer and are of P type in this example. The Shannon implant is shallow and low dosage; therefore, it is completely depleted regardless of bias. The Schottky barrier controlling layer is used to control the Schottky barrier height, thus allowing for better control over the leakage current and improving the reverse recovery characteristics of the Schottky diode. Details of the formation of the Schottky barrier controlling layer are described below.
-
FIG. 1B is a cross sectional view of another embodiment of a DMOS device.Device 102 also includes Schottky barrier controlling layers 190 a-b around the bottoms of the active region contact trenches. In this example, the depth ofgate contact trench 117 is different from that of active region contact trenches 112-b. The active region contact trenches are deeper than body regions 140 a-d and extend beyond the body regions. Since the active contact trench is deeper, it provides more area for making Ohmic contact along the sidewalls and results in better unclamped inductive switching (UIS) capability. Furthermore, by making the gate contact trench shallower than the active contact trenches, it is unlikely that the gate contact trench would penetrate the gate runner poly during the etching process, which is useful for devices with relatively shallow gate polys (such as devices fabricated using processes that result in gate polys that do not extend above the body top surface). -
FIG. 1C is another embodiment of a DMOS device. In this example,gate contact trench 117 and active region contact trenches 112 a-b have different depths. Further, the depth of each of the active region contact trenches is non-uniform since the trench depth varies in the direction parallel to the substrate surface. As will be described in more detail below, the active region contact trenches are formed using a 2-step process, resulting in a first contact opening (e.g. 112 a-b) that is wider than a second contact opening (e.g. 119 a-b). The shape of the profile of the active region contact trench allows for greater Ohmic contact area and better punch-through prevention by anti-punch through implants 170 a-d, and improves the device's UIS capability. Shannon implants distribute around the sidewall and bottom of the second contact opening, forming a Schottky barrier controlling layer 190 a-b. -
FIGS. 1D-1F illustrate embodiments of DMOS devices with integrated low injection body diode.Devices devices -
FIG. 2 is a diagram illustrating a buck converter circuit example. In this example,circuit 200 is shown to employ a highside FET device 201 and a lowside FET device 207.High side device 201 includes atransistor 202 and abody diode 204.Low side device 207 can be implemented using devices such as 100, 102, or 104 shown inFIGS. 1A-1F .Device 207 includes atransistor 208, abody diode 210 and aSchottky diode 212. The load includes aninductor 214, acapacitor 216 and aresistor 218. During normal operation,device 201 is turned on to transfer power from the input source to the load. This causes the current to ramp up in the inductor. Whendevice 201 is turned off, the inductor current still flows and commutates tobody diode 210 ofdevice 207. After a short delay, the control circuit turns ondevice 207, which turns on the channel oftransistor 208 and dramatically reduces the forward drop across the drain-source terminals ofdevice 208. WithoutSchottky diode 212, the body diode conduction loss and the losses from removing the stored charge inbody diode 210 ofdevice 207 can be substantial. However, ifSchottky diode 212 is built intodevice 207 and if the Schottky diode has a low forward drop, the conduction loss is greatly reduced. Since the low forward drop across the Schottky diode is lower than the junction drop of the body diode, no stored charge is injected while the Schottky diode conducts, further improving the losses related to diode recovery. -
FIG. 3 is a flowchart illustrating an embodiment of a fabrication process for constructing a DMOS device. At 302, gate trenches are formed in the epi layer overlaying the semiconductor substrate. At 304, gate material is deposited in the gate trenches. At 306 and 308, the body and the source are formed. At 310, contact trenches are formed. As will be discussed in further detail below, in some embodiments, the active region contact trenches and the gate region trenches are formed in a single step; in some embodiments, the trenches are formed in multiple steps to achieve different depth. At 312, contact electrodes are disposed within the contact trenches.Process 300 and its steps can be modified to produce different embodiments of MOS devices such as 102-110 shown inFIGS. 1A-1F . -
FIGS. 4A-4V are device cross-sectional views illustrating in detail an example fabrication process used for fabricating an MOS device. In this example, an N type substrate (i.e., an N silicon wafer with an N epi layer grown on it) is used as the drain of the device. -
FIGS. 4A-4J shows the formation of the gate. InFIG. 4A , a SiO2 layer 402 is formed onN type substrate 400 by deposition or thermal oxidation. The thickness of the silicon oxide ranges from 100 Å to 30000 Å in various embodiments. Other thicknesses can be used. The thickness is adjusted depending on the desired height of the gate. Aphotoresist layer 404 is spun on top of the oxide layer and patterned using a trench mask. - In
FIG. 4B , the SiO2 in the exposed areas is removed, leaving a SiO2hard mask 410 for silicon etching. InFIG. 4C , the silicon is etched anisotropically, leaving trenches such as 420. The gate material is deposited in the trenches. Gates that are later formed within the trench have sides that are substantially perpendicular to the top surface of the substrate. InFIG. 4D , SiO2hard mask 410 is etched back by an appropriate amount so that the trench walls remain approximately aligned with the edge of the hard mask after later etching steps. SiO2 is the mask material used in this embodiment because etching using a SiO2 hard mask leaves relatively straight trench walls that mutually align with the sides of the mask. Other material may be used as appropriate. Certain other types of material traditionally used for hard mask etching, such as Si3N4, may leave the etched trench walls with a curvature that is less desirable for gate formation in the following steps. - In
FIG. 4E , the substrate is etched isotropically to round out the bottoms of the trenches. The trench is approximately between 0.5-2.5 μm deep and approximately between 0.2-1.5 μm wide in some embodiments; other dimensions can also be used. To provide a smooth surface for growing gate dielectric material, a sacrificial layer ofSiO 2 430 is grown in the trenches. This layer is then removed by the process of wet etching. InFIG. 4G , a layer ofSiO 2 432 is grown thermally in the trenches as dielectric material. - In
FIG. 4H ,poly 440 is deposited to fill up the trenches. In this case, the poly is doped to obtain the appropriate gate resistance. In some embodiments, doping takes place as the poly layer is deposited (in situ). In some embodiments, the poly is doped after the deposition. InFIG. 4I , the poly layer on top of the SiO2 is etched back to form gates such as 442. At this point,top surface 444 of the gate is still recessed relative totop surface 448 of the SiO2, however,top surface 444 of the gate may be higher thantop layer 446 of the silicon, depending on the thickness ofhard mask layer 410. In some embodiments, no mask is used in poly etch back. In some embodiments, a mask is used in poly etch back to eliminate the use of an additional mask in the following body implanting process. InFIG. 4J , the SiO2 hard mask is removed. In some embodiments, dry etch is used for hard mask removal. The etching process stops when the top silicon surface is encountered, leaving the poly gate extending beyond the substrate surface where source and body dopants will be implanted. In some embodiments, the gate extends beyond the substrate surface by approximately between 300 Å to 20000 Å. Other values can also be used. A SiO2 hard mask is used in these embodiments since it provides the desired amount of gate extension beyond the Si surface in a controllable fashion. A screen oxide may then be grown across the wafer. The above processing steps may be simplified for fabricating devices with recessed gate poly. For example, in some embodiments a photoresist mask or a very thin SiO2 hard mask is used during trench formation, and thus the resulting gate poly does not extend beyond the Si surface. -
FIGS. 4K-4N illustrate the formation of the source and the body. InFIG. 4K , aphotoresist layer 450 is patterned on the body surface using a body mask. The unmasked regions are implanted with body dopants. Dopants such as Boron ions are implanted. In some embodiments that are not shown here, the body implant is carried out withoutbody block 450, forming a continuous body region between active trenches. InFIG. 4L , the photoresist is removed and the wafer is heated to thermally diffuse the implanted body dopants via a process sometimes referred to as body drive. Body regions 460 a-d are then formed. In some embodiments, the energy used for implanting the body dopants is approximately between 30˜600 keV, the dose is approximately between 5e12-4e13 ions/cm2, and the resulting final body depth is approximately between 0.3-2.4 μm. Different depths can be achieved by varying factors including the implant energy, dose and diffusion temperature. Anoxide layer 462 is formed during the diffusion process. - In
FIG. 4M , aphotoresist layer 464 is patterned using a source mask. In the embodiment shown,source mask 464 does not block any area between active trenches. In some embodiments,source mask 464 also blocks a center area of between active trenches (not shown). Theunmasked region 466 is implanted with source dopants. In this example, arsenic ions penetrate the silicon in the unmasked areas to form N+ type source. In some embodiments, the energy used for implanting the source dopants is approximately between 10-100 keV, the dose is approximately between 1e15-1e16 ions/cm2, and the resulting source depth is approximately between 0.05-0.5 μm. Further depth reduction can be achieved by varying factors such as the doping energy and dose. Other implant processes may also be used as appropriate. InFIG. 4N , the photoresist is removed and the wafer is heated to thermally diffuse the implanted source dopants via a source drive process. A dielectric (e.g. BPSG)layer 465 is disposed on the top surface of the device after source drive, and optionally densified in some embodiments. -
FIGS. 4O-4T illustrate the formation of the contact trench and various implants along the contact trench. InFIG. 4O , aphotoresist layer 472 is deposited on the dielectric layer and patterned using a contact mask. A first contact etch is performed to formtrenches - In
FIG. 4P , the photoresist layer is removed, and the area around the bottom oftrench 470 is bombarded with implant ions to form a punch-through prevention layer. Boron ions with a dose of approximately 1-5e15 ions/cm2 are used in some embodiments. The implant energy is approximately 10-60 kEv. In some embodiments, BF2 ions with a dose of approximately 1-5e15 ions/cm2 and implant energy of 40-100 kEv are used. In some embodiments, both BF2 and Boron are implanted to form the form the punch-through prevention layer. The implantation tilt is approximately between 0-45°. InFIG. 4Q , the implant is thermally diffused. - In
FIG. 4R , a second contact etch takes place. Since the etching process does not affect the dielectric layer, the second contact etch does not require an extra mask. The depth of the trenches is increased by 0.2-0.5 μm in some embodiments. The punch-through prevention layer is etched through, leaving the anti-punch-through implants 474 a-b along the trench wall. InFIG. 4S , a low dose shallow P type Schottkybarrier controlling layer 476 is formed using ion implantation. In some embodiments, Boron or BF2 with a dosage between 2e11-3e13 ions/cm2 and implant energy between 10-100 kEv are used. InFIG. 4T , the Schottky barrier controlling layer is activated by thermal diffusion. In comparison to the anti-punch through implant, the Schottky barrier controlling layer requires a lower dose and thus results in a lower doping and thinner layer of implant. In some embodiments, the Schottky barrier controlling layer is approximately 0.01˜0.05 μm thick. The Schottky barrier controlling layer can adjust the barrier height because the implant adjusts the surface energy between the contact electrode and the semiconductor. - In
FIG. 4U , completed device 490 is shown.Metal layer 478 is deposited, etched where appropriate, and annealed. Passivation openings are made after apassivation layer 480 is deposited. Additional steps required to complete the fabrication such as wafer grinding and back metal deposition are also performed. - Alternative processes may be used. For example, to fabricate devices 106-110 shown in
FIGS. 1D-1F , the body implant process shown inFIG. 4K is modified and no body block in active area. Body dopants are directly implanted, blanketing the exposed areas and forming continuous body regions between gates. During contact etch, trenches are etched to a depth that is shallower than the bottom of the body region, leaving a body layer below the contact trench. Alternatively, active contact trench may be etched just through the body to expose epi drain region followed by an additional body dopant implant with well controlled energy and dopant to form a thin body layer through the contact trench sidewall and bottom. - In some embodiments, to form the Schottky barrier controlling layer, a narrow bandgap material such as SiGe is deposited by chemical vapor deposition (CVD) to form a layer on the top surface of an epitaxial layer. The thickness of narrow bandgap material layer is in the range from 100 Å to 1000 Å in some embodiments. For example, a 200 Å silicon rich SiGe layer is used in some embodiments. In some embodiments, the silicon rich SiGe layer comprises 80% Si and 20% Ge. In some embodiments, the narrow bandgap material layer is in-situ doped with N type dopant at a concentration between 2e17 to 2e18/cm3. A low temperature oxide layer is then deposited over the narrow bandgap layer, and patterned to form a hard mask for dry etching trenches into the epitaxial layer. The hard mask protects portions of the narrow bandgap layer underneath during the dry etching process.
-
FIGS. 5A-6B illustrates additional alternative embodiments of fabrication steps. For example,FIG. 5A follows the punch-through prevention layer diffusion (seeFIG. 4Q ). Aphotoresist layer 502 is patterned using a second contact mask to blockgate trench 504. InFIG. 5B , a second etch takes place to increase the depth of activeregion contact trench 506. The photoresist is then removed, and Schottky barrier controlling layer is implanted in a manner similar toFIGS. 4S and 4T . Additional finishing steps including metal deposition and passivation still apply (seeFIG. 4U ). The resulting device is similar todevice 102 ofFIG. 1B , where the gate trench has a different depth than the active region contact trench. By using a separate mask for the second contact trench etching to achieve different gate trench and active region contact trench depths, the gate trench contact can be made shallower and alleviate concerns over puncturing the gate poly during etching. Thus, the process is often used to fabricate devices with short gate polys, including embodiments with gate polys that do not extend above the substrate surface. -
FIG. 6A also follows the punch-through prevention layer diffusion (seeFIG. 4Q ). Aphotoresist layer 602 is patterned using a second contact mask to blockgate trench 604 and to form a contact opening over activeregion contact trench 606 that is smaller than the contact opening from the first etch. InFIG. 6B , a second contact etch is performed to form a deeper,narrower trench portion 608. The photo resist is removed and remaining steps fromFIGS. 4S-4U apply. The resulting device is similar to 103 ofFIG. 1C . -
FIGS. 7-10 illustrate optional modifications to the fabrication process that are used in some embodiments to further enhance device performance. - The optional modification shown in
FIG. 7 may take place after the gates have been formed (FIG. 4G ) and prior to applying the body block mask (FIG. 4K ). Ablanket implant 702 having the opposite polarity as the epitaxial layer is deposited throughout the epi. In some embodiments, a high energy, low dose of Boron (5e11-1e13, 200-600 keV) is used to formblanket implant 702 before the formation of the main body implant. The blanket implant is used to adjust epi profile without resulting in polarity changing in the epi. The blanket implant changes the body profile in the body bottom region, and enhances the breakdown voltage without noticeably increasing Rdson. - The optional modification shown in
FIG. 8 may take place after the Shannon implant has been deposited (FIG. 4S ) but prior to its activation (FIG. 4T ). An epitaxial layer profile tuning implant is implanted under the active region contact trench. The epitaxial layer profile tuning implant has the opposite polarity as the epi. In some embodiments a high energy, low dose of Boron or BF2 (e.g., 5e11-1e13, 60-300 keV) is used for the implant. The implant tunes the epi profile without changing the epi polarity, and enhances the breakdown voltage. - The optional modification shown in
FIG. 9 may take place after the Shannon implant has been deposited (FIG. 4S ) but prior to its activation (FIG. 4T ). A high energy, medium dose of Boron (1e12-5e13, 60-300 keV) is implanted to form a P type island 902 that is located in the n-type epi under contact trench and disconnected from the body region. The floating P type island also enhances breakdown voltage. - The optional modification shown in
FIG. 10 may take place after the contact trench has been made (FIG. 4O ) and prior to making the Shannon implant (FIG. 4P ). Since sharp corners tend to accumulate electric charges, creates high electric fields, and lower breakdown voltage, corners of the trench bottom 1002 a-b are rounded to reduce charge accumulation and improve breakdown voltage. - Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, the invention is not limited to the details provided. There are many alternative ways of implementing the invention. The disclosed embodiments are illustrative and not restrictive.
Claims (18)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/051,016 US10535764B2 (en) | 2005-02-11 | 2018-07-31 | Device and fabrication of MOS device with island region |
US16/705,029 US10978585B2 (en) | 2005-02-11 | 2019-12-05 | MOS device with island region |
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/056,346 US7285822B2 (en) | 2005-02-11 | 2005-02-11 | Power MOS device |
US11/900,616 US7605425B2 (en) | 2005-02-11 | 2007-09-11 | Power MOS device |
US12/005,166 US8362547B2 (en) | 2005-02-11 | 2007-12-21 | MOS device with Schottky barrier controlling layer |
US13/725,789 US8809143B2 (en) | 2005-02-11 | 2012-12-21 | Fabrication of MOS device with schottky barrier controlling layer |
US14/300,529 US9236450B2 (en) | 2005-02-11 | 2014-06-10 | Fabrication of MOS device with schottky barrier controlling layer |
US14/961,582 US10074742B2 (en) | 2005-02-11 | 2015-12-07 | MOS device with island region |
US16/051,016 US10535764B2 (en) | 2005-02-11 | 2018-07-31 | Device and fabrication of MOS device with island region |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/961,582 Continuation US10074742B2 (en) | 2005-02-11 | 2015-12-07 | MOS device with island region |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/705,029 Continuation US10978585B2 (en) | 2005-02-11 | 2019-12-05 | MOS device with island region |
Publications (2)
Publication Number | Publication Date |
---|---|
US20180337274A1 true US20180337274A1 (en) | 2018-11-22 |
US10535764B2 US10535764B2 (en) | 2020-01-14 |
Family
ID=40430886
Family Applications (6)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/005,166 Active 2028-07-19 US8362547B2 (en) | 2005-02-11 | 2007-12-21 | MOS device with Schottky barrier controlling layer |
US13/725,789 Active US8809143B2 (en) | 2005-02-11 | 2012-12-21 | Fabrication of MOS device with schottky barrier controlling layer |
US14/300,529 Active US9236450B2 (en) | 2005-02-11 | 2014-06-10 | Fabrication of MOS device with schottky barrier controlling layer |
US14/961,582 Active US10074742B2 (en) | 2005-02-11 | 2015-12-07 | MOS device with island region |
US16/051,016 Active US10535764B2 (en) | 2005-02-11 | 2018-07-31 | Device and fabrication of MOS device with island region |
US16/705,029 Active US10978585B2 (en) | 2005-02-11 | 2019-12-05 | MOS device with island region |
Family Applications Before (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/005,166 Active 2028-07-19 US8362547B2 (en) | 2005-02-11 | 2007-12-21 | MOS device with Schottky barrier controlling layer |
US13/725,789 Active US8809143B2 (en) | 2005-02-11 | 2012-12-21 | Fabrication of MOS device with schottky barrier controlling layer |
US14/300,529 Active US9236450B2 (en) | 2005-02-11 | 2014-06-10 | Fabrication of MOS device with schottky barrier controlling layer |
US14/961,582 Active US10074742B2 (en) | 2005-02-11 | 2015-12-07 | MOS device with island region |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/705,029 Active US10978585B2 (en) | 2005-02-11 | 2019-12-05 | MOS device with island region |
Country Status (1)
Country | Link |
---|---|
US (6) | US8362547B2 (en) |
Families Citing this family (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8093651B2 (en) * | 2005-02-11 | 2012-01-10 | Alpha & Omega Semiconductor Limited | MOS device with integrated schottky diode in active region contact trench |
US8362547B2 (en) | 2005-02-11 | 2013-01-29 | Alpha & Omega Semiconductor Limited | MOS device with Schottky barrier controlling layer |
US8362552B2 (en) * | 2008-12-23 | 2013-01-29 | Alpha And Omega Semiconductor Incorporated | MOSFET device with reduced breakdown voltage |
US8969950B2 (en) * | 2008-12-23 | 2015-03-03 | Alpha & Omega Semiconductor, Inc. | Integrated MOSFET-Schottky diode device with reduced source and body Kelvin contact impedance and breakdown voltage |
US7767526B1 (en) * | 2009-01-29 | 2010-08-03 | Alpha & Omega Semiconductor Incorporated | High density trench MOSFET with single mask pre-defined gate and contact trenches |
CN102104026B (en) * | 2009-12-18 | 2013-09-11 | 上海华虹Nec电子有限公司 | Method for manufacturing power metal oxide semiconductor (MOS) transistor device integrated with Schottky diodes |
US9246019B2 (en) * | 2010-12-17 | 2016-01-26 | Diodes Incorporated | High efficiency rectifier |
CN102231386A (en) * | 2011-06-28 | 2011-11-02 | 上海宏力半导体制造有限公司 | TMBS (Trench MOSFET Barrier Schottky) device and manufacturing method thereof |
US8610235B2 (en) | 2011-09-22 | 2013-12-17 | Alpha And Omega Semiconductor Incorporated | Trench MOSFET with integrated Schottky barrier diode |
US8785278B2 (en) | 2012-02-02 | 2014-07-22 | Alpha And Omega Semiconductor Incorporated | Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact |
CN103633088B (en) * | 2012-08-15 | 2016-06-08 | 上海华虹宏力半导体制造有限公司 | The manufacture method of the power diode of low forward voltage drop fast time of recovery |
CN103928513B (en) | 2013-01-15 | 2017-03-29 | 无锡华润上华半导体有限公司 | A kind of trench-dmos devices and preparation method thereof |
CN103151270A (en) * | 2013-02-26 | 2013-06-12 | 上海宏力半导体制造有限公司 | Manufacturing method for schottky barrier component of grooved metal-oxide semiconductor |
TW201440118A (en) * | 2013-04-11 | 2014-10-16 | Anpec Electronics Corp | Method for fabricating semiconductor power device |
KR101999407B1 (en) | 2013-05-23 | 2019-10-02 | 매그나칩 반도체 유한회사 | Semiconductor device with embedded schottky diode and manufacture method thereof |
US9331197B2 (en) | 2013-08-08 | 2016-05-03 | Cree, Inc. | Vertical power transistor device |
US10868169B2 (en) | 2013-09-20 | 2020-12-15 | Cree, Inc. | Monolithically integrated vertical power transistor and bypass diode |
US9318597B2 (en) | 2013-09-20 | 2016-04-19 | Cree, Inc. | Layout configurations for integrating schottky contacts into a power transistor device |
US20150084063A1 (en) * | 2013-09-20 | 2015-03-26 | Cree, Inc. | Semiconductor device with a current spreading layer |
US10600903B2 (en) | 2013-09-20 | 2020-03-24 | Cree, Inc. | Semiconductor device including a power transistor device and bypass diode |
US9318598B2 (en) * | 2014-05-30 | 2016-04-19 | Texas Instruments Incorporated | Trench MOSFET having reduced gate charge |
JP6763779B2 (en) * | 2014-11-18 | 2020-09-30 | ローム株式会社 | Semiconductor devices and methods for manufacturing semiconductor devices |
KR102415409B1 (en) * | 2015-09-09 | 2022-07-04 | 에스케이하이닉스 주식회사 | EPROM cell, method of fabricating the EPROM cell, and EPROM cell array |
TWI576920B (en) * | 2015-11-20 | 2017-04-01 | 敦南科技股份有限公司 | Diode device and manufacturing method thereof |
DE102016101545B4 (en) * | 2016-01-28 | 2020-10-08 | Infineon Technologies Dresden Gmbh | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH SILICIDE LAYERS AND A SEMICONDUCTOR DEVICE |
US10388781B2 (en) | 2016-05-20 | 2019-08-20 | Alpha And Omega Semiconductor Incorporated | Device structure having inter-digitated back to back MOSFETs |
US10056461B2 (en) | 2016-09-30 | 2018-08-21 | Alpha And Omega Semiconductor Incorporated | Composite masking self-aligned trench MOSFET |
US10103140B2 (en) | 2016-10-14 | 2018-10-16 | Alpha And Omega Semiconductor Incorporated | Switch circuit with controllable phase node ringing |
US9941162B1 (en) | 2016-11-17 | 2018-04-10 | Globalfoundries Inc. | Self-aligned middle of the line (MOL) contacts |
US9929048B1 (en) | 2016-12-22 | 2018-03-27 | Globalfoundries Inc. | Middle of the line (MOL) contacts with two-dimensional self-alignment |
US10026824B1 (en) | 2017-01-18 | 2018-07-17 | Globalfoundries Inc. | Air-gap gate sidewall spacer and method |
CN108573926B (en) * | 2017-03-09 | 2020-01-21 | 联华电子股份有限公司 | Semiconductor memory device and method of manufacturing the same |
US11081554B2 (en) * | 2017-10-12 | 2021-08-03 | Semiconductor Components Industries, Llc | Insulated gate semiconductor device having trench termination structure and method |
US10770396B2 (en) * | 2018-12-28 | 2020-09-08 | Vanguard International Semiconductor Corporation | Semiconductor structure and method for fabricating the same |
US11527627B2 (en) | 2020-01-14 | 2022-12-13 | Diodes Incorporated | Semiconductor Schottky rectifier device |
JP7337739B2 (en) * | 2020-03-19 | 2023-09-04 | 株式会社東芝 | semiconductor equipment |
JP7339933B2 (en) * | 2020-09-11 | 2023-09-06 | 株式会社東芝 | semiconductor equipment |
CN113437153B (en) * | 2021-06-23 | 2022-02-22 | 深圳真茂佳半导体有限公司 | Field effect transistor structure with embedded gate among multiple grooves and manufacturing method thereof |
Family Cites Families (68)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4156246A (en) * | 1977-05-25 | 1979-05-22 | Bell Telephone Laboratories, Incorporated | Combined ohmic and Schottky output transistors for logic circuit |
GB2111745B (en) * | 1981-12-07 | 1985-06-19 | Philips Electronic Associated | Insulated-gate field-effect transistors |
JPH0693512B2 (en) * | 1986-06-17 | 1994-11-16 | 日産自動車株式会社 | Vertical MOSFET |
US5164325A (en) * | 1987-10-08 | 1992-11-17 | Siliconix Incorporated | Method of making a vertical current flow field effect transistor |
US4967245A (en) * | 1988-03-14 | 1990-10-30 | Siliconix Incorporated | Trench power MOSFET device |
US4967243A (en) * | 1988-07-19 | 1990-10-30 | General Electric Company | Power transistor structure with high speed integral antiparallel Schottky diode |
US5111253A (en) * | 1989-05-09 | 1992-05-05 | General Electric Company | Multicellular FET having a Schottky diode merged therewith |
JPH03109775A (en) | 1989-09-25 | 1991-05-09 | Hitachi Ltd | Insulation-gate-type semiconductor device |
JPH05304297A (en) * | 1992-01-29 | 1993-11-16 | Nec Corp | Semiconductor power device and manufacture thereof |
JP3109775B2 (en) | 1993-02-18 | 2000-11-20 | 永大産業株式会社 | Wood material heat treatment method |
GB9306895D0 (en) * | 1993-04-01 | 1993-05-26 | Philips Electronics Uk Ltd | A method of manufacturing a semiconductor device comprising an insulated gate field effect device |
GB9313843D0 (en) * | 1993-07-05 | 1993-08-18 | Philips Electronics Uk Ltd | A semiconductor device comprising an insulated gate field effect transistor |
DE4435458C2 (en) | 1994-10-04 | 1998-07-02 | Siemens Ag | Semiconductor component controllable by field effect |
US5489797A (en) * | 1994-12-19 | 1996-02-06 | Sgs-Thomson Microelectronics, Inc. | Local interconnect structure |
JPH08204179A (en) * | 1995-01-26 | 1996-08-09 | Fuji Electric Co Ltd | Silicon carbide trench mosfet |
JP3325736B2 (en) * | 1995-02-09 | 2002-09-17 | 三菱電機株式会社 | Insulated gate semiconductor device |
JPH08264772A (en) | 1995-03-23 | 1996-10-11 | Toyota Motor Corp | Field-effect type semiconductor element |
GB9512089D0 (en) | 1995-06-14 | 1995-08-09 | Evans Jonathan L | Semiconductor device fabrication |
JPH09102602A (en) | 1995-10-05 | 1997-04-15 | Nippon Telegr & Teleph Corp <Ntt> | Mosfet |
US5886383A (en) * | 1997-01-10 | 1999-03-23 | International Rectifier Corporation | Integrated schottky diode and mosgated device |
US6110799A (en) * | 1997-06-30 | 2000-08-29 | Intersil Corporation | Trench contact process |
US6037628A (en) * | 1997-06-30 | 2000-03-14 | Intersil Corporation | Semiconductor structures with trench contacts |
GB9815021D0 (en) * | 1998-07-11 | 1998-09-09 | Koninkl Philips Electronics Nv | Semiconductor power device manufacture |
AU1117500A (en) * | 1998-10-16 | 2000-05-08 | Paratek Microwave, Inc. | Voltage tunable varactors and tunable devices including such varactors |
US6351018B1 (en) * | 1999-02-26 | 2002-02-26 | Fairchild Semiconductor Corporation | Monolithically integrated trench MOSFET and Schottky diode |
US6188105B1 (en) * | 1999-04-01 | 2001-02-13 | Intersil Corporation | High density MOS-gated power device and process for forming same |
JP3647676B2 (en) * | 1999-06-30 | 2005-05-18 | 株式会社東芝 | Semiconductor device |
JP2001085685A (en) * | 1999-09-13 | 2001-03-30 | Shindengen Electric Mfg Co Ltd | Transistor |
US6433396B1 (en) * | 1999-10-05 | 2002-08-13 | International Rectifier Corporation | Trench MOSFET with integrated schottky device and process for its manufacture |
GB9928285D0 (en) * | 1999-11-30 | 2000-01-26 | Koninkl Philips Electronics Nv | Manufacture of trench-gate semiconductor devices |
DE10026740C2 (en) * | 2000-05-30 | 2002-04-11 | Infineon Technologies Ag | Semiconductor switching element with integrated Schottky diode and method for its production |
US6445035B1 (en) * | 2000-07-24 | 2002-09-03 | Fairchild Semiconductor Corporation | Power MOS device with buried gate and groove |
US6818946B1 (en) * | 2000-08-28 | 2004-11-16 | Semiconductor Components Industries, L.L.C. | Trench MOSFET with increased channel density |
US6707127B1 (en) * | 2000-08-31 | 2004-03-16 | General Semiconductor, Inc. | Trench schottky rectifier |
US6608350B2 (en) * | 2000-12-07 | 2003-08-19 | International Rectifier Corporation | High voltage vertical conduction superjunction semiconductor device |
US6710403B2 (en) * | 2002-07-30 | 2004-03-23 | Fairchild Semiconductor Corporation | Dual trench power MOSFET |
US7345342B2 (en) * | 2001-01-30 | 2008-03-18 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
US6998678B2 (en) * | 2001-05-17 | 2006-02-14 | Infineon Technologies Ag | Semiconductor arrangement with a MOS-transistor and a parallel Schottky-diode |
JP4225711B2 (en) * | 2001-06-29 | 2009-02-18 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
TW541969U (en) * | 2001-07-31 | 2003-07-11 | Forhouse Corp | Improvement of transmission wheel for jogging treadmill |
US6621107B2 (en) * | 2001-08-23 | 2003-09-16 | General Semiconductor, Inc. | Trench DMOS transistor with embedded trench schottky rectifier |
US6566201B1 (en) | 2001-12-31 | 2003-05-20 | General Semiconductor, Inc. | Method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion |
US6838722B2 (en) * | 2002-03-22 | 2005-01-04 | Siliconix Incorporated | Structures of and methods of fabricating trench-gated MIS devices |
US6784505B2 (en) * | 2002-05-03 | 2004-08-31 | Fairchild Semiconductor Corporation | Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique |
JP2004055803A (en) | 2002-07-19 | 2004-02-19 | Renesas Technology Corp | Semiconductor device |
ITMI20022700A1 (en) * | 2002-12-20 | 2004-06-21 | St Microelectronics Srl | INTEGRATED DEVICE WITH SCHOTTKY DIODE AND MOS TRANSITOR |
KR100459872B1 (en) * | 2003-05-07 | 2004-12-03 | 삼성전자주식회사 | Buried channel transistor having trench gate and Method of manufacturing the same |
US7652326B2 (en) * | 2003-05-20 | 2010-01-26 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
JP4945055B2 (en) * | 2003-08-04 | 2012-06-06 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
US6987305B2 (en) * | 2003-08-04 | 2006-01-17 | International Rectifier Corporation | Integrated FET and schottky device |
JP4176734B2 (en) * | 2004-05-14 | 2008-11-05 | 株式会社東芝 | Trench MOSFET |
JP2006049341A (en) * | 2004-07-30 | 2006-02-16 | Renesas Technology Corp | Semiconductor device and manufacturing method thereof |
US7667264B2 (en) * | 2004-09-27 | 2010-02-23 | Alpha And Omega Semiconductor Limited | Shallow source MOSFET |
DE102004057235B4 (en) | 2004-11-26 | 2007-12-27 | Infineon Technologies Ag | Vertical trench transistor and method for its production |
US7285822B2 (en) | 2005-02-11 | 2007-10-23 | Alpha & Omega Semiconductor, Inc. | Power MOS device |
US7671439B2 (en) * | 2005-02-11 | 2010-03-02 | Alpha & Omega Semiconductor, Ltd. | Junction barrier Schottky (JBS) with floating islands |
US8362547B2 (en) * | 2005-02-11 | 2013-01-29 | Alpha & Omega Semiconductor Limited | MOS device with Schottky barrier controlling layer |
US7453119B2 (en) * | 2005-02-11 | 2008-11-18 | Alphs & Omega Semiconductor, Ltd. | Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact |
US7436022B2 (en) * | 2005-02-11 | 2008-10-14 | Alpha & Omega Semiconductors, Ltd. | Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout |
JP2006332607A (en) * | 2005-04-28 | 2006-12-07 | Nec Electronics Corp | Semiconductor device |
US20060273385A1 (en) * | 2005-06-06 | 2006-12-07 | M-Mos Semiconductor Sdn. Bhd. | Trenched MOSFET device with contact trenches filled with tungsten plugs |
US7446374B2 (en) * | 2006-03-24 | 2008-11-04 | Fairchild Semiconductor Corporation | High density trench FET with integrated Schottky diode and method of manufacture |
US7679146B2 (en) * | 2006-05-30 | 2010-03-16 | Semiconductor Components Industries, Llc | Semiconductor device having sub-surface trench charge compensation regions |
JP2008108962A (en) * | 2006-10-26 | 2008-05-08 | Toshiba Corp | Semiconductor device |
US20080246082A1 (en) * | 2007-04-04 | 2008-10-09 | Force-Mos Technology Corporation | Trenched mosfets with embedded schottky in the same cell |
US20090039456A1 (en) * | 2007-08-08 | 2009-02-12 | Alpha & Omega Semiconductor, Ltd | Structures and methods for forming Schottky diodes on a P-substrate or a bottom anode Schottky diode |
US8969950B2 (en) * | 2008-12-23 | 2015-03-03 | Alpha & Omega Semiconductor, Inc. | Integrated MOSFET-Schottky diode device with reduced source and body Kelvin contact impedance and breakdown voltage |
US8723317B2 (en) * | 2012-09-14 | 2014-05-13 | Force Mos Technology Co., Ltd. | Trench metal oxide semiconductor field effect transistor with embedded schottky rectifier using reduced masks process |
-
2007
- 2007-12-21 US US12/005,166 patent/US8362547B2/en active Active
-
2012
- 2012-12-21 US US13/725,789 patent/US8809143B2/en active Active
-
2014
- 2014-06-10 US US14/300,529 patent/US9236450B2/en active Active
-
2015
- 2015-12-07 US US14/961,582 patent/US10074742B2/en active Active
-
2018
- 2018-07-31 US US16/051,016 patent/US10535764B2/en active Active
-
2019
- 2019-12-05 US US16/705,029 patent/US10978585B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US10535764B2 (en) | 2020-01-14 |
US20200119185A1 (en) | 2020-04-16 |
US20160087093A1 (en) | 2016-03-24 |
US20130203225A1 (en) | 2013-08-08 |
US10074742B2 (en) | 2018-09-11 |
US8362547B2 (en) | 2013-01-29 |
US9236450B2 (en) | 2016-01-12 |
US8809143B2 (en) | 2014-08-19 |
US20090065814A1 (en) | 2009-03-12 |
US20140357030A1 (en) | 2014-12-04 |
US10978585B2 (en) | 2021-04-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10978585B2 (en) | MOS device with island region | |
US8728890B2 (en) | Fabrication of MOS device with integrated Schottky diode in active region contact trench | |
US8928079B2 (en) | MOS device with low injection diode | |
US8597998B2 (en) | Power MOS device fabrication | |
US8637368B2 (en) | Fabrication of MOS device with varying trench depth | |
TWI411108B (en) | Mos device with low injection diode |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |