CN102231386A - TMBS (Trench MOSFET Barrier Schottky) device and manufacturing method thereof - Google Patents
TMBS (Trench MOSFET Barrier Schottky) device and manufacturing method thereof Download PDFInfo
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- CN102231386A CN102231386A CN2011101764894A CN201110176489A CN102231386A CN 102231386 A CN102231386 A CN 102231386A CN 2011101764894 A CN2011101764894 A CN 2011101764894A CN 201110176489 A CN201110176489 A CN 201110176489A CN 102231386 A CN102231386 A CN 102231386A
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Abstract
The invention relates to a TMBS (Trench MOSFET Barrier Schottky) device comprising a first conduction-type semiconductor region, a plurality of trenches, grids, two second conduction-type body regions, two first conduction-type source regions, a groove and ohmic contact regions. The plurality of trenches are arranged in the semiconductor region, and the grid of each FET (Field Effect Transistor) is arranged in each trench; the two second conduction-type body regions are arranged between two adjacent trenches, and the first conduction-type semiconductor regions are arranged between the two body regions; each source region is arranged above the body regions; the groove is arranged between the two source regions and extends to the semiconductor region between the two body regions, a metal layer is filled in the groove, semiconductor regions between the metal layer and the body regions form a Schottky structure; and the ohmic contact regions are arranged at two sides of the groove and formed at junctions of the body regions and the source regions. The TMBS device disclosed by the invention is a high-density Schottky device; and a manufacturing method disclosed by the invention has the advantages of simple manufacturing process and low cost.
Description
Technical field
The present invention relates to a kind of highdensity schottky device, relate in particular to a kind of trench field effect transistor barrier schottky (Trench MOSFET Barrier Schottky, TMBS) device and preparation method thereof.
Background technology
In current power device manufacture craft, usually barrier schottky structure and trench field effect transistor are packaged together, improve the speed that meets of device, thereby improve the switching characteristic of power device.See also Fig. 1, Fig. 1 is a kind of cross-sectional view of trench field effect transistor barrier schottky device of prior art.Described trench field effect transistor barrier schottky device comprises trench field effect transistor 13 and the TMBS structure 14 that is formed on the substrate 11, and described TMBS structure 14 is arranged between two adjacent trench field effect transistors 13.The bottom of described substrate 11 is provided with the drain electrode (Drain) 12 of described field-effect transistor 13.
Described trench field effect transistor 13 comprises the groove 131 that extends to described substrate 11, be formed with the grid of described field-effect transistor 13 in the described groove 131, be formed with this tagma (Body) 132 between described groove 131 and the described TMBS structure 14, be formed at the source region 134 on described this tagma 132.Being provided with groove 135 in the described source region 134, is ohmic contact regions 133 near the bottom of described groove 135, and described ohmic contact regions 133 is used for this tagma 132 is drawn.Usually, described this tagma 132 is P-N-type semiconductor N district, and described ohmic contact regions 133 is described to be P+ N-type semiconductor N district, and described source region 134 is N+ N-type semiconductor N district.
Described TMBS structure 14 comprises a plurality of TMBS grooves 141, and the substrate 11 between adjacent two TMBS grooves 141 forms TMBS table top (Mesa) structure 142, and the top of described TMBS mesa structure 142 is provided with Schottky contacts (TMBS Contact) 143.Described trench field effect transistor barrier schottky device also comprises and is used to realize interconnected metal wire and passivation layer (Passivation).
Trench field effect transistor barrier schottky device shown in Figure 1 needs following 8 road mask (Mask) technologies: the first road masking process, the groove 131 of formation field-effect transistor 13; The second road masking process forms TMBS groove 141; The 3rd road masking process forms this tagma 132; The 4th road masking process forms source region 134; The 5th road masking process forms ohmic contact regions; The 6th road masking process forms Schottky contacts 143; The 7th road masking process forms interconnected metal wire; The 8th road masking process forms passivation layer.Yet the trench field effect transistor barrier schottky preparation of devices method of prior art needs 8 road masks, complex manufacturing technology; And be provided with independent TMBS structure 14 zones, the wafer area that takies is big, the cost height.
Summary of the invention
The object of the present invention is to provide a kind of high-density, trench formula field-effect transistor barrier schottky device.
Another object of the present invention is to provide above-mentioned trench field effect transistor barrier schottky preparation of devices method.
A kind of trench field effect transistor barrier schottky device comprises: the semiconductor region of first conduction type; Be formed at a plurality of grooves of described semiconductor region, the grid of described field-effect transistor is set in the described groove; Being formed at two these tagmas of second conduction type between adjacent two grooves, is the semiconductor region of described first conduction type between described two these tagmas; Two source regions of first conduction type, each described source region is formed at the top in described this tagma; Groove, described groove shaped are formed between described two source regions, and extend to the described semiconductor region between described two these tagmas, fill metal level in the described groove, and the described semiconductor region between described metal level and described two these tagmas forms Schottky junction structure; The ohmic contact regions of second conduction type, described ohmic contact regions is formed at the both sides of described groove, and is formed at the intersection in described this tagma and described source region.
The preferred a kind of technical scheme of above-mentioned trench field effect transistor barrier schottky device, described semiconductor region is the N type semiconductor district; Described this tagma is P-N-type semiconductor N district; Described source region is N+ N-type semiconductor N district; Described ohmic contact regions is P+ N-type semiconductor N district.
A kind of trench field effect transistor barrier schottky preparation of devices method comprises the steps: to form a plurality of grooves at the semiconductor region of first conduction type; Form photoresist layer between adjacent two grooves, described semiconductor region is carried out body inject, form two these tagmas of second conduction type between adjacent two grooves; Above described this tagma, form the source region of two first conduction types; Form groove between two source regions, described groove extends to the described semiconductor region between described two these tagmas; Utilize described groove, the rotation ion implantation angle, the intersection in the both sides of described groove, described this tagma and described source region forms ohmic contact regions; Form metal level in described groove, the described semiconductor region between described metal level and described two these tagmas forms Schottky junction structure.
The preferred a kind of technical scheme of said method, described semiconductor region is the N type semiconductor district; Described this tagma is P-N-type semiconductor N district; Described source region is N+ N-type semiconductor N district; Described ohmic contact regions is P+ N-type semiconductor N district.
Compared with prior art, trench field effect transistor barrier schottky device of the present invention is arranged at Schottky the active region of trench field effect transistor, thereby the additional areas of having avoided TMBS structure of the prior art to take, thereby reduce the wafer area that device takies, realize highdensity schottky device.Trench field effect transistor barrier schottky preparation of devices method of the present invention, by changing this tagma mask pattern, and between two grooves, photoresist layer is set, the rotation ion implantation angle, Schottky is arranged at the active region of trench field effect transistor, can save twice mask mask step, preparation method's technology is simple, cost is low.
Description of drawings
Fig. 1 is a kind of cross-sectional view of trench field effect transistor barrier schottky device of prior art.
Fig. 2 is the cross-sectional view of trench field effect transistor barrier schottky device of the present invention.
Fig. 3 is the flow chart of trench field effect transistor barrier schottky preparation of devices method of the present invention.
Fig. 4 is the schematic diagram that preparation method of the present invention forms the step in this tagma to Fig. 5.
Fig. 6 is the schematic diagram that preparation method of the present invention forms the step of Schottky contact region.
Embodiment
Trench field effect transistor barrier schottky device of the present invention is arranged at Schottky the active region (active area) of trench field effect transistor, thereby reduced the area that device takies wafer, and preparation method of the present invention can omit the twice mask step, and preparation technology is simple, cost is low.For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
See also Fig. 2, Fig. 2 is the cross-sectional view of trench field effect transistor barrier schottky device of the present invention.Described trench field effect transistor barrier schottky device comprises the semiconductor region 31 of first conduction type, and described semiconductor region 31 is formed on the substrate.Preferably, described semiconductor region 31 is N type semiconductor district 31.Be formed with a plurality of grooves 331 on the described semiconductor region 31, the grid of described field-effect transistor is set in the described groove 331, between described grid and the described groove gate oxide is set.
Be formed with two these tagmas 332 of second conduction type between adjacent two grooves 331, between described two these tagmas 332 is the semiconductor region 31 of described first conduction type, promptly before forming described this tagma 332, between adjacent two grooves 331, form photoresistance (Photo Resistor, PR) layer, can do not injected by described photoresist layer semiconductor region covered 31 by ion, thereby between adjacent two grooves 331, form two these tagmas 332, preferably, described this tagma 332 is P-N-type semiconductor N district.
The top in each described this tagma 332 forms the source region 334 of first conduction type, and preferred, described source region 334 is N+ N-type semiconductor N district.Be formed with groove 338 between described two source regions 334, described groove 338 extends to the described semiconductor region 31 between described two these tagmas 332.The intersection in the both sides of described groove 338, described this tagma 332 and described source region 334 is formed with ohmic contact regions 337, preferably, described ohmic contact regions 337 is the semiconductor region of P+ type, utilizes described groove 338, the rotation ion implantation angle can form described ohmic contact regions 337.Fill metal level in the described groove 338, the described semiconductor region 31 between described metal level and described two these tagmas 332 forms Schottky junction structure.
See also Fig. 3, Fig. 3 is the flow chart of trench field effect transistor barrier schottky preparation of devices method of the present invention.Trench field effect transistor barrier schottky preparation of devices method of the present invention comprises the steps:
The surface of the semiconductor region 31 between adjacent two grooves 331 forms photoresist layer 339, and as shown in Figure 4, described photoresist layer 339 can form synchronously with other photoresist layers in described these tagma 332 injection process.With described photoresist layer 339 is mask, described semiconductor region 31 is carried out ion inject, and forms described this tagma 332.Because the existence of described photoresist layer 339 can not injected by ion by described photoresist layer 339 semiconductor region covered 31, therefore between adjacent two grooves 331, form two these tagmas 332, as shown in Figure 5.Preferably, described this tagma 332 is P-N-type semiconductor N district.
Form the source region 334 of two first conduction types above described this tagma 332, preferred, described source region 334 is N+ N-type semiconductor N district.
Utilize described groove 338, the rotation ion implantation angle carries out the ion injection to described this tagma 332 and source region 334, thereby forms ohmic contact regions at the intersection in the both sides of described groove 338, described this tagma 332 and described source region 334, as shown in Figure 6.
Form metal level in described groove 338, the described semiconductor region 31 between described metal level and described two these tagmas 332 forms Schottky junction structure.Described metal level can form synchronously with the source electrode contact electrode of field-effect transistor.
Trench field effect transistor barrier schottky preparation of devices method of the present invention also comprises the step that forms passivation layer, and these steps are same as the prior art, do not repeat them here.
Compare with the method for prior art, trench field effect transistor barrier schottky device of the present invention is arranged at Schottky the active region of trench field effect transistor, thereby the additional areas of having avoided TMBS structure of the prior art to take, and then reduce the wafer area that device takies, realize highdensity schottky device.Trench field effect transistor barrier schottky preparation of devices method of the present invention, by changing this tagma mask pattern, between two grooves, photoresist layer is set, the rotation ion implantation angle, Schottky is arranged at the active region of trench field effect transistor, can save twice mask mask step (mask step of the metal level of schottky trench mask step and Schottky junction structure), preparation method's technology of the present invention is simple, cost is low.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the present invention is not limited at the specific embodiment described in the specification.
Claims (10)
1. a trench field effect transistor barrier schottky device is characterized in that, comprising:
The semiconductor region of first conduction type;
Be formed at a plurality of grooves of described semiconductor region, the grid of described field-effect transistor is set in the described groove;
Being formed at two these tagmas of second conduction type between adjacent two grooves, is the semiconductor region of described first conduction type between described two these tagmas;
Two source regions of first conduction type, each described source region is formed at the top in described this tagma;
Groove, described groove shaped are formed between described two source regions, and extend to the described semiconductor region between described two these tagmas, fill metal level in the described groove, and the described semiconductor region between described metal level and described two these tagmas forms Schottky junction structure;
The ohmic contact regions of second conduction type, the basic contact zone of described ohm is formed at the both sides of described groove, and is formed at the intersection in described this tagma and described source region.
2. trench field effect transistor barrier schottky device as claimed in claim 1 is characterized in that described semiconductor region is the N type semiconductor district.
3. trench field effect transistor barrier schottky device as claimed in claim 1 is characterized in that, described this tagma is P-N-type semiconductor N district.
4. trench field effect transistor barrier schottky device as claimed in claim 1 is characterized in that, described source region is N+ N-type semiconductor N district.
5. trench field effect transistor barrier schottky device as claimed in claim 1 is characterized in that, described ohmic contact regions is P+ N-type semiconductor N district.
6. a trench field effect transistor barrier schottky preparation of devices method is characterized in that, comprises the steps:
Semiconductor region at first conduction type forms a plurality of grooves;
Form photoresist layer between adjacent two grooves, described semiconductor region is carried out body inject, form two these tagmas of second conduction type between adjacent two grooves;
Above described this tagma, form the source region of two first conduction types;
Form groove between two source regions, described groove extends to the described semiconductor region between described two these tagmas;
Utilize described groove, the rotation ion implantation angle, the intersection in the both sides of described groove, described this tagma and described source region forms ohmic contact regions;
Form metal level in described groove, the described semiconductor region between described metal level and described two these tagmas forms Schottky junction structure.
7. trench field effect transistor barrier schottky preparation of devices method as claimed in claim 6 is characterized in that described semiconductor region is the N type semiconductor district.
8. trench field effect transistor barrier schottky preparation of devices method as claimed in claim 6 is characterized in that described this tagma is P-N-type semiconductor N district.
9. trench field effect transistor barrier schottky preparation of devices method as claimed in claim 6 is characterized in that described source region is N+ N-type semiconductor N district.
10. trench field effect transistor barrier schottky preparation of devices method as claimed in claim 6 is characterized in that described ohmic contact regions is P+ N-type semiconductor N district.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN2011101764894A CN102231386A (en) | 2011-06-28 | 2011-06-28 | TMBS (Trench MOSFET Barrier Schottky) device and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011101764894A CN102231386A (en) | 2011-06-28 | 2011-06-28 | TMBS (Trench MOSFET Barrier Schottky) device and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425569A (en) * | 2013-09-11 | 2015-03-18 | 英飞凌科技股份有限公司 | Semiconductor device, junction field effect transistor and vertical field effect transistor |
| CN107134478A (en) * | 2017-03-22 | 2017-09-05 | 深圳深爱半导体股份有限公司 | Power semiconductor and its manufacture method |
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|---|---|---|---|---|
| US20090065814A1 (en) * | 2005-02-11 | 2009-03-12 | Alpha & Omega Semiconductor Limited | MOS device with schottky barrier controlling layer |
| CN101853852A (en) * | 2010-04-29 | 2010-10-06 | 苏州硅能半导体科技股份有限公司 | Groove MOS (Metal Oxide Semiconductor) device integrating Schottky diodes in unit cell and manufacture method |
| CN102104026A (en) * | 2009-12-18 | 2011-06-22 | 上海华虹Nec电子有限公司 | Method for manufacturing power metal oxide semiconductor (MOS) transistor device integrated with Schottky diodes |
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2011
- 2011-06-28 CN CN2011101764894A patent/CN102231386A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090065814A1 (en) * | 2005-02-11 | 2009-03-12 | Alpha & Omega Semiconductor Limited | MOS device with schottky barrier controlling layer |
| CN102104026A (en) * | 2009-12-18 | 2011-06-22 | 上海华虹Nec电子有限公司 | Method for manufacturing power metal oxide semiconductor (MOS) transistor device integrated with Schottky diodes |
| CN101853852A (en) * | 2010-04-29 | 2010-10-06 | 苏州硅能半导体科技股份有限公司 | Groove MOS (Metal Oxide Semiconductor) device integrating Schottky diodes in unit cell and manufacture method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425569A (en) * | 2013-09-11 | 2015-03-18 | 英飞凌科技股份有限公司 | Semiconductor device, junction field effect transistor and vertical field effect transistor |
| CN104425569B (en) * | 2013-09-11 | 2018-02-23 | 英飞凌科技股份有限公司 | Semiconductor devices, junction field effect transistor and vertical field-effect transistor |
| CN107134478A (en) * | 2017-03-22 | 2017-09-05 | 深圳深爱半导体股份有限公司 | Power semiconductor and its manufacture method |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140425 |
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Effective date of registration: 20140425 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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Application publication date: 20111102 |