US20180310412A1 - Method of making a flexible printed circuit board - Google Patents
Method of making a flexible printed circuit board Download PDFInfo
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- US20180310412A1 US20180310412A1 US15/609,131 US201715609131A US2018310412A1 US 20180310412 A1 US20180310412 A1 US 20180310412A1 US 201715609131 A US201715609131 A US 201715609131A US 2018310412 A1 US2018310412 A1 US 2018310412A1
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- electroplating layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/032—Organic insulating material consisting of one material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/064—Photoresists
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/188—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by direct electroplating
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0341—Intermediate metal, e.g. before reinforcing of conductors by plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/07—Electric details
- H05K2201/0753—Insulation
- H05K2201/0769—Anti metal-migration, e.g. avoiding tin whisker growth
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0588—Second resist used as pattern over first resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/072—Electroless plating, e.g. finish plating or initial plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0723—Electroplating, e.g. finish plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Definitions
- the subject matter herein generally relates to circuit boards, and particularly, to a flexible printed circuit board (FPCB) and a method for making the FPCB.
- FPCB flexible printed circuit board
- the FPCB usually comprises a copper wiring layer.
- a surface of the copper wiring layer is usually treated by chemical plating of nickel and gold to form a nickel chemical-plating layer and a gold chemical-plating layer, thereby increase corrosion resistance of the FPCB.
- the line space may further decrease due to existence of the nickel chemical-plating layer, which may increase the risk of ion migration from the copper wiring layer.
- FIG. 1 is a flowchart of an exemplary embodiment of a method for making an FPCB.
- FIG. 2 is a diagram of a carrier used in the method of FIG. 1 .
- FIG. 3 is a diagram showing a first photoresist layer being formed on the carrier of FIG. 2 .
- FIG. 4 is a diagram of a copper electroplating layer formed by electroplating of copper in the first photoresist layer of FIG. 3 .
- FIG. 5 is a diagram showing a second photoresist layer being formed on the first photoresist layer and the copper electroplating layer of FIG. 4 .
- FIG. 6 is a diagram of a nickel electroplating layer formed by electroplating nickel in the second photoresist layer of FIG. 5 .
- FIG. 7 is a diagram showing the first and the second photoresist layers of FIG. 6 removed.
- FIG. 8 is a diagram showing a non-wiring area of the carrier of FIG. 7 etched and removed.
- FIG. 9 is a diagram showing a cover film being formed on the copper electroplating layer of FIG. 8 .
- FIG. 10 is a diagram of an exemplary embodiment of an FPCB formed by chemical plating gold on the nickel electroplating layer of FIG. 9 .
- FIG. 11 is a diagram of another exemplary embodiment of an FPCB formed by chemical plating nickel and gold on the nickel electroplating layer of FIG. 9 .
- FIG. 12 is a flowchart of another exemplary embodiment of the method for making an FPCB.
- FIG. 13 is a diagram showing a second photoresist layer formed on the first photoresist layer and the copper electroplating layer in the method of FIG. 12 .
- FIG. 14 is a diagram of a nickel electroplating layer formed by electroplating nickel in the second photoresist layer of FIG. 13 .
- FIG. 15 is a diagram showing the first and the second photoresist layers of FIG. 14 removed, non-wiring area of the carrier etched, a cover film covering the copper electroplating layer, and a gold chemical-plating layer formed on the nickel electroplating layer, to form yet another exemplary embodiment of an FPCB.
- a method for making an FPCB 100 (shown in FIG. 10 ) is presented in accordance with a first exemplary embodiment.
- the method for making the FPCB 100 is provided by way of example, as there are a variety of ways to carry out the method.
- the exemplary method can begin at step 101 .
- a carrier 10 which comprises an insulating layer 11 and a copper foil 12 formed on at least one surface of the insulating layer 11 ( FIG. 1 shows only one copper foil 12 ).
- the copper foil 12 comprises a wiring area 121 and a non-wiring area 122 besides the wiring area 121 .
- the insulating layer 11 is made of a polymer selected from a group consisting of polyimide, polytetrafluoroethylene, poly thiamine, poly (methyl methacrylate), polycarbonate, polyethylene terephthalate, and polyimide-polyethyleneterephthalate, and any combination thereof. In at least one exemplary embodiment, the insulating layer 11 has a thickness of about 10 ⁇ m.
- a first photoresist layer 20 is formed on the copper foil 12 .
- the first photoresist layer 20 has a first hollow pattern 21 to expose the wiring area 121 of the copper foil 12 .
- the first photoresist layer 20 is treated by an exposure and development process to form the first hollow pattern 21 .
- the first photoresist layer 20 can be a dry film.
- the first hollow pattern 21 is electroplated with copper, thereby forming a copper electroplating layer 30 on the wiring area 121 .
- the copper electroplating layer 30 comprises a first portion 31 that awaits nickel electroplating and a second portion 32 besides the first portion 31 .
- the copper electroplating layer 30 has a thickness of about 25 ⁇ m.
- a second photoresist layer 40 is formed on and covered on the first photoresist layer 20 and the copper electroplating layer 30 .
- the second photoresist layer 40 has a second hollow pattern 41 to expose at least the first portion 31 of the copper electroplating layer 30 .
- the second photoresist layer 40 covers only the first portion 31 .
- the second photoresist layer 40 is treated by an exposure and development process to form the second hollow pattern 41 .
- the second photoresist layer 40 can also be a dry film.
- the second hollow pattern 41 is electroplated with nickel, thereby forming a nickel electroplating layer 50 a at least on the first portion 31 .
- the nickel electroplating layer 50 a has a thickness of about 2 ⁇ m to about 6 ⁇ m.
- the first photoresist layer 20 and the second photoresist layer 40 are removed.
- the non-wiring area 122 of the copper foil 12 is etched and removed so that the wiring area 121 forms a desired circuit wiring.
- a cover film 60 is covered on the second portion 32 of the copper electroplating layer 30 , thereby causing the cover film 60 to fill in gaps of the copper electroplating layer 30 and the cover film 60 to be spaced from sidewalls of the first portion 31 .
- the cover film 60 is a solder mask layer.
- a top surface of the nickel electroplating layer 50 a facing away from the first portion 31 and the sidewalls of the first portion 31 are chemical plated with gold to form a gold chemical-plating layer 70 , thereby forming the FPCB 100 .
- FIG. 11 illustrates in another exemplary embodiment, before forming the gold chemical-plating layer 70 , the top surface of the nickel electroplating layer 50 a facing away from the first portion 31 and the sidewalls of the first portion 31 are chemical plated with nickel to form a nickel chemical-plating layer 50 b. Then, the gold chemical-plating layer 70 is formed on a top surface of the nickel chemical-plating layer 50 b facing away from the first portion 31 and sidewalls of the nickel chemical-plating layer 50 b.
- the sum of thicknesses of the nickel electroplating layer 50 a and the top surface of the nickel chemical-plating layer 50 b is about 2 ⁇ m to about 6 ⁇ m.
- the sidewall of the nickel chemical-plating layer 50 b has a thickness of about 0.2 ⁇ m to about 2 ⁇ m.
- a second exemplary method for making an FPCB 100 ′ is further provided. Differences from the above first exemplary embodiment are:
- a second photoresist layer 40 is applied on the first photoresist layer 20 and the copper electroplating layer 30 .
- the second photoresist layer exposes both the first portion 31 and the second portion 32 of the copper electroplating layer 30 .
- the second hollow pattern 41 is electroplated with nickel, thereby forming a nickel electroplating layer 50 a both on the first portion 31 and the second portion 32 .
- the cover film 60 covers the second portion 32 of the copper electroplating layer 30 and the nickel electroplating layer 50 a formed on the second portion 32 .
- FIGS. 10 and 11 illustrate that in the first exemplary embodiment, an FPCB 100 comprises an insulating layer 11 and a wiring area 121 formed on at least one surface of the insulating layer 11 .
- a copper electroplating layer 30 is formed on and corresponds to the wiring area 121 .
- the copper electroplating layer 30 comprises a first portion 31 and a second portion 32 besides the first portion 31 .
- a nickel electroplating layer 50 a is formed on a top surface of at least the first portion 31 facing away from the wiring area 121 .
- the nickel electroplating layer 50 a exposes sidewalls of the first portion 31 .
- a cover film 60 is formed on the second portion 32 and fills in gaps of the copper electroplating layer 30 .
- the nickel electroplating layer 50 a is only formed on the top of the first portion 31 .
- a gold chemical-plating layer 70 is formed on a top surface of the nickel electroplating layer 50 a facing away from the first portion 31 and the sidewalls of the first portion 31 .
- a nickel chemical-plating layer 50 b is formed on a top surface of the nickel electroplating layer 50 a facing away from the first portion 31 and the sidewalls of the first portion 31 .
- the gold chemical-plating layer 70 is formed on a top surface of the nickel chemical-plating layer 50 b facing away from the first portion 31 and sidewalls of the nickel chemical-plating layer 50 b.
- FIG. 15 illustrates a second exemplary embodiment of an FPCB 100 ′. Differences from the first exemplary embodiment are that the nickel electroplating layer 50 a is formed on a top surface of both the first portion 31 and the second portion 32 facing away from the wiring area 121 . The nickel electroplating layer 50 a exposes sidewalls of the first portion 31 and the second portion 32 .
- the nickel electroplating layer 50 a is not formed on the sidewalls of the first portion 31 , thereby preventing the line space of the copper electroplating layer 30 from being reduced by the nickel electroplating layer 50 a.
- a risk of ion migration from the copper electroplating layer 30 is reduced.
- the nickel chemical-plating layer 50 b is formed on the top surface of the nickel electroplating layer 50 a facing away from the first portion 31 and the sidewalls of the first portion 31 , a very small thickness of the nickel chemical-plating layer 50 b can prevent ion migration from the copper electroplating layer 30 , thereby preventing the line space of the copper electroplating layer 30 from being greatly reduced.
- the nickel electroplating layer 50 a can function as a catalytic agent in the process of chemical-electroplating of nickel.
- the copper electroplating layer 30 does not need to be activated by palladium substitution. That is, palladium residue within the nickel electroplating layer 50 a is avoided, which further reduces the risk of ion migration.
Abstract
Description
- The subject matter herein generally relates to circuit boards, and particularly, to a flexible printed circuit board (FPCB) and a method for making the FPCB.
- FPCBs are widely used in various kinds of electronic devices. The FPCB usually comprises a copper wiring layer. A surface of the copper wiring layer is usually treated by chemical plating of nickel and gold to form a nickel chemical-plating layer and a gold chemical-plating layer, thereby increase corrosion resistance of the FPCB.
- However, when the copper wiring layer has a minimal line space, the line space may further decrease due to existence of the nickel chemical-plating layer, which may increase the risk of ion migration from the copper wiring layer.
- Implementations of the present technology will now be described, by way of example only, with reference to the attached figures.
-
FIG. 1 is a flowchart of an exemplary embodiment of a method for making an FPCB. -
FIG. 2 is a diagram of a carrier used in the method ofFIG. 1 . -
FIG. 3 is a diagram showing a first photoresist layer being formed on the carrier ofFIG. 2 . -
FIG. 4 is a diagram of a copper electroplating layer formed by electroplating of copper in the first photoresist layer ofFIG. 3 . -
FIG. 5 is a diagram showing a second photoresist layer being formed on the first photoresist layer and the copper electroplating layer ofFIG. 4 . -
FIG. 6 is a diagram of a nickel electroplating layer formed by electroplating nickel in the second photoresist layer ofFIG. 5 . -
FIG. 7 is a diagram showing the first and the second photoresist layers ofFIG. 6 removed. -
FIG. 8 is a diagram showing a non-wiring area of the carrier ofFIG. 7 etched and removed. -
FIG. 9 is a diagram showing a cover film being formed on the copper electroplating layer ofFIG. 8 . -
FIG. 10 is a diagram of an exemplary embodiment of an FPCB formed by chemical plating gold on the nickel electroplating layer ofFIG. 9 . -
FIG. 11 is a diagram of another exemplary embodiment of an FPCB formed by chemical plating nickel and gold on the nickel electroplating layer ofFIG. 9 . -
FIG. 12 is a flowchart of another exemplary embodiment of the method for making an FPCB. -
FIG. 13 is a diagram showing a second photoresist layer formed on the first photoresist layer and the copper electroplating layer in the method ofFIG. 12 . -
FIG. 14 is a diagram of a nickel electroplating layer formed by electroplating nickel in the second photoresist layer ofFIG. 13 . -
FIG. 15 is a diagram showing the first and the second photoresist layers ofFIG. 14 removed, non-wiring area of the carrier etched, a cover film covering the copper electroplating layer, and a gold chemical-plating layer formed on the nickel electroplating layer, to form yet another exemplary embodiment of an FPCB. - It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features of the present disclosure.
- The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.
- The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series, and the like.
- Referring to
FIGS. 1-10 , a method for making an FPCB 100 (shown inFIG. 10 ) is presented in accordance with a first exemplary embodiment. The method for making the FPCB 100 is provided by way of example, as there are a variety of ways to carry out the method. The exemplary method can begin atstep 101. - At
step 101, referring toFIG. 2 , acarrier 10 is provided, which comprises aninsulating layer 11 and acopper foil 12 formed on at least one surface of the insulating layer 11 (FIG. 1 shows only one copper foil 12). Thecopper foil 12 comprises awiring area 121 and anon-wiring area 122 besides thewiring area 121. - In at least one exemplary embodiment, the
insulating layer 11 is made of a polymer selected from a group consisting of polyimide, polytetrafluoroethylene, poly thiamine, poly (methyl methacrylate), polycarbonate, polyethylene terephthalate, and polyimide-polyethyleneterephthalate, and any combination thereof. In at least one exemplary embodiment, theinsulating layer 11 has a thickness of about 10 μm. - At
step 102, referring toFIG. 3 , a firstphotoresist layer 20 is formed on thecopper foil 12. The firstphotoresist layer 20 has a firsthollow pattern 21 to expose thewiring area 121 of thecopper foil 12. - In at least one exemplary embodiment, the first
photoresist layer 20 is treated by an exposure and development process to form the firsthollow pattern 21. The firstphotoresist layer 20 can be a dry film. - At
step 103, referring toFIG. 4 , the firsthollow pattern 21 is electroplated with copper, thereby forming a copper electroplatinglayer 30 on thewiring area 121. The copperelectroplating layer 30 comprises afirst portion 31 that awaits nickel electroplating and asecond portion 32 besides thefirst portion 31. - In at least one exemplary embodiment, the copper
electroplating layer 30 has a thickness of about 25 μm. - At
step 104, referring toFIG. 5 , a secondphotoresist layer 40 is formed on and covered on the firstphotoresist layer 20 and the copperelectroplating layer 30. The secondphotoresist layer 40 has a secondhollow pattern 41 to expose at least thefirst portion 31 of the copperelectroplating layer 30. - In at least one exemplary embodiment, the second
photoresist layer 40 covers only thefirst portion 31. - In at least one exemplary embodiment, the second
photoresist layer 40 is treated by an exposure and development process to form the secondhollow pattern 41. The secondphotoresist layer 40 can also be a dry film. - At
step 105, referring toFIG. 6 , the secondhollow pattern 41 is electroplated with nickel, thereby forming a nickel electroplatinglayer 50 a at least on thefirst portion 31. - In at least one exemplary embodiment, the nickel electroplating
layer 50 a has a thickness of about 2 μm to about 6 μm. - At
step 106, referring toFIG. 7 , the firstphotoresist layer 20 and the secondphotoresist layer 40 are removed. - At
step 107, referring toFIG. 8 , thenon-wiring area 122 of thecopper foil 12 is etched and removed so that thewiring area 121 forms a desired circuit wiring. - At
step 108, referring toFIG. 9 , acover film 60 is covered on thesecond portion 32 of the copperelectroplating layer 30, thereby causing thecover film 60 to fill in gaps of the copperelectroplating layer 30 and thecover film 60 to be spaced from sidewalls of thefirst portion 31. - In at least one exemplary embodiment, the
cover film 60 is a solder mask layer. - At
step 109, referring toFIG. 10 , a top surface of the nickel electroplatinglayer 50 a facing away from thefirst portion 31 and the sidewalls of thefirst portion 31 are chemical plated with gold to form a gold chemical-plating layer 70, thereby forming the FPCB 100. -
FIG. 11 illustrates in another exemplary embodiment, before forming the gold chemical-plating layer 70, the top surface of the nickel electroplatinglayer 50 a facing away from thefirst portion 31 and the sidewalls of thefirst portion 31 are chemical plated with nickel to form a nickel chemical-plating layer 50 b. Then, the gold chemical-plating layer 70 is formed on a top surface of the nickel chemical-plating layer 50 b facing away from thefirst portion 31 and sidewalls of the nickel chemical-plating layer 50 b. In this exemplary embodiment, the sum of thicknesses of the nickel electroplatinglayer 50 a and the top surface of the nickel chemical-plating layer 50 b is about 2 μm to about 6 μm. The sidewall of the nickel chemical-plating layer 50 b has a thickness of about 0.2 μm to about 2 μm. - Referring to
FIG. 12 , a second exemplary method for making an FPCB 100′ is further provided. Differences from the above first exemplary embodiment are: - At
step 104′, referring toFIG. 13 , asecond photoresist layer 40 is applied on thefirst photoresist layer 20 and thecopper electroplating layer 30. The second photoresist layer exposes both thefirst portion 31 and thesecond portion 32 of thecopper electroplating layer 30. - At
step 105′, referring toFIG. 14 , the secondhollow pattern 41 is electroplated with nickel, thereby forming anickel electroplating layer 50 a both on thefirst portion 31 and thesecond portion 32. - Thus, at
step 108′, referring toFIG. 15 , thecover film 60 covers thesecond portion 32 of thecopper electroplating layer 30 and thenickel electroplating layer 50 a formed on thesecond portion 32. - Depending on the exemplary embodiment, certain of the steps of methods described may be removed, others may be added, and the sequence of steps may be altered. It is also to be understood that the description and the claims drawn to a method may include some indication in reference to certain steps. However, the indication used is only to be viewed for identification purposes and not as a suggestion as to an order for the steps.
-
FIGS. 10 and 11 illustrate that in the first exemplary embodiment, anFPCB 100 comprises an insulatinglayer 11 and awiring area 121 formed on at least one surface of the insulatinglayer 11. Acopper electroplating layer 30 is formed on and corresponds to thewiring area 121. Thecopper electroplating layer 30 comprises afirst portion 31 and asecond portion 32 besides thefirst portion 31. Anickel electroplating layer 50 a is formed on a top surface of at least thefirst portion 31 facing away from thewiring area 121. Thenickel electroplating layer 50 a exposes sidewalls of thefirst portion 31. Acover film 60 is formed on thesecond portion 32 and fills in gaps of thecopper electroplating layer 30. - In at least one exemplary embodiment, the
nickel electroplating layer 50 a is only formed on the top of thefirst portion 31. - Referring to
FIG. 10 , in at least one exemplary embodiment, a gold chemical-plating layer 70 is formed on a top surface of thenickel electroplating layer 50 a facing away from thefirst portion 31 and the sidewalls of thefirst portion 31. - Referring to
FIG. 11 , in at least one exemplary embodiment, a nickel chemical-plating layer 50 b is formed on a top surface of thenickel electroplating layer 50 a facing away from thefirst portion 31 and the sidewalls of thefirst portion 31. The gold chemical-plating layer 70 is formed on a top surface of the nickel chemical-plating layer 50 b facing away from thefirst portion 31 and sidewalls of the nickel chemical-plating layer 50 b. -
FIG. 15 illustrates a second exemplary embodiment of anFPCB 100′. Differences from the first exemplary embodiment are that thenickel electroplating layer 50 a is formed on a top surface of both thefirst portion 31 and thesecond portion 32 facing away from thewiring area 121. Thenickel electroplating layer 50 a exposes sidewalls of thefirst portion 31 and thesecond portion 32. - With the above configuration, the
nickel electroplating layer 50 a is not formed on the sidewalls of thefirst portion 31, thereby preventing the line space of thecopper electroplating layer 30 from being reduced by thenickel electroplating layer 50 a. Thus, a risk of ion migration from thecopper electroplating layer 30 is reduced. Even when the nickel chemical-plating layer 50 b is formed on the top surface of thenickel electroplating layer 50 a facing away from thefirst portion 31 and the sidewalls of thefirst portion 31, a very small thickness of the nickel chemical-plating layer 50 b can prevent ion migration from thecopper electroplating layer 30, thereby preventing the line space of thecopper electroplating layer 30 from being greatly reduced. - Moreover, the
nickel electroplating layer 50 a can function as a catalytic agent in the process of chemical-electroplating of nickel. Thus, during the process of chemical-electroplating of nickel and gold, thecopper electroplating layer 30 does not need to be activated by palladium substitution. That is, palladium residue within thenickel electroplating layer 50 a is avoided, which further reduces the risk of ion migration. - Even though information and advantages of the present embodiments have been set forth in the foregoing description, together with details of the structures and functions of the present embodiments, the disclosure is illustrative only. Changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the present embodiments to the full extent indicated by the plain meaning of the terms in which the appended claims are expressed.
Claims (12)
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US11044806B2 (en) * | 2017-08-18 | 2021-06-22 | Kinsus Interconnect Technology Corp. | Method for manufacturing multi-layer circuit board capable of being applied with electrical testing |
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US4866008A (en) * | 1987-12-11 | 1989-09-12 | Texas Instruments Incorporated | Methods for forming self-aligned conductive pillars on interconnects |
JPH05315332A (en) * | 1992-04-02 | 1993-11-26 | Nec Corp | Semiconductor device and manufacture thereof |
US6534192B1 (en) * | 1999-09-24 | 2003-03-18 | Lucent Technologies Inc. | Multi-purpose finish for printed wiring boards and method of manufacture of such boards |
US6398935B1 (en) * | 2000-03-27 | 2002-06-04 | Emc Corporation | Method for manufacturing pcb's |
KR100396787B1 (en) * | 2001-11-13 | 2003-09-02 | 엘지전자 주식회사 | Wire bonding pad structure of semiconductor package pcb |
JP4705448B2 (en) * | 2005-09-29 | 2011-06-22 | 日本シイエムケイ株式会社 | Method for manufacturing printed wiring board |
JP4974119B2 (en) * | 2008-03-03 | 2012-07-11 | 株式会社伸光製作所 | Circuit board manufacturing method |
JP5428667B2 (en) * | 2009-09-07 | 2014-02-26 | 日立化成株式会社 | Manufacturing method of semiconductor chip mounting substrate |
CN102045951B (en) * | 2010-11-29 | 2012-10-17 | 上海申和热磁电子有限公司 | Metal surface plated nickel/gold treatment method of ceramic metalized substrate and manufactured ceramic metalized substrate |
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US11044806B2 (en) * | 2017-08-18 | 2021-06-22 | Kinsus Interconnect Technology Corp. | Method for manufacturing multi-layer circuit board capable of being applied with electrical testing |
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