US20170250337A1 - Non-volatile memory device including ferroelectrics and method of manufacturing the same - Google Patents

Non-volatile memory device including ferroelectrics and method of manufacturing the same Download PDF

Info

Publication number
US20170250337A1
US20170250337A1 US15/213,600 US201615213600A US2017250337A1 US 20170250337 A1 US20170250337 A1 US 20170250337A1 US 201615213600 A US201615213600 A US 201615213600A US 2017250337 A1 US2017250337 A1 US 2017250337A1
Authority
US
United States
Prior art keywords
semiconductor substrate
memory device
volatile memory
recess
ferroelectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US15/213,600
Other languages
English (en)
Inventor
Se Hun Kang
Deok Sin Kil
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
SK Hynix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SK Hynix Inc filed Critical SK Hynix Inc
Assigned to SK Hynix Inc. reassignment SK Hynix Inc. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KANG, SE HUN, KIL, DEOK SIN
Publication of US20170250337A1 publication Critical patent/US20170250337A1/en
Priority to US16/198,529 priority Critical patent/US10734392B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H01L43/08—
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • H01L27/115—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L43/02—
    • H01L43/12—
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/223—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using MOS with ferroelectric gate insulating film

Definitions

  • Various embodiments generally relate to a non-volatile memory device and a method of manufacturing the same, more particularly, to a non-volatile memory device including ferroelectrics and a method of manufacturing the, non-volatile memory device.
  • a semiconductor memory device may be classified into a volatile memory device and a non-volatile memory device
  • the volatile memory device may have rapid read and write speeds.
  • data in the volatile memory device may be erased.
  • the non-volatile memory device may store data regardless of a power supply.
  • the non-volatile memory device may be advantageous in storing data regardless of the power supply.
  • the non-volatile memory device may include a flash memory device used in portable electronic devices.
  • a non-volatile memory device having improved operational capacity to which a random access may be applied may also be widely developed.
  • this non-volatile memory device may include a ferroelectric RAM (FeRAM) using a ferroelectric capacitor, a magnetic RAM (MRAM) using a tunneling magneto-resistive (TMR) layer, a phase-changeable memory device using chalcogenide alloys, a resistive RAM (ReRAM) using a resistive layer as a data storage medium, etc.
  • FeRAM ferroelectric RAM
  • MRAM magnetic RAM
  • TMR tunneling magneto-resistive
  • ReRAM resistive RAM
  • the FeRAM may use a ferroelectric material as a storage medium.
  • the ferroelectric material may have a spontaneous polarization characteristic.
  • a spontaneous polarization direction of the ferroelectric material may be controlled by an electric field.
  • the ferroelectric material may be polarized in accordance with the spontaneous polarization characteristic so that the FeRAM may perform memory operations.
  • the ferroelectric memory device may use the ferroelectric layer as a gate insulating layer.
  • the semiconductor memory device may have been highly integrated, it may be difficult to screen surface charges on the ferroelectric layer due to a narrow line width of the gate.
  • the non-volatile memory device may include a semiconductor substrate, a ferroelectric layer, a source, a drain, a gate and a channel region.
  • the semiconductor substrate may have a recess.
  • the ferroelectric layer may be formed in the recess.
  • the source may be arranged at a first side of the recess.
  • the drain may be arranged at a second side of the recess. The second side is located opposite to the first side with respect to the recess.
  • the gate may be arranged over the ferroelectric layers.
  • the channel region may be formed in the semiconductor substrate along a contour recess and between the source and the drain.
  • a non-volatile memory device may include a semiconductor substrate, a storage member, a source, a drain and a gate.
  • the storage member may be formed in the semiconductor substrate.
  • the source and the drain may be formed in the semiconductor substrate at both sides of the storage member.
  • the gate may be formed over the storage member.
  • the storage member has different polarization states depending on by an electric field level which applied to the gate to the storage member.
  • a method of manufacturing a non-volatile memory device In the method of manufacturing the non-volatile memory device, impurities may be implanted into a semiconductor substrate.
  • the semiconductor substrate may be etched to form a recess, thereby defining a source and a drain doped with the impurities.
  • a ferroelectric layer may be formed in the recess.
  • a gate may be formed on the ferroelectric layer.
  • a non-volatile memory device may include a source, a drain, a ferroelectric layer and a gate.
  • the source and drain is located at a first level.
  • the ferroelectric layer is extending from between the source and the drain to a second level.
  • the second level is lower than the first level.
  • the gate is provided over the ferroelectric layer and between the source and the drain.
  • FIGS. 1 to 4 a re cross-sectional views illustrating a method of manufacturing a non-volatile memory device in accordance with an embodiment
  • FIGS. 5 and 6 are cross-sectional views illustrating a non-volatile memory device in accordance with an embodiment
  • FIG. 7 is a schematic diagram illustrating a memory system according to an embodiment.
  • first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should, not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
  • spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example of the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented for example, rotated 90 degrees or at other orientations, and w the spatially relative descriptors used herein should be interpreted accordingly.
  • FIGS. 1 to 4 are cross-sectional views illustrating a method of manufacturing a non-volatile memory device in accordance with an embodiment.
  • a semiconductor substrate 100 may be prepared.
  • the semiconductor substrate 100 may include a semiconductor material such as Si, SiGe, etc.
  • Impurities may be implanted into the semiconductor substrate 100 to form Impurity regions such as a source and a drain.
  • the impurity regions may include N type impurities having a high concentration such as P (phosphorus), As (arsenic), etc.
  • the impurity regions may include P type impurities such as B (boron), etc.
  • the impurities in the source may be contrary to the impurities in the drain.
  • the semiconductor substrate 100 having the impurity regions may be etched to form a recess T.
  • the impurity regions may be divided into a source 110 a and a drain 110 b by the recess T.
  • a channel region between the source 110 a and the drain 110 b may have a length L 2 longer than a length L 1 of a channel region in a planar type non-volatile memory device.
  • the recess T may be formed by an anisotropic etching process, an isotropic etching process, etc.
  • the recess T may be formed by the isotropic etching process such as a wet etching process
  • the recess T may have a semi-spherical shape.
  • the recess T′ may have a squared trench shape with a vertical sidewall.
  • a ferroelectric layer 120 may be formed on the semiconductor substrate 100 to fill up the recess T.
  • the ferroelectric layer 120 may include a dielectric material capable of showing switchable polarizations upon application of an external electric field.
  • the polarized ferroelectric layer 120 may generate displacement of contrarily charged ions and dipole moments.
  • the ferroelectric layer 120 may include a hafnium oxide (Hf x O y ) layer where each of x and y is positive integer.
  • the ferroelectric layer 120 may include additional dielectric materials capable of being polarized by the electric field applied to an electrode, for example, a gate.
  • the ferroelectric layer 120 may maintain the polarization state after the electric field may be turned off.
  • the polarization of the ferroelectric layer 120 may be interpreted as states of a memory cell, for example 1 or 0.
  • the polarization of the ferroelectric layer 120 may be determined by measuring a specific resistance of a ferroelectric memory device such as a ferroelectric MOS transistor. The specific resistance may be dependent upon the polarization of the ferroelectric layer 120 . The polarization of the ferroelectric layer 120 may be sensed by measuring a voltage flowing through the ferroelectric MOS transistor when a low bias is applied. Furthermore, since the ferroelectric layer 120 may maintain its polarization state even when a power supply interrupts, the ferroelectric layer 120 may be used as a non-volatile storage medium such as a cell capacitor. The ferroelectric layer 120 may not require a refresh operation, unlike a DRAM.
  • the ferroelectric layer 120 may be planarized until an upper surface of the semiconductor substrate 100 may be exposed to form the planarized ferroelectric layer 120 in the recess T.
  • the ferroelectric layer 120 may be planarized by an etch stop process having an etching end point such as the upper surface of the semiconductor substrate 100 .
  • the channel region may have the length L 2 and is formed under the ferroelectric layer 120
  • a conductive layer may be formed on the semiconductor substrate 100 .
  • the conductive layer may be patterned to form a gate 130 on the ferroelectric layer 120 .
  • the gate 130 may include a metal layer.
  • the gate 130 may be electrically isolated from the source 110 a and the drain 110 b.
  • the ferroelectric memory device may include one ferroelectric MOS transistor.
  • the ferroelectric MOS transistor may perform operations of a transistor. Furthermore, the ferroelectric MOS transistor may store data ‘0’ or ‘1’ by changing its polarization state in accordance with the electric field applied to the ferroelectric layer 120 .
  • the ferroelectric layer 120 may be formed in the recess T of the semiconductor substrate 100 . Since the channel region is formed along a bottom surface of the recess T and between the source 110 a and the drain 110 b, the channel region may have the length longer than the length of the planar type MOS transistor. That is, a contact area between the ferroelectric layer 120 and the channel region may be remarkably increased by the recess T so that a sufficient amount of charges may be arranged on an interface between the ferroelectric layer 120 and the channel region. As a result, a depolarization may be reduced by decreasing a screening.
  • a process for forming a gate insulating layer 115 may be performed between the process for forming the recess T and the process for forming the ferroelectric layer 120 .
  • the gate insulating layer 115 may be interposed between the semiconductor substrate 100 and the ferroelectric layer 120 to improve interfacial characteristics and insulation characteristics between the gate 130 and the source/drain 110 a and 110 b.
  • FIG. 7 is a schematic diagram illustrating a memory system according to an embodiment.
  • a memory system 1000 may include a memory controller 2000 and a memory 3000 .
  • the memory 3000 may communicate with the memory controller 2000 through a bus line B.
  • the bus line B may include a bus for transmitting addresses, data, commands, etc.
  • the memory 3000 may include the ferroelectric memory device of example embodiments.
  • the ferroelectric memory device may include the ferroelectric layer formed in the semiconductor substrate. Since the ferroelectric layer may be formed in the recess of the semiconductor substrate, the channel region may have a long length so that a charge amount between the ferroelectric layer and the channel region may increase.
  • the ferroelectric memory device may be applied to a switching device as well as a memory device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Manufacturing & Machinery (AREA)
US15/213,600 2016-02-26 2016-07-19 Non-volatile memory device including ferroelectrics and method of manufacturing the same Abandoned US20170250337A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/198,529 US10734392B2 (en) 2016-02-26 2018-11-21 Resistive memory device including ferroelectrics and method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020160023560A KR102616134B1 (ko) 2016-02-26 2016-02-26 강유전체를 포함하는 비휘발성 메모리 장치 및 그 제조방법
KR10-2016-0023560 2016-02-26

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/198,529 Continuation US10734392B2 (en) 2016-02-26 2018-11-21 Resistive memory device including ferroelectrics and method of manufacturing the same

Publications (1)

Publication Number Publication Date
US20170250337A1 true US20170250337A1 (en) 2017-08-31

Family

ID=59679867

Family Applications (2)

Application Number Title Priority Date Filing Date
US15/213,600 Abandoned US20170250337A1 (en) 2016-02-26 2016-07-19 Non-volatile memory device including ferroelectrics and method of manufacturing the same
US16/198,529 Active US10734392B2 (en) 2016-02-26 2018-11-21 Resistive memory device including ferroelectrics and method of manufacturing the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US16/198,529 Active US10734392B2 (en) 2016-02-26 2018-11-21 Resistive memory device including ferroelectrics and method of manufacturing the same

Country Status (2)

Country Link
US (2) US20170250337A1 (ko)
KR (1) KR102616134B1 (ko)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140138753A1 (en) * 2012-11-20 2014-05-22 Micron Technology, Inc. Transistors, Memory Cells and Semiconductor Constructions

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050027294A (ko) * 2003-09-15 2005-03-21 삼성전자주식회사 반도체 메모리에서의 리세스 게이트 형성방법
US6965143B2 (en) * 2003-10-10 2005-11-15 Advanced Micro Devices, Inc. Recess channel flash architecture for reduced short channel effect
KR100549949B1 (ko) * 2003-12-23 2006-02-07 삼성전자주식회사 리세스 타입 모오스 트랜지스터의 제조방법 및 그의 구조
KR100621563B1 (ko) * 2004-11-03 2006-09-19 삼성전자주식회사 비휘발성 메모리 소자 및 그 제조 방법
KR100801729B1 (ko) * 2005-11-25 2008-02-11 주식회사 하이닉스반도체 함몰된 게이트구조를 갖는 트랜지스터 및 그 제조방법
KR20070056749A (ko) * 2005-11-30 2007-06-04 주식회사 하이닉스반도체 개선된 리프레쉬 특성을 가지는 리세스 채널 트랜지스터제조 방법
KR100679829B1 (ko) * 2005-12-29 2007-02-06 동부일렉트로닉스 주식회사 반도체 소자의 트랜지스터 제조방법
KR101481708B1 (ko) * 2008-11-21 2015-01-12 삼성전자주식회사 리세스 채널 트랜지스터 및 이의 제조방법
KR101928559B1 (ko) * 2012-07-17 2018-12-14 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR102181605B1 (ko) * 2013-12-23 2020-11-24 삼성전자주식회사 반도체 메모리 장치 및 그 제조 방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140138753A1 (en) * 2012-11-20 2014-05-22 Micron Technology, Inc. Transistors, Memory Cells and Semiconductor Constructions

Also Published As

Publication number Publication date
US20190109279A1 (en) 2019-04-11
US10734392B2 (en) 2020-08-04
KR20170100976A (ko) 2017-09-05
KR102616134B1 (ko) 2023-12-21

Similar Documents

Publication Publication Date Title
KR101965941B1 (ko) 강유전체 메모리 및 강유전체 메모리의 형성 방법들
US9224619B2 (en) Semiconductor device and fabricating method thereof
US7338862B2 (en) Methods of fabricating a single transistor floating body DRAM cell having recess channel transistor structure
US7863672B2 (en) Non-volatile memory device and method of fabricating the same
US8471232B2 (en) Resistive memory devices including vertical transistor arrays and related fabrication methods
US9685215B1 (en) Semiconductor memory device including a ferroelectric layer
US10748930B2 (en) Multi-level ferroelectric memory device and method of manufacturing the same
US8036017B2 (en) Semiconductor memory device
US20080246067A1 (en) Dram device and method of manufacturing the same
US9330745B2 (en) Magnetic memory devices including magnetic memory cells having opposite magnetization directions
US20220271057A1 (en) Semiconductor memory device and operating method thereof
US20240006478A1 (en) Channel conduction in semiconductor devices
KR20140121614A (ko) 비휘발성 메모리 장치
US10205090B2 (en) Semiconductor memory device
US10734392B2 (en) Resistive memory device including ferroelectrics and method of manufacturing the same
US10446608B2 (en) Non-volatile random access memory (NVRAM)
US20170025426A1 (en) Select Gates with Conductive Strips on Sides
US20220344370A1 (en) Memory devices and methods of manufacturing thereof
US9613971B2 (en) Select gates with central open areas
US9443862B1 (en) Select gates with select gate dielectric first
US20230371268A1 (en) Memory device, and methods thereof
US20220376114A1 (en) Memory cell, memory cell arrangement, and methods thereof
US11758735B2 (en) Common-connection method in 3D memory
Tran Challenges of DRAM and flash scaling-potentials in advanced emerging memory devices
US20230157037A1 (en) Hybrid Memory Device And Electronic Device Including Same

Legal Events

Date Code Title Description
AS Assignment

Owner name: SK HYNIX INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KANG, SE HUN;KIL, DEOK SIN;REEL/FRAME:039390/0130

Effective date: 20160630

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION