US20160197080A1 - High voltage lateral double-diffused metal oxide semiconductor field effect transistor (ldmosfet) having a deep fully depleted drain drift region - Google Patents
High voltage lateral double-diffused metal oxide semiconductor field effect transistor (ldmosfet) having a deep fully depleted drain drift region Download PDFInfo
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- US20160197080A1 US20160197080A1 US15/067,307 US201615067307A US2016197080A1 US 20160197080 A1 US20160197080 A1 US 20160197080A1 US 201615067307 A US201615067307 A US 201615067307A US 2016197080 A1 US2016197080 A1 US 2016197080A1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
Definitions
- the semiconductor structures disclosed herein relate to lateral double-diffused metal oxide semiconductor field effect transistors (LDMOSFETS) and, more particularly, LDMOSFETS having a relatively deep, fully-depleted, drain drift region for providing ballasting resistance.
- LDMOSFETS metal oxide semiconductor field effect transistors
- an LDMOSFET like a conventional MOSFET, comprises a channel region positioned laterally between a source region and a drain region.
- the LDMOSFET is asymmetrical. Specifically, the drain region of the LDMOSFET is separated from the channel region by a relatively low-doped drain drift region, which provides ballasting resistance so that the LDMOSFET has a relatively high blocking voltage (i.e., a high maximum voltage that can be applied to the transistor).
- LDMOSFETs with even higher blocking voltages and better transistor-to-substrate and/or transistor-to-transistor isolation are needed to prevent device failures.
- Each semiconductor structure can comprise a substrate and a laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate.
- LDMOSFET metal oxide semiconductor field effect transistor
- Each LDMOSFET can have a fully depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage.
- Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET.
- each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.
- a semiconductor structure comprising a semiconductor substrate.
- This semiconductor substrate can have a first type conductivity at a relatively low conductivity level (e.g., a P ⁇ substrate).
- the semiconductor structure can further comprise a transistor (e.g., a P-type lateral double-diffused metal oxide semiconductor field effect transistor (PLDMOSFET)) on the substrate.
- a transistor e.g., a P-type lateral double-diffused metal oxide semiconductor field effect transistor (PLDMOSFET)
- the transistor can comprise a plurality of intra-transistor wells within the substrate.
- These intra-transistor wells can comprise a first intra-transistor well having the first type conductivity (e.g., a P-well); a second intra-transistor well positioned laterally adjacent to the first intra-transistor well and having a second type conductivity (e.g., an N-well); a third intra-transistor well positioned laterally adjacent to the second intra-transistor well and having the first type conductivity (e.g., another P-well); and a fourth intra-transistor well positioned laterally adjacent to the third intra-transistor well and having the second type conductivity (e.g., another N-well).
- first type conductivity e.g., a P-well
- a second intra-transistor well positioned laterally adjacent to the first intra-transistor well and having a second type conductivity (e.g., an N-well)
- a third intra-transistor well positioned laterally adjacent to the second intra-transistor well and having the first type conduct
- the transistor can further comprise, within the substrate at the top surface, a drain region, a source region, one or more contact regions and a trench isolation structure that electrically isolates these regions.
- the transistor can comprise a drain region within the first intra-transistor well at the top surface of the substrate and a source region within the fourth intra-transistor well at the top surface of the substrate.
- the drain region and the source region can each have the first type conductivity at a relatively high conductivity level (e.g., a P+drain region and a P+ source region).
- the transistor can comprise a contact region within the fourth intra-transistor well at the top surface of the substrate. This contact region can have the second type conductivity at a relatively high conductivity level (e.g., an N+ contact region).
- this transistor can further comprise another contact region, having the second type conductivity at a relatively high conductivity level (e.g., another N+ contact region), within the second intra-transistor well at the top surface of the substrate.
- another contact region having the second type conductivity at a relatively high conductivity level (e.g., another N+ contact region), within the second intra-transistor well at the top surface of the substrate.
- the drain region, source region and any contact regions can be electrically isolated by a trench isolation structure.
- the transistor can also comprise an intra-transistor band in the substrate below and in contact with the first intra-transistor well, the second intra-transistor well, the third intra-transistor well and the fourth intra-transistor well.
- This intra-transistor band can have the first type conductivity (e.g., a P-band).
- the semiconductor structure can further comprise, within the substrate, a first isolation well, a second isolation well and an isolation band.
- the first isolation well can be positioned laterally around (i.e., can border) the transistor and can have the second type conductivity (e.g., an N-type isolation well).
- the second isolation well can be positioned laterally between the fourth intra-transistor well and the first isolation well, can have the first type conductivity (e.g., a P-type isolation well) and can extend vertically to the intra-transistor band.
- the second isolation band can be below and in contact with the first isolation well and the intra-transistor band and can have the second type conductivity (e.g., an N-type isolation band) such that the transistor is electrically isolated from both a lower portion of the substrate and adjacent devices on the substrate.
- the second type conductivity e.g., an N-type isolation band
- the transistor will have a fully depleted deep drain drift region located within the intra-transistor band between the second intra-transistor well and the isolation band. This fully depleted drain drift region will ensure that the transistor has a relatively high blocking voltage.
- This semiconductor substrate can have a first type conductivity at a relatively low conductivity level (e.g., a P ⁇ substrate).
- the semiconductor structure can further comprise a transistor (e.g., a P-type lateral double-diffused metal oxide semiconductor field effect transistor (PLDMOSFET)) on the substrate.
- a transistor e.g., a P-type lateral double-diffused metal oxide semiconductor field effect transistor (PLDMOSFET)
- the transistor can comprise a plurality of intra-transistor wells within the substrate. These intra-transistor wells can comprise a first intra-transistor well having the first type conductivity (e.g., a P-well) and a second intra-transistor well positioned laterally adjacent to the first intra-transistor well and having a second type conductivity (e.g., an N-well).
- first type conductivity e.g., a P-well
- a second intra-transistor well positioned laterally adjacent to the first intra-transistor well and having a second type conductivity (e.g., an N-well).
- This transistor can further comprise, within the substrate at the top surface, a drain region, a source region, one or more contact regions and a trench isolation region that electrically isolates these regions.
- the transistor can comprise a drain region within the first intra-transistor well at the top surface of the substrate and a source region within the second intra-transistor well at the top surface of the substrate.
- the drain region and the source region can each have the first type conductivity at a relatively high conductivity level (e.g., a P+ drain region and a P+ source region).
- the transistor can comprise a contact region within the second intra-transistor well at the top surface of the substrate. This contact region can have the second type conductivity at a relatively high conductivity level (e.g., an N+ contact region).
- This transistor can also comprise another contact region, having the second type conductivity at a relatively high conductivity level (e.g., another N+ contact region), within the first intra-transistor well at the top surface of the substrate between the drain region and the second intra-transistor well.
- another contact region having the second type conductivity at a relatively high conductivity level (e.g., another N+ contact region) within the first intra-transistor well at the top surface of the substrate between the drain region and the second intra-transistor well.
- the drain region, source region and any contact regions can be electrically isolated by a trench isolation structure.
- the transistor can also comprise an intra-transistor band.
- This intra-transistor band can be positioned in the substrate below and in contact with the first intra-transistor well and the second intra-transistor well.
- This intra-transistor band can have the first type conductivity (e.g., a P-band).
- the semiconductor structure can further comprise a first isolation well, a second isolation well, and an isolation band.
- the first isolation well can be positioned laterally around (i.e., can border) the transistor and can have the second type conductivity (e.g., an N-type isolation well).
- the second isolation well can be positioned laterally between the second intra-transistor well and the first isolation well, can have the first type conductivity (e.g., a P-type isolation well) and can extend vertically to the intra-transistor band.
- the isolation band can be below and in contact with the first isolation well and the intra-transistor band and can have the second type conductivity (e.g., an N-type isolation band) such that the transistor is electrically isolated from both a lower portion of the substrate and adjacent devices on the substrate.
- the second type conductivity e.g., an N-type isolation band
- the transistor will have a fully depleted deep drain drift region located within the first intra-transistor well and the intra-transistor band between the contact region and the isolation band. This fully depleted drain drift region will ensure that the transistor has a relatively high blocking voltage.
- This semiconductor substrate can have with a first type conductivity at a relatively low conductivity level (e.g., a P ⁇ substrate).
- the semiconductor structure can further comprise a transistor (e.g., an N-type lateral double-diffused metal oxide semiconductor field effect transistor (NLDMOSFET)) on the substrate.
- the transistor can comprise a plurality of intra-transistor wells within the substrate. These intra-transistor wells can comprise a first intra-transistor well in the substrate and having a second type conductivity (e.g., an N-well); a second intra-transistor well in the substrate within the first intra-transistor well and having the first type conductivity (e.g., a P-well); and a third intra-transistor well positioned laterally adjacent to the first intra-transistor well and having the first type conductivity (e.g., another P-well).
- a transistor e.g., an N-type lateral double-diffused metal oxide semiconductor field effect transistor (NLDMOSFET)
- NLDMOSFET metal oxide semiconductor field effect transistor
- the first intra-transistor well can extend a first depth into the substrate from the top surface
- the second intra-transistor well can extend a second depth into the substrate from the top surface and the first depth can be deeper than the second depth (i.e., the second intra-transistor well can be a more shallow well than the first intra-transistor well).
- This transistor can further comprise, within the substrate at the top surface, a drain region, a source region, one or more contact regions, and a trench isolation structure that electrically isolates these regions.
- the transistor can comprise a drain region within the first intra-transistor well at the top surface of the substrate and a source region within the third intra-transistor well at the top surface of the substrate.
- the drain region and the source region can each have the second type conductivity at a relatively high conductivity level (e.g., a N+ drain region and a N+ source region).
- the transistor can also comprise a contact region within the third intra-transistor well. This contact region can have the first type conductivity at a relatively high conductivity level (e.g., a P+ contact region).
- this transistor can further comprise another contact region, having the first type conductivity at a relatively high conductivity level (e.g., another P+ contact region), within the second intra-transistor well at the top surface of the substrate.
- another contact region having the first type conductivity at a relatively high conductivity level (e.g., another P+ contact region) within the second intra-transistor well at the top surface of the substrate.
- the drain region, source region and any contact regions can be electrically isolated by a trench isolation structure.
- the semiconductor structure can further comprise, within the substrate, a first isolation band, a first isolation well, a second isolation well and a second isolation band.
- the first isolation band can be positioned below and in contact with the first intra-transistor well.
- This first isolation band can have the first type conductivity (e.g., a P-type isolation band).
- the first isolation well can have the second type conductivity (e.g., an N-type isolation well) and can be positioned laterally around (i.e., can border) the transistor.
- the second isolation well can have the first type conductivity (e.g., a P-type isolation well) and can be positioned laterally between the first isolation well and the first intra-transistor well of the transistor and can extend vertically to the first isolation band.
- the second isolation band can be below the first isolation well, the first isolation band and the second intra-transistor well of the transistor and can have the second type conductivity (e.g., an N-type isolation band) such that the transistor is electrically isolated from a lower portion of the substrate and adjacent devices on the substrate.
- the second type conductivity e.g., an N-type isolation band
- the transistor will have a fully depleted deep drain drift region located within the first intra-transistor well between the second intra-transistor well and the first isolation band. This fully depleted drain drift region will ensure that the transistor has a relatively high blocking voltage.
- yet another semiconductor structure comprising a semiconductor substrate with a first type conductivity at a relatively low conductivity level (e.g., a P ⁇ substrate).
- the semiconductor structure can further comprise a transistor (e.g., an N-type lateral double-diffused metal oxide semiconductor field effect transistor (NLDMOSFET)) on the substrate.
- the transistor can comprise a plurality of intra-transistor wells within the substrate. These intra-transistor wells can comprise a first intra-transistor well in the substrate and having a second type conductivity (e.g., an N-well) and a second intra-transistor well in the positioned laterally adjacent to the first intra-transistor well and having the first type conductivity (e.g., a P-well).
- a transistor e.g., an N-type lateral double-diffused metal oxide semiconductor field effect transistor (NLDMOSFET)
- NLDMOSFET metal oxide semiconductor field effect transistor
- This transistor can further comprise, within the substrate at the top surface, a drain region, a source region, one or more contact regions and a trench isolation region electrically isolating those regions.
- the transistor can further comprise a drain region within the first intra-transistor well at the top surface of the substrate and a source region within the second intra-transistor well at the top surface of the substrate.
- the drain region and the source region can each have the second type conductivity at a relatively high conductivity level (e.g., a N+ drain region and a N+ source region).
- the transistor can also comprise a contact region within the second intra-transistor well. This contact region can have the first type conductivity at a relatively high conductivity level (e.g., a P+ contact region).
- This transistor can also comprise another contact region, having the first type conductivity at a relatively high conductivity level (e.g., another P+ contact region), within the first intra-transistor well at the top surface of the substrate.
- another contact region having the first type conductivity at a relatively high conductivity level (e.g., another P+ contact region), within the first intra-transistor well at the top surface of the substrate.
- the drain region, source region and any contact regions can be electrically isolated by a trench isolation structure.
- the semiconductor structure can further comprise, within the substrate, a first isolation band, a first isolation well, a second isolation well and a second isolation band.
- the first isolation band can be positioned below and in contact with the first intra-transistor well.
- This first isolation band can have the first type conductivity (e.g., a P-band).
- the first isolation well can have the second type conductivity (e.g., an N-type isolation well) and can be positioned laterally around (i.e., can border) the transistor.
- the second isolation well can have the first type conductivity (e.g., a P-type isolation well) and can be positioned laterally between the first isolation well and the first intra-transistor well of the transistor and can extend vertically to the first isolation band.
- the second isolation band can be below the first isolation well, the first isolation band and the second intra-transistor well of the transistor and can have the second type conductivity (e.g., an N-band) such that the transistor is electrically isolated from a lower portion of the substrate and adjacent devices on the substrate.
- the second type conductivity e.g., an N-band
- the transistor will have a fully depleted deep drain drift region located within the first intra-transistor well between the contact region and the first isolation band. This fully depleted drain drift region will ensure that the transistor has a relatively high blocking voltage.
- FIG. 1 is a vertical cross-section diagram illustrating a P-type lateral double-diffused metal oxide semiconductor field effect transistor
- FIG. 2 is a vertical cross-section diagram illustrating another P-type lateral double-diffused metal oxide semiconductor field effect transistor
- FIG. 3 is a horizontal cross-section diagram further illustrating the P-type lateral double-diffused metal oxide semiconductor field effect transistor of FIG. 1 or FIG. 2 ;
- FIG. 4 is a vertical cross-section diagram illustrating yet another P-type lateral double-diffused metal oxide semiconductor field effect transistor
- FIG. 5 is a horizontal cross-section diagram further illustrating the P-type lateral double-diffused metal oxide semiconductor field effect transistor of FIG. 4 ;
- FIG. 6 is a vertical cross-section diagram illustrating an N-type lateral double-diffused metal oxide semiconductor field effect transistor
- FIG. 7 is a vertical cross-section diagram illustrating another N-type lateral double-diffused metal oxide semiconductor field effect transistor
- FIG. 8 is a horizontal cross-section diagram further illustrating the N-type lateral double-diffused metal oxide semiconductor field effect transistor of FIG. 6 or FIG. 7 ;
- FIG. 9 is a vertical cross-section diagram illustrating yet another N-type lateral double-diffused metal oxide semiconductor field effect transistor
- FIG. 10 is a horizontal cross-section diagram further illustrating the N-type lateral double-diffused metal oxide semiconductor field effect transistor of FIG. 9 ;
- FIG. 11 is a vertical cross-section diagram illustrating an exemplary inverter comprising the transistors of FIGS. 1 and 6 ;
- FIG. 12 is a vertical cross-section diagram illustrating another exemplary inverter comprising the transistors of FIGS. 2 and 7 ;
- FIG. 13 is a vertical cross-section diagram illustrating yet another exemplary inverter comprising the transistors of FIGS. 4 and 9 ;
- FIG. 14 is a vertical cross-section diagram illustrating two of the transistors of FIG. 1 stacked.
- a lateral double-diffused metal oxide semiconductor field effect transistor like a conventional MOSFET transistor, comprises a channel region positioned laterally between a source region and a drain region.
- the LDMOSFET is asymmetrical. Specifically, the drain region of the LDMOSFET is separated from the channel region by a relatively low-doped drain drift region, which provides ballasting resistance so that the LDMOSFET has a relatively high blocking voltage (i.e., a high maximum voltage that can be applied to the transistor).
- LDMOSFETs with even higher blocking voltages and better transistor-to-substrate and/or transistor-to-transistor isolation are needed to prevent device failures.
- Each semiconductor structure can comprise a substrate and a laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate.
- LDMOSFET metal oxide semiconductor field effect transistor
- Each LDMOSFET can have a fully depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage.
- Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET.
- each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.
- the first type conductivity is referred to as being P-type conductivity and the second type conductivity is referred to as being N-type conductivity.
- the first type conductivity can comprise N-type conductivity and the second type conductivity can comprise P-type conductivity.
- different dopants can be used to achieve the different type conductivities and that the dopants may vary depending upon the different semiconductor materials used.
- a silicon-based semiconductor material having N-type conductivity is typically doped with an N-type dopant (e.g., a Group V dopant, such as arsenic (As), phosphorous (P) or antimony (Sb)), whereas a silicon-based semiconductor material having P-type conductivity is typically doped with a P-type dopant (e.g., a Group III dopant, such as boron (B) or indium (In)).
- N-type dopant e.g., a Group V dopant, such as arsenic (As), phosphorous (P) or antimony (Sb)
- P-type dopant e.g., a Group III dopant, such as boron (B) or indium (In)
- GaN gallium nitride
- Si silicon
- the semiconductor substrate 101 can comprise a bulk silicon substrate or any other bulk semiconductor substrate.
- the semiconductor substrate 101 can have a first type conductivity (e.g., P-type conductivity) at a relatively low conductivity level.
- the semiconductor substrate 101 can comprise a P ⁇ substrate.
- the semiconductor structure 100 can further comprise a transistor 1 A, as in FIG. 1 , or 1 B, as in FIG. 2 , on the semiconductor substrate 101 and, particularly, a P-type lateral double-diffused metal oxide semiconductor field effect transistor (PLDMOSFET) on the substrate 101 .
- a transistor 1 A as in FIG. 1 , or 1 B, as in FIG. 2
- PLDMOSFET P-type lateral double-diffused metal oxide semiconductor field effect transistor
- the transistor 1 A, 1 B can comprise a plurality of intra-transistor wells 104 - 107 within the substrate 101 .
- an “intra-transistor well” refers to a well (i.e., a dopant implant region), which is an active component of the transistor.
- These intra-transistor wells can comprise, for example, a first intra-transistor well 104 having the first type conductivity (e.g., a P-well); a second intra-transistor well 105 positioned laterally adjacent to the first intra-transistor well 104 and having a second type conductivity (e.g., an N-well); a third intra-transistor well 106 positioned laterally adjacent to the second intra-transistor well 105 and having the first type conductivity (e.g., another P-well); and a fourth intra-transistor well 107 positioned laterally adjacent to the third intra-transistor well 106 and having the second type conductivity (e.g., another N-well).
- Each of these intra-transistor wells 104 - 107 can be positioned at the top surface 120 of the semiconductor substrate 101 and can extend vertically into the semiconductor substrate 101 some predetermined depth (e.g., a same predetermined depth 121 ).
- the third intra-transistor well 106 can be physically separated from the fourth intra-transistor well 107 by a space 141 , as shown.
- the space 141 between the third intra-transistor well 106 and fourth intra-transistor well 107 will have the same doping type and conductivity level as the lower portion 191 of the substrate 101 (e.g., P ⁇ ).
- the third intra-transistor well 106 can be immediately adjacent to (i.e., can abut) the fourth intra-transistor well 107 (not shown).
- the transistor 1 A, 1 B can further comprise a gate structure 130 on the top surface 120 of the substrate 101 .
- a first side 131 of the gate structure 130 can extend laterally over the third intra-transistor well 106 .
- a second side 132 of the gate structure 130 can extend laterally over the fourth intra-transistor well 107 and can define the channel region 140 of the transistor 1 A, 1 B.
- the gate structure 130 can comprise a gate dielectric layer (e.g., a gate oxide layer, a high-k gate dielectric layer or other suitable gate dielectric layer) and a gate conductor layer (e.g., a polysilicon gate conductor layer, a metal gate conductor layer, a dual work function gate conductor layer or other suitable gate conductor layer) on the gate dielectric layer.
- a gate dielectric layer e.g., a gate oxide layer, a high-k gate dielectric layer or other suitable gate dielectric layer
- a gate conductor layer e.g., a polysilicon gate conductor
- the transistor 1 A, 1 B can further comprise, at the top surface 120 of the substrate 101 on either side of the gate structure 130 , a drain region 111 , a source region 112 , various contact regions (e.g., 113 and, optionally, 119 ) and a trench isolation structure 110 that electrically isolates these regions.
- the drain region 111 can be positioned within the first intra-transistor well 104 at the top surface 120 of the substrate 101 adjacent to the first side 131 of the gate structure 130 and the source region 112 can be positioned within the fourth intra-transistor well 107 at the top surface 120 of the substrate 101 adjacent to the second side 132 of the gate structure 130 .
- the drain region 111 and source region 112 can be asymmetric with respect to the gate structure 130 and, specifically, the drain region 111 can be positioned farther from the gate structure 130 than the source region 112 , as shown.
- the drain region 111 and the source region 112 can each comprise doped regions having the first type conductivity at a relatively high conductivity level (e.g., a P+ drain region and a P+ source region).
- a contact region 113 (also referred to herein as a body contact region), having the second type conductivity at a relatively high conductivity level (e.g., an N+ contact region), can be positioned within the fourth intra-transistor well 107 at the top surface 120 of the substrate 101 so as to allow that fourth intra-transistor well 107 to be electrically biased.
- the source region 112 can be positioned closer to the gate structure 130 than the contact region 113 .
- the transistor 1 B can further comprise a contact region 119 , having the second type conductivity at a relatively high conductivity level (e.g., an N+ contact region), within the second intra-transistor well 105 at the top surface 120 of the substrate 101 so as to effectively form a junction field effect transistor.
- a contact region 119 will be closer to the gate structure 130 than the drain region 111 .
- a patterned trench isolation structure 110 at the top surface 120 of the substrate 101 can electrically isolate the drain region 111 , source region 112 , and contact regions (e.g., the contact region 113 and, if applicable, the contact region 119 ).
- This trench isolation structure 110 can comprise, for example, a conventional shallow trench isolation (STI) structure) comprising a patterned trench, which is filled with one or more isolation materials (e.g., silicon dioxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), and/or any other suitable isolation material).
- STI shallow trench isolation
- the transistor 1 A, 1 B can further comprise an intra-transistor band 103 within the substrate 101 .
- an “intra-transistor band” refers to a band (i.e., a buried dopant implant region within the substrate and separated from the top surface by some predetermined distance), which is an active component of the transistor.
- the intra-transistor band 103 can be positioned in the substrate 101 below and in contact with the first intra-transistor well 104 , the second intra-transistor well 105 , the third intra-transistor well 106 and the fourth intra-transistor well 107 .
- This intra-transistor band 103 can have the first type conductivity (e.g., a P-band).
- the semiconductor structure 100 can further comprise, within the substrate 101 , a first isolation well 108 , a second isolation well 109 and an isolation band 102 .
- an “isolation well” refers to a well (i.e., a dopant implant region) that electrically isolates adjacent devices and/or components thereof.
- Such isolation wells can be positioned at the top surface of the semiconductor substrate and can extend vertically into the semiconductor substrate some predetermined depth (e.g., the same predetermined depth 121 as the intra-transistor wells).
- an “isolation band” refers to a band (i.e., a buried dopant implant region within the substrate and separated from the top surface by some predetermined distance), which electrically isolates devices and components thereof from the lower portion of the substrate.
- the first isolation well 108 can be positioned laterally around (i.e., can border) the transistor 1 A, 1 B (see the cross-section diagram of FIG. 3 ) and can have the second type conductivity (e.g., an N-type isolation well).
- the second isolation well 109 can be positioned laterally between the fourth intra-transistor well 107 and the first isolation well 108 , can have the first type conductivity (e.g., a P-type isolation well), and can extend vertically to the intra-transistor band 103 .
- the isolation band 102 can be below and in contact with the first isolation well 108 and the intra-transistor band 103 .
- the isolation band 102 can have vertical portion aligned below and in contact with the first isolation well 108 . This vertical portion can further be positioned laterally around (i.e., can border) the intra-transistor band 103 . Additionally, the isolation band 102 can have a horizontal portion that separates the bottom surface of the intra-transistor band 103 and the lower portion 191 of the substrate 101 . This isolation band 102 can have the second type conductivity (e.g., an N-band). The isolation band 102 in combination with the first isolation well 108 , which also has the second type conductivity, can electrically isolate the transistor 1 A, 1 B from the lower portion 191 of the substrate 101 and from any adjacent devices (not shown) on the substrate 101 .
- the isolation band 102 in combination with the first isolation well 108 , which also has the second type conductivity, can electrically isolate the transistor 1 A, 1 B from the lower portion 191 of the substrate 101 and from any adjacent devices (not shown) on the substrate 101 .
- the semiconductor structure 100 can further comprise an additional contact region 115 that allows the well 108 and, thereby the band 102 to be electrically biased. More specifically, the semiconductor structure 100 can further comprise a contact region 115 , having the second type at a relatively high conductivity level (e.g., an N+ contact region), within the first isolation well 108 at the top surface of the substrate 101 so as to allow that isolation well 108 and, thereby the band 102 below to be electrically biased. As with the other contact regions 113 , 119 , described above, the contact region 115 can be electrically isolated by the trench isolation region 110 .
- a relatively high conductivity level e.g., an N+ contact region
- the transistor 1 A, 1 B will have a fully-depleted deep drain drift region 150 located within the intra-transistor band 103 between the second intra-transistor well 105 and the isolation band 102 .
- This fully-depleted drain drift region 150 will ensure that the transistor 1 A, 1 B has a relatively high blocking voltage.
- the transistor 1 A, 1 B is electrically isolated by the first isolation well 108 and isolation band 102 from the lower portion 191 of the substrate 101 and from adjacent devices on the substrate 101 , the transistor 1 A, 1 B can be placed in relatively close proximity to adjacent devices in order to increase device density on the substrate 101 with minimal risk of shorts.
- the semiconductor substrate 201 can comprise a bulk silicon substrate or any other bulk semiconductor substrate.
- the semiconductor substrate 201 can have a first type conductivity (e.g., P-type conductivity) at a relatively low conductivity level.
- the semiconductor substrate 201 can comprise a P ⁇ substrate.
- the semiconductor structure 200 can further comprise a transistor 2 on the semiconductor substrate 201 and, particularly, a P-type lateral double-diffused metal oxide semiconductor field effect transistor (PLDMOSFET) on the substrate 201 .
- PLDMOSFET P-type lateral double-diffused metal oxide semiconductor field effect transistor
- the transistor 2 can comprise a plurality of intra-transistor wells 204 and 207 within the substrate 201 .
- an “intra-transistor well” refers to a well (i.e., a dopant implant region), which is an active component of the transistor.
- These intra-transistor wells can comprise a first intra-transistor well 204 having the first type conductivity (e.g., a P-well) and a second intra-transistor well 207 positioned laterally adjacent to the first intra-transistor well 204 and having a second type conductivity (e.g., an N-well).
- These intra-transistor wells 204 and 207 can be positioned at the top surface 220 of the semiconductor substrate 201 and can extend vertically into the semiconductor substrate 201 some predetermined depth (e.g., a same predetermined depth 221 ).
- first intra-transistor well 204 can be physically separated from the second intra-transistor well 207 by a space 241 , as shown.
- the space 241 between the first intra-transistor well 204 and second intra-transistor well 207 will have the same doping type and conductivity level as the lower portion 291 of the substrate 201 (e.g., P ⁇ ).
- the first intra-transistor well 204 can be immediately adjacent to (i.e., can abut) the second intra-transistor well 207 .
- the transistor 2 can further comprise a gate structure 230 on the top surface 220 of the substrate 201 .
- a first side 231 of the gate structure 230 can extend laterally over the first intra-transistor well 204 .
- a second side 232 of the gate structure 230 can extend laterally over the second intra-transistor well 207 and can define the channel region 240 of the transistor 2 .
- the gate structure 230 can comprise a gate dielectric layer (e.g., a gate oxide layer, a high-k gate dielectric layer or other suitable gate dielectric layer) and a gate conductor layer (e.g., a polysilicon gate conductor layer, a metal gate conductor layer, a dual work function gate conductor layer or other suitable gate conductor layer) on the gate dielectric layer.
- the transistor 2 can further comprise, at the top surface 220 of the substrate 201 on either side of the gate structure 230 , a drain region 211 , a source region 212 , various contact regions (e.g., 213 and 219 ) and a trench isolation structure 210 that electrically isolates these regions.
- the transistor 2 can further comprise a drain region 211 within the first intra-transistor well 204 at the top surface 220 of the substrate 201 adjacent to the first side 231 of the gate structure 230 and a source region 212 within the second intra-transistor well 207 at the top surface 220 of the substrate 201 adjacent to the second side 232 of the gate structure 230 .
- the source region 212 and drain region 211 can be asymmetric with respect to the gate structure 230 and, specifically, the drain region 211 can be positioned farther from the gate structure 230 than the source region 212 , as shown.
- the drain region 211 and the source region 212 can comprise doped regions having the first type conductivity at a relatively high conductivity level (e.g., a P+ drain region and a P+ source region).
- the transistor 2 can further comprise an intra-transistor band 203 within the substrate 201 .
- an “intra-transistor band” refers to a band (i.e., a buried dopant implant region within the substrate and separated from the top surface by some predetermined distance) that is an active component of the transistor.
- the intra-transistor band 203 can be in the substrate 201 below and in contact with the first intra-transistor well 204 and the second intra-transistor well 207 .
- This intra-transistor band 203 can have the first type conductivity (e.g., a P-band).
- a contact region 213 (also referred to herein as a body contact region), having the second type conductivity at a relatively high conductivity level (e.g., an N+ contact region), can be positioned within the second intra-transistor well 207 at the top surface 220 of the substrate 201 so as to allow that second intra-transistor well 207 to be electrically biased.
- the source region 212 can be positioned closer to the gate structure 230 than the contact region 213 .
- the transistor 2 can further comprise another contact region 219 , having the second type conductivity at a relatively high conductivity level (e.g., an N+ contact region), within the first intra-transistor well 204 at the top surface 220 of the substrate 201 so as to effectively form a junction field effect transistor.
- the contact region 219 can be positioned closer to the gate structure 230 than the drain region 211 .
- a patterned trench isolation structure 210 at the top surface 220 of the substrate 201 can electrically isolate the drain region 211 , source region 212 , and contact regions 213 , 219 .
- This trench isolation structure 210 can comprise, for example, a conventional shallow trench isolation (STI) structure) comprising a patterned trench, which is filled with one or more isolation materials (e.g., silicon dioxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), and/or any other suitable isolation material).
- STI shallow trench isolation
- the semiconductor structure 200 can further comprise, within the substrate 201 , a first isolation well 208 , a second isolation well 209 and an isolation band 202 .
- an “isolation well refers” to a well (i.e., a dopant implant region) that electrically isolates adjacent devices and/or components thereof.
- Such isolation wells can be positioned at the top surface of the semiconductor substrate and can extend vertically into the semiconductor substrate some predetermined depth (e.g., the same predetermined depth 221 as the intra-transistor wells).
- an “isolation band” refers to a band (i.e., a buried dopant implant region within the substrate and separated from the top surface by some predetermined distance), which electrically isolates devices and components thereof from the lower portion of the substrate.
- the first isolation well 208 can be positioned laterally around (i.e., can border) the transistor 2 (see the cross-section diagram of FIG. 5 ) and can have the second type conductivity (e.g., an N-type isolation well).
- the second isolation well 209 can be positioned laterally between the second intra-transistor well 207 and the first isolation well 208 , can have the first type conductivity (e.g., a P-type isolation well) and can extend vertically to the intra-transistor band 203 .
- the isolation band 202 can be below and in contact with the first isolation well 208 and the intra-transistor band 203 . More specifically, the isolation band 202 can have vertical portion aligned below and in contact with the first isolation well 208 .
- This vertical portion can further be positioned laterally around (i.e., can border) the intra-transistor band 203 .
- the isolation band 202 can have a horizontal portion that separates the bottom surface of the intra-transistor band 203 and the lower portion 291 of the substrate 201 .
- This isolation band 202 can have the second type conductivity (e.g., an N-band).
- the isolation band 202 in combination with the first isolation well 208 which also has the second type conductivity, can electrically isolate the transistor 2 from the lower portion 291 of the substrate 201 and from any adjacent devices (not shown) on the substrate 201 .
- the semiconductor structure 200 can further comprise an additional contact region 215 that allows the well 208 and, thereby the band 202 to be electrically biased. More specifically, the semiconductor structure 200 can further comprise a contact region 215 , having the second conductivity type at a relatively high conductivity level (e.g., an N+ contact region), within the first isolation well 208 at the top surface 220 of the substrate 201 so as to allow that isolation well 208 and, thereby the band 202 below to be electrically biased. As with the other contact regions 213 , 219 , described above, the contact region 215 can be electrically isolated by the trench isolation region 210 .
- a relatively high conductivity level e.g., an N+ contact region
- the transistor 2 will have a fully-depleted deep drain drift region 250 located within the intra-transistor band 203 and first intra-transistor well 204 between contact region 219 and the isolation band 202 .
- This fully-depleted drain drift region 250 will ensure that the transistor 2 has a relatively high blocking voltage.
- the transistor 2 is electrically isolated by the first isolation well 208 and isolation band 202 from the lower portion 291 of the substrate 201 and from adjacent devices on the substrate 201 , the transistor 2 can be placed in relatively close proximity to adjacent devices in order to increase device density on the substrate 201 with minimal risk of shorts.
- the semiconductor substrate 601 can comprise a bulk silicon substrate or any other bulk semiconductor substrate.
- the semiconductor substrate 601 can have a first type conductivity (e.g., P-type conductivity) at a relatively low conductivity level.
- the semiconductor substrate 601 can comprise a P ⁇ substrate.
- the semiconductor structure 600 can further comprise a transistor 6 A, as in FIG. 6 , or 6 B, as in FIG. 7 , on the semiconductor substrate 601 and, particularly, an N-type lateral double-diffused metal oxide semiconductor field effect transistor (NLDMOSFET) on the substrate 601 .
- NLDMOSFET N-type lateral double-diffused metal oxide semiconductor field effect transistor
- this transistor 6 A, 6 B can comprise plurality of intra-transistor wells within the substrate 601 .
- an “intra-transistor well” refers to a well (i.e., a dopant implant region), which is an active component of the transistor.
- These intra-transistor wells can comprise a first intra-transistor well 604 having a second type conductivity (e.g., an N-well); a second intra-transistor well 605 within the first intra-transistor well 604 and having the first type conductivity (e.g., a P-well); and a third intra-transistor well 607 positioned laterally adjacent to the first intra-transistor well 604 and having the first type conductivity (e.g., another P-well).
- a second type conductivity e.g., an N-well
- second intra-transistor well 605 within the first intra-transistor well 604 and having the first type conductivity
- the first type conductivity e.g., a P-well
- third intra-transistor well 607 positioned laterally adjacent to the first intra-transistor well 604 and having the first type conductivity (e.g., another P-well).
- the first intra-transistor well 604 and the third intra-transistor well 607 can extend a first depth 621 into the substrate 601 from the top surface 620
- the second intra-transistor well 605 can extend a second depth 622 into the substrate 601 from the top surface 620 and the first depth 621 can be deeper than the second depth 622 (i.e., the second intra-transistor 605 well can be a more shallow well than the first and third intra-transistor wells).
- the first intra-transistor well 604 can be physically separated from the third intra-transistor well 607 by a space 641 , as shown.
- the space 641 between the first intra-transistor well 604 and third intra-transistor well 607 will have the same doping type and conductivity level as the lower portion 691 of the substrate 601 (e.g., P ⁇ ).
- the first intra-transistor well 604 can be immediately adjacent to (i.e., can abut) the third intra-transistor well 607 (not shown).
- the transistor 6 can further comprise a gate structure 630 on the top surface 620 of the substrate 601 .
- a first side 631 of the gate structure 630 can extend laterally over the first intra-transistor well 604 .
- a second side 632 of the gate structure 630 can extend laterally over the third intra-transistor well 607 and can define the channel region 640 of the transistor 6 .
- the gate structure 630 can comprise a gate dielectric layer (e.g., a gate oxide layer, a high-k gate dielectric layer or other suitable gate dielectric layer) and a gate conductor layer (e.g., a polysilicon gate conductor layer, a metal gate conductor layer, a dual work function gate conductor layer or other suitable gate conductor layer) on the gate dielectric layer.
- the transistor 6 can further comprise, at the top surface 620 of the substrate 601 on either side of the gate structure 630 , a drain region 611 , a source region 612 , various contact regions (e.g., 613 and, optionally, 619 ) and a trench isolation structure 610 that electrically isolates these regions.
- the transistor can comprise a drain region 611 within the first intra-transistor within the first intra-transistor well 604 at the top surface 620 of the substrate 601 adjacent to the first side 631 of the gate structure 630 and a source region 612 within the third intra-transistor well 607 at the top surface 620 of the substrate 601 adjacent to the second side 632 of the gate structure 630 .
- the drain region 611 and source region 612 can be asymmetric with respect to the gate structure 630 and, specifically, the drain region 611 can be positioned farther from the gate structure 630 than the source region 612 , as shown.
- the drain region 611 and the source region 612 can each have the second type conductivity at a relatively high conductivity level (e.g., a N+ drain region and a N+ source region).
- a contact region 613 (also referred to herein as a body contact region), having the first conductivity type at a relatively high conductivity level (e.g., a P+ contact region), can be positioned within the third intra-transistor well 607 at the top surface 620 of the substrate 601 so as to allow that third intra-transistor well 607 to be electrically biased.
- the source region 612 can be positioned closer to the gate structure 630 than the contact region 613 .
- the transistor 6 B can further comprise a contact region 619 , having the first conductivity type at a relatively high conductivity level (e.g., another P+ contact region), within the second intra-transistor well 605 at the top surface 620 of the substrate 601 so as to effectively form a junction field effect transistor.
- the contact region 619 can be positioned closer to the gate structure 630 than the drain region 611 .
- a patterned trench isolation structure 610 at the top surface 620 of the substrate 601 can electrically isolate the drain region 611 , source region 612 , and contact regions (e.g., the contact region 613 and, if applicable, the contact region 619 ).
- This trench isolation structure 610 can comprise, for example, a conventional shallow trench isolation (STI) structure) comprising a patterned trench, which is filled with one or more isolation materials (e.g., silicon dioxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), and/or any other suitable isolation material).
- STI shallow trench isolation
- the semiconductor structure 600 can further comprise, within the substrate 601 , a first isolation band 603 , a first isolation well 608 , a second isolation well 609 and a second isolation band 602 .
- an “isolation well” refers to a well (i.e., a dopant implant region) that electrically isolates adjacent devices and/or components thereof.
- Such isolation wells can be positioned at the top surface of the semiconductor substrate and can extend vertically into the semiconductor substrate some predetermined depth (e.g., the same predetermined depth 621 as the first and third intra-transistor wells).
- an “isolation band” refers to a band (i.e., a buried dopant implant region within the substrate and separated from the top surface by some predetermined distance), which electrically isolates devices and components thereof from the lower portion of the substrate.
- the first isolation band 603 can be positioned below and in contact with the first intra-transistor well 604 .
- This first isolation band 603 can have the first type conductivity (e.g., a P-type isolation band).
- the first isolation well 608 can have the second type conductivity (e.g., an N-type isolation well) and can be positioned laterally around (i.e., can border) the transistor 6 A, 6 B (see the cross-section diagram of FIG. 8 ).
- the second isolation well 609 can have the first type conductivity (e.g., a P-type isolation well) and can be positioned laterally between the first isolation well 608 and the first intra-transistor well 604 of the transistor 6 A, 6 B and can extend vertically to the first isolation band 603 .
- the second isolation band 602 can be below and in contact with the first isolation well 608 , the first isolation band 603 and the third intra-transistor well 607 of the transistor 6 A, 6 B. More specifically, the second isolation band 602 can have a vertical portion aligned below and in contact with the first isolation well 608 .
- the second isolation band 602 can have a horizontal portion that separates the bottom surfaces of the first isolation band 603 and the third intra-transistor well 607 from the lower portion 691 of the substrate 601 .
- the second isolation band 602 can have the second type conductivity (e.g., an N-type isolation band).
- the second isolation band 602 in combination with the first isolation well 608 which also has the second type conductivity, can electrically isolate the transistor 6 A, 6 B from the lower portion 691 of the substrate 601 and from any adjacent devices (not shown) on the substrate 601 .
- the semiconductor structure 600 can further comprise additional contact regions 614 and 615 that allow the wells 609 and 608 and, thereby the bands 603 and 602 , respectively, to be electrically biased. More specifically, the semiconductor structure 600 can further comprise a contact region 614 , having the first conductivity type at a relatively high conductivity level (e.g., a P+ contact region), within the second isolation well 609 at the top surface 620 of the substrate 601 so as to allow that isolation well 609 and, thereby the band 603 below to be electrically biased.
- a relatively high conductivity level e.g., a P+ contact region
- the semiconductor structure 600 can also further comprise a contact region 615 , having the second conductivity type at a relatively high conductivity level (e.g., an N+ contact region), within the first isolation well 608 at the top surface 620 of the substrate 601 so as to allow that isolation well 608 and, thereby the band 602 below to be electrically biased.
- a contact region 615 having the second conductivity type at a relatively high conductivity level (e.g., an N+ contact region), within the first isolation well 608 at the top surface 620 of the substrate 601 so as to allow that isolation well 608 and, thereby the band 602 below to be electrically biased.
- the contact regions 614 and 615 can be electrically isolated by the trench isolation region 610 .
- the transistor 6 A, 6 B will have a fully-depleted deep drain drift region 650 located within the first intra-transistor well 604 between the second intra-transistor well 605 and the first isolation band 603 .
- This fully-depleted drain drift region 650 will ensure that the transistor 6 A, 6 B has a relatively high blocking voltage.
- the transistor 6 A, 6 B is electrically isolated by the first isolation well 608 and isolation band 602 from the lower portion 691 of the substrate 601 and from adjacent devices on the substrate 601 , the transistor 6 A, 6 B can be placed in relatively close proximity to adjacent devices in order to increase device density on the substrate 601 with minimal risk of shorts.
- the semiconductor substrate 901 can comprise a bulk silicon substrate or any other bulk semiconductor substrate.
- the semiconductor substrate 901 can have a first type conductivity (e.g., P-type conductivity) at a relatively low conductivity level.
- the semiconductor substrate 901 can comprise a P ⁇ substrate.
- the semiconductor structure 900 can further comprise a transistor 9 on the semiconductor substrate 901 and, particularly, an N-type lateral double-diffused metal oxide semiconductor field effect transistor (NLDMOSFET) on the substrate 901 .
- NLDMOSFET N-type lateral double-diffused metal oxide semiconductor field effect transistor
- this transistor 9 can comprise plurality of intra-transistor wells within the substrate 901 .
- an “intra-transistor well” refers to a well (i.e., a dopant implant region), which is an active component of the transistor.
- These intra-transistor wells can comprise a first intra-transistor well 904 having a second type conductivity (e.g., an N-well) and a second intra-transistor well 907 positioned laterally adjacent to the first intra-transistor well 904 and having the first type conductivity (e.g., a P-well).
- Each of these intra-transistor wells 904 and 907 can be positioned at the top surface 920 of the semiconductor substrate 901 and can extend vertically into the semiconductor substrate 901 some predetermined depth (e.g., a same predetermined depth 921 ).
- first intra-transistor well 904 can be physically separated from the second intra-transistor well 907 by a space 941 , as shown.
- the space 941 between the first intra-transistor well 904 and second intra-transistor well 907 will have the same doping type and conductivity level as the lower portion 991 of the substrate 901 (e.g., P ⁇ ).
- the first intra-transistor well 904 can be immediately adjacent to (i.e., can abut) the second intra-transistor well 907 (not shown).
- the transistor 9 can further comprise a gate structure 930 on the top surface 920 of the substrate 901 .
- a first side 931 of the gate structure 930 can extend laterally over the first intra-transistor well 904 .
- a second side 932 of the gate structure 930 can extend laterally over the second intra-transistor well 907 and can define the channel region 940 of the transistor 9 .
- the gate structure 930 can comprise a gate dielectric layer (e.g., a gate oxide layer, a high-k gate dielectric layer or other suitable gate dielectric layer) and a gate conductor layer (e.g., a polysilicon gate conductor layer, a metal gate conductor layer, a dual work function gate conductor layer or other suitable gate conductor layer) on the gate dielectric layer.
- a gate dielectric layer e.g., a gate oxide layer, a high-k gate dielectric layer or other suitable gate dielectric layer
- a gate conductor layer e.g., a polysilicon gate conductor
- the transistor 9 can further comprise, at the top surface 920 of the substrate 901 on either side of the gate structure 930 , a drain region 911 , a source region 612 , various contact regions (e.g., 913 and 919 ) and a trench isolation structure 910 that electrically isolates these regions.
- the transistor 9 can comprise a drain region 911 within the first intra-transistor within the first intra-transistor well 904 at the top surface 920 of the substrate 901 adjacent to the first side 931 of the gate structure 930 and a source region 912 within the second intra-transistor well 907 at the top surface 920 of the substrate 901 adjacent to the second side 932 of the gate structure 930 .
- the drain region 911 and source region 912 can be asymmetric with respect to the gate structure 930 and, specifically, the drain region 911 can be positioned farther from the gate structure 930 than the source region 912 , as shown.
- the drain region 911 and the source region 912 can each have the second type conductivity at a relatively high conductivity level (e.g., a N+ drain region and a N+ source region).
- a contact region 913 (also referred to herein as a body contact region), having the first conductivity type at a relatively high conductivity level (e.g., a P+ contact region), can be positioned within the second intra-transistor well 907 at the top surface 920 of the substrate 901 so as to allow that second intra-transistor well 907 to be electrically biased.
- the source region 912 can be positioned closer to the gate structure 930 than the contact region 913 .
- the transistor 9 can further comprise a contact region 919 , having the first conductivity type at a relatively high conductivity level (e.g., another P+ contact region), within the first intra-transistor well 905 at the top surface 920 of the substrate 901 so as to effectively form a junction field effect transistor.
- the contact region 919 can be positioned closer to the gate structure 930 than the drain region 911 .
- a patterned trench isolation structure 910 at the top surface 920 of the substrate 901 can electrically isolate the drain region 911 , source region 912 , and contact regions 913 , 919 .
- This trench isolation structure 910 can comprise, for example, a conventional shallow trench isolation (STI) structure) comprising a patterned trench, which is filled with one or more isolation materials (e.g., silicon dioxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), and/or any other suitable isolation material).
- STI shallow trench isolation
- the semiconductor structure 900 can further comprise, within the substrate 901 , a first isolation band 903 , a first isolation well 908 , a second isolation well 909 and a second isolation band 902 .
- an “isolation well” refers to a well (i.e., a dopant implant region) that electrically isolates adjacent devices and/or components thereof.
- Such isolation wells can be positioned at the top surface of the semiconductor substrate and can extend vertically into the semiconductor substrate some predetermined depth (e.g., the same predetermined depth 921 as the first and second intra-transistor wells).
- an “isolation band” refers to a band (i.e., a buried dopant implant region within the substrate and separated from the top surface by some predetermined distance), which electrically isolates devices and components thereof from the lower portion of the substrate.
- the first isolation band 903 can be positioned below and in contact with the first intra-transistor well 904 .
- This first isolation band 903 can have the first type conductivity (e.g., a P-type isolation band).
- the first isolation well 908 can have the second type conductivity (e.g., an N-type isolation well) and can be positioned laterally around (i.e., can border) the transistor 9 (see the cross-section diagram of FIG. 10 ).
- the second isolation well 909 can have the first type conductivity (e.g., a P-type isolation well) and can be positioned laterally between the first isolation well 908 and the first intra-transistor well 904 of the transistor 9 and can extend vertically to the first isolation band 903 .
- the second isolation band 902 can be below and in contact with the first isolation well 908 , the first isolation band 903 and the second intra-transistor well 907 of the transistor 9 . More specifically, the second isolation band 902 can have a vertical portion aligned below and in contact with the first isolation well 608 . Additionally, the second isolation band 902 can have a horizontal portion that separates the bottom surfaces of the first isolation band 903 and the second intra-transistor well 907 from the lower portion 991 of the substrate 901 .
- the second isolation band 902 can have the second type conductivity (e.g., an N-type isolation band).
- the second isolation band 902 in combination with the first isolation well 908 which also has the second type conductivity, can electrically isolate the transistor 9 from the lower portion 991 of the substrate 901 and from any adjacent devices (not shown) on the substrate 901 .
- the semiconductor structure 900 can further comprise additional contact regions 914 and 915 that allow the wells 909 and 908 and, thereby the bands 903 and 902 , respectively, to be electrically biased. More specifically, the semiconductor structure 900 can further comprise a contact region 914 , having the first conductivity type at a relatively high conductivity level (e.g., a P+ contact region), within the second isolation well 909 at the top surface 920 of the substrate 901 so as to allow that isolation well 909 and, thereby the band 903 below to be electrically biased.
- a relatively high conductivity level e.g., a P+ contact region
- the semiconductor structure 900 can also further comprise a contact region 915 , having the second conductivity type at a relatively high conductivity level (e.g., an N+ contact region), within the first isolation well 908 at the top surface 920 of the substrate 901 so as to allow that isolation well 908 and, thereby the band 902 below to be electrically biased.
- a contact region 915 having the second conductivity type at a relatively high conductivity level (e.g., an N+ contact region), within the first isolation well 908 at the top surface 920 of the substrate 901 so as to allow that isolation well 908 and, thereby the band 902 below to be electrically biased.
- the contact regions 914 and 915 can be electrically isolated by the trench isolation region 910 .
- the transistor 9 will have a fully depleted deep drain drift region 950 located within the first intra-transistor well 904 between contact region 919 and the first isolation band 903 .
- This fully-depleted drain drift region 950 will ensure that the transistor 9 has a relatively high blocking voltage.
- the transistor 9 is electrically isolated by the first isolation well 908 and isolation band 902 from the lower portion 991 of the substrate 901 and from adjacent devices on the substrate 901 , the transistor 9 can be placed in relatively close proximity to adjacent devices in order to increase device density on the substrate 901 with minimal risk of shorts.
- semiconductor structures comprising multiple ones of the above-described transistors in either logic circuit (e.g., inverter) configuration or a stacked LDMOSFET configuration.
- logic circuit e.g., inverter
- stacked LDMOSFET configuration e.g., stacked LDMOSFET
- FIG. 11 is a cross-section diagram illustrating a semiconductor structure 1100 wherein the transistor 1 A of FIGS. 1 and 6A of FIG. 6 are arranged on the same substrate 1101 as a logic circuit (e.g., inverter) configuration. That is, the transistor 1 A (e.g., a PLDMOSFET) is positioned laterally adjacent to the transistor 6 A (e.g., an NLDMOSFET) on the same substrate 1101 . It should be noted that in this case the transistors 1 A and 6 A can be laterally surrounded by isolation wells 108 and 608 , respectively, having the second type conductivity, as discussed in detail above.
- a logic circuit e.g., inverter
- each transistor 1 A and 6 A can be electrically isolated from the lower portion 1191 of the semiconductor substrate 1101 below by isolation bands 102 and 602 , respectively, having the second type conductivity, as discussed in detail above.
- these isolation bands 102 , 602 can be continuous (i.e., can form adjacent portions of the same band that extends laterally under both transistors).
- FIG. 12 is a cross-section diagram illustrating a semiconductor structure 1200 wherein the transistor 1 B of FIGS. 2 and 6B of FIG. 7 are arranged on the same substrate 1201 as a logic circuit (e.g., inverter) configuration. That is, the transistor 1 B (e.g., a PLDMOSFET) is positioned laterally adjacent to the transistor 6 B (e.g., an NLDMOSFET) on the same substrate 1201 . It should be noted that in this case the transistors 1 B and 6 B can be laterally surrounded by isolation wells 108 and 608 , respectively, having the second type conductivity, as discussed in detail above.
- a logic circuit e.g., inverter
- each transistor 1 B and 6 B can be electrically isolated from the lower portion 1291 of the semiconductor substrate 1201 below by isolation bands 102 and 602 , respectively, having the second type conductivity, as discussed in detail above.
- these isolation bands 102 , 602 can be continuous (i.e., can form adjacent portions of the same band that extends laterally under both transistors).
- FIG. 13 is a cross-section diagram illustrating a semiconductor structure 1300 wherein the transistor 2 of FIGS. 4 and 9 of FIG. 9 are arranged on the same substrate 1301 as a logic circuit (e.g., inverter) configuration. That is, the transistor 2 (e.g., a PLDMOSFET) is positioned laterally adjacent to the transistor 9 (e.g., an NLDMOSFET) on the same substrate 1301 .
- the transistors 2 and 9 can be laterally surrounded by isolation wells 208 and 908 , respectively, having the second type conductivity, as discussed in detail above. However, the portion of these wells 208 , 908 between the transistors 2 and 9 can be shared.
- each transistor 2 and 9 can be electrically isolated from the lower portion 1391 of the semiconductor substrate 1301 below by isolation bands 202 and 902 , respectively, having the second type conductivity, as discussed in detail above.
- these isolation bands 202 , 902 can be continuous (i.e., can form adjacent portions of the same band that extends laterally under both transistors).
- FIG. 14 is a cross-section diagram illustrating a semiconductor structure 1400 wherein two of transistors 1 A of FIG. 1 (e.g., two PDLMOSFETs) are stacked together on the same substrate 1401 . That is, a first transistor 1 A is positioned laterally adjacent to another transistor 1 A on the same substrate 1401 . It should be noted that in this case two the transistors 1 A can share a fourth intra-transistor well 107 (within which their respective source regions 112 are located) as well as the contact region 113 to that well 107 . The two transistors 1 A can be laterally surrounded by a single isolation well 108 , having the second type conductivity, as discussed in detail above.
- two of transistors 1 A of FIG. 1 e.g., two PDLMOSFETs
- the two transistors 1 A can be electrically isolated from the lower portion 1491 of the semiconductor substrate 1401 below by a single isolation band 102 that extends laterally below both transistors. It should be understood that the other disclosed LDMOSFETs 1 B, 2 , 6 A, 6 B and 9 can be stacked together in a similar manner.
- CMOS complementary metal oxide semiconductor
- multiple masked dopant implantation processes can be performed to create, within a bulk semiconductor substrate, the multiple discrete dopant implant regions (i.e., the various wells and bands described) having the desired conductivity type and level and as well as the relative positioning. Additional masked dopant implantation processes can be performed in order to form the source, drain and contact regions described. Alternatively, multiple in-situ doped epitaxial growth processes can be performed in order to form the source, drain and contact regions described.
- Each semiconductor structure can comprise a substrate and a laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate.
- LDMOSFET metal oxide semiconductor field effect transistor
- Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage.
- Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET.
- each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.
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Abstract
Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.
Description
- This application is a Divisional of U.S. application Ser. No. 14/672,865 filed Mar. 30, 2015, that is a Divisional of U.S. application Ser. No. 13/959,777 filed Aug. 6, 2013, issued as U.S. Pat. No. 9,059,278 on Jun. 16, 2015, the complete disclosures of which, in their entirety, are herein incorporated by reference.
- The semiconductor structures disclosed herein relate to lateral double-diffused metal oxide semiconductor field effect transistors (LDMOSFETS) and, more particularly, LDMOSFETS having a relatively deep, fully-depleted, drain drift region for providing ballasting resistance.
- Typically, an LDMOSFET, like a conventional MOSFET, comprises a channel region positioned laterally between a source region and a drain region. However, unlike the conventional MOSFET, the LDMOSFET is asymmetrical. Specifically, the drain region of the LDMOSFET is separated from the channel region by a relatively low-doped drain drift region, which provides ballasting resistance so that the LDMOSFET has a relatively high blocking voltage (i.e., a high maximum voltage that can be applied to the transistor). However, as operating voltages and device densities increase, LDMOSFETs with even higher blocking voltages and better transistor-to-substrate and/or transistor-to-transistor isolation are needed to prevent device failures.
- In view of the foregoing, disclosed herein are semiconductor structures. Each semiconductor structure can comprise a substrate and a laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.
- More particularly, disclosed herein is a semiconductor structure comprising a semiconductor substrate. This semiconductor substrate can have a first type conductivity at a relatively low conductivity level (e.g., a P− substrate).
- The semiconductor structure can further comprise a transistor (e.g., a P-type lateral double-diffused metal oxide semiconductor field effect transistor (PLDMOSFET)) on the substrate. Specifically, the transistor can comprise a plurality of intra-transistor wells within the substrate. These intra-transistor wells can comprise a first intra-transistor well having the first type conductivity (e.g., a P-well); a second intra-transistor well positioned laterally adjacent to the first intra-transistor well and having a second type conductivity (e.g., an N-well); a third intra-transistor well positioned laterally adjacent to the second intra-transistor well and having the first type conductivity (e.g., another P-well); and a fourth intra-transistor well positioned laterally adjacent to the third intra-transistor well and having the second type conductivity (e.g., another N-well).
- The transistor can further comprise, within the substrate at the top surface, a drain region, a source region, one or more contact regions and a trench isolation structure that electrically isolates these regions. Specifically, the transistor can comprise a drain region within the first intra-transistor well at the top surface of the substrate and a source region within the fourth intra-transistor well at the top surface of the substrate. The drain region and the source region can each have the first type conductivity at a relatively high conductivity level (e.g., a P+drain region and a P+ source region). The transistor can comprise a contact region within the fourth intra-transistor well at the top surface of the substrate. This contact region can have the second type conductivity at a relatively high conductivity level (e.g., an N+ contact region). Optionally, this transistor can further comprise another contact region, having the second type conductivity at a relatively high conductivity level (e.g., another N+ contact region), within the second intra-transistor well at the top surface of the substrate. As mentioned above, the drain region, source region and any contact regions can be electrically isolated by a trench isolation structure.
- The transistor can also comprise an intra-transistor band in the substrate below and in contact with the first intra-transistor well, the second intra-transistor well, the third intra-transistor well and the fourth intra-transistor well. This intra-transistor band can have the first type conductivity (e.g., a P-band).
- The semiconductor structure can further comprise, within the substrate, a first isolation well, a second isolation well and an isolation band. The first isolation well can be positioned laterally around (i.e., can border) the transistor and can have the second type conductivity (e.g., an N-type isolation well). The second isolation well can be positioned laterally between the fourth intra-transistor well and the first isolation well, can have the first type conductivity (e.g., a P-type isolation well) and can extend vertically to the intra-transistor band. The second isolation band can be below and in contact with the first isolation well and the intra-transistor band and can have the second type conductivity (e.g., an N-type isolation band) such that the transistor is electrically isolated from both a lower portion of the substrate and adjacent devices on the substrate.
- In such a semiconductor structure, the transistor will have a fully depleted deep drain drift region located within the intra-transistor band between the second intra-transistor well and the isolation band. This fully depleted drain drift region will ensure that the transistor has a relatively high blocking voltage.
- Also disclosed herein is another semiconductor structure comprising a semiconductor substrate. This semiconductor substrate can have a first type conductivity at a relatively low conductivity level (e.g., a P− substrate).
- The semiconductor structure can further comprise a transistor (e.g., a P-type lateral double-diffused metal oxide semiconductor field effect transistor (PLDMOSFET)) on the substrate. Specifically, the transistor can comprise a plurality of intra-transistor wells within the substrate. These intra-transistor wells can comprise a first intra-transistor well having the first type conductivity (e.g., a P-well) and a second intra-transistor well positioned laterally adjacent to the first intra-transistor well and having a second type conductivity (e.g., an N-well).
- This transistor can further comprise, within the substrate at the top surface, a drain region, a source region, one or more contact regions and a trench isolation region that electrically isolates these regions. Specifically, the transistor can comprise a drain region within the first intra-transistor well at the top surface of the substrate and a source region within the second intra-transistor well at the top surface of the substrate. The drain region and the source region can each have the first type conductivity at a relatively high conductivity level (e.g., a P+ drain region and a P+ source region). The transistor can comprise a contact region within the second intra-transistor well at the top surface of the substrate. This contact region can have the second type conductivity at a relatively high conductivity level (e.g., an N+ contact region). This transistor can also comprise another contact region, having the second type conductivity at a relatively high conductivity level (e.g., another N+ contact region), within the first intra-transistor well at the top surface of the substrate between the drain region and the second intra-transistor well. As mentioned above, the drain region, source region and any contact regions can be electrically isolated by a trench isolation structure.
- The transistor can also comprise an intra-transistor band. This intra-transistor band can be positioned in the substrate below and in contact with the first intra-transistor well and the second intra-transistor well. This intra-transistor band can have the first type conductivity (e.g., a P-band).
- The semiconductor structure can further comprise a first isolation well, a second isolation well, and an isolation band. The first isolation well can be positioned laterally around (i.e., can border) the transistor and can have the second type conductivity (e.g., an N-type isolation well). The second isolation well can be positioned laterally between the second intra-transistor well and the first isolation well, can have the first type conductivity (e.g., a P-type isolation well) and can extend vertically to the intra-transistor band. The isolation band can be below and in contact with the first isolation well and the intra-transistor band and can have the second type conductivity (e.g., an N-type isolation band) such that the transistor is electrically isolated from both a lower portion of the substrate and adjacent devices on the substrate.
- In such a semiconductor structure, the transistor will have a fully depleted deep drain drift region located within the first intra-transistor well and the intra-transistor band between the contact region and the isolation band. This fully depleted drain drift region will ensure that the transistor has a relatively high blocking voltage.
- Also disclosed herein is yet another semiconductor structure comprising a semiconductor substrate. This semiconductor substrate can have with a first type conductivity at a relatively low conductivity level (e.g., a P− substrate).
- The semiconductor structure can further comprise a transistor (e.g., an N-type lateral double-diffused metal oxide semiconductor field effect transistor (NLDMOSFET)) on the substrate. Specifically, the transistor can comprise a plurality of intra-transistor wells within the substrate. These intra-transistor wells can comprise a first intra-transistor well in the substrate and having a second type conductivity (e.g., an N-well); a second intra-transistor well in the substrate within the first intra-transistor well and having the first type conductivity (e.g., a P-well); and a third intra-transistor well positioned laterally adjacent to the first intra-transistor well and having the first type conductivity (e.g., another P-well). In this case, the first intra-transistor well can extend a first depth into the substrate from the top surface, the second intra-transistor well can extend a second depth into the substrate from the top surface and the first depth can be deeper than the second depth (i.e., the second intra-transistor well can be a more shallow well than the first intra-transistor well).
- This transistor can further comprise, within the substrate at the top surface, a drain region, a source region, one or more contact regions, and a trench isolation structure that electrically isolates these regions. Specifically, the transistor can comprise a drain region within the first intra-transistor well at the top surface of the substrate and a source region within the third intra-transistor well at the top surface of the substrate. The drain region and the source region can each have the second type conductivity at a relatively high conductivity level (e.g., a N+ drain region and a N+ source region). The transistor can also comprise a contact region within the third intra-transistor well. This contact region can have the first type conductivity at a relatively high conductivity level (e.g., a P+ contact region). Optionally, this transistor can further comprise another contact region, having the first type conductivity at a relatively high conductivity level (e.g., another P+ contact region), within the second intra-transistor well at the top surface of the substrate. As mentioned above, the drain region, source region and any contact regions can be electrically isolated by a trench isolation structure.
- The semiconductor structure can further comprise, within the substrate, a first isolation band, a first isolation well, a second isolation well and a second isolation band. Specifically, the first isolation band can be positioned below and in contact with the first intra-transistor well. This first isolation band can have the first type conductivity (e.g., a P-type isolation band). The first isolation well can have the second type conductivity (e.g., an N-type isolation well) and can be positioned laterally around (i.e., can border) the transistor. The second isolation well can have the first type conductivity (e.g., a P-type isolation well) and can be positioned laterally between the first isolation well and the first intra-transistor well of the transistor and can extend vertically to the first isolation band. The second isolation band can be below the first isolation well, the first isolation band and the second intra-transistor well of the transistor and can have the second type conductivity (e.g., an N-type isolation band) such that the transistor is electrically isolated from a lower portion of the substrate and adjacent devices on the substrate.
- In such a semiconductor structure, the transistor will have a fully depleted deep drain drift region located within the first intra-transistor well between the second intra-transistor well and the first isolation band. This fully depleted drain drift region will ensure that the transistor has a relatively high blocking voltage.
- Also disclosed herein is yet another semiconductor structure comprising a semiconductor substrate with a first type conductivity at a relatively low conductivity level (e.g., a P− substrate).
- The semiconductor structure can further comprise a transistor (e.g., an N-type lateral double-diffused metal oxide semiconductor field effect transistor (NLDMOSFET)) on the substrate. Specifically, the transistor can comprise a plurality of intra-transistor wells within the substrate. These intra-transistor wells can comprise a first intra-transistor well in the substrate and having a second type conductivity (e.g., an N-well) and a second intra-transistor well in the positioned laterally adjacent to the first intra-transistor well and having the first type conductivity (e.g., a P-well).
- This transistor can further comprise, within the substrate at the top surface, a drain region, a source region, one or more contact regions and a trench isolation region electrically isolating those regions. Specifically, the transistor can further comprise a drain region within the first intra-transistor well at the top surface of the substrate and a source region within the second intra-transistor well at the top surface of the substrate. The drain region and the source region can each have the second type conductivity at a relatively high conductivity level (e.g., a N+ drain region and a N+ source region). The transistor can also comprise a contact region within the second intra-transistor well. This contact region can have the first type conductivity at a relatively high conductivity level (e.g., a P+ contact region). This transistor can also comprise another contact region, having the first type conductivity at a relatively high conductivity level (e.g., another P+ contact region), within the first intra-transistor well at the top surface of the substrate. As mentioned above, the drain region, source region and any contact regions can be electrically isolated by a trench isolation structure.
- The semiconductor structure can further comprise, within the substrate, a first isolation band, a first isolation well, a second isolation well and a second isolation band. Specifically, the first isolation band can be positioned below and in contact with the first intra-transistor well. This first isolation band can have the first type conductivity (e.g., a P-band). The first isolation well can have the second type conductivity (e.g., an N-type isolation well) and can be positioned laterally around (i.e., can border) the transistor. The second isolation well can have the first type conductivity (e.g., a P-type isolation well) and can be positioned laterally between the first isolation well and the first intra-transistor well of the transistor and can extend vertically to the first isolation band. The second isolation band can be below the first isolation well, the first isolation band and the second intra-transistor well of the transistor and can have the second type conductivity (e.g., an N-band) such that the transistor is electrically isolated from a lower portion of the substrate and adjacent devices on the substrate.
- In such a semiconductor structure, the transistor will have a fully depleted deep drain drift region located within the first intra-transistor well between the contact region and the first isolation band. This fully depleted drain drift region will ensure that the transistor has a relatively high blocking voltage.
- The embodiments herein will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawn to scale and in which:
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FIG. 1 is a vertical cross-section diagram illustrating a P-type lateral double-diffused metal oxide semiconductor field effect transistor; -
FIG. 2 is a vertical cross-section diagram illustrating another P-type lateral double-diffused metal oxide semiconductor field effect transistor; -
FIG. 3 is a horizontal cross-section diagram further illustrating the P-type lateral double-diffused metal oxide semiconductor field effect transistor ofFIG. 1 orFIG. 2 ; -
FIG. 4 is a vertical cross-section diagram illustrating yet another P-type lateral double-diffused metal oxide semiconductor field effect transistor; -
FIG. 5 is a horizontal cross-section diagram further illustrating the P-type lateral double-diffused metal oxide semiconductor field effect transistor ofFIG. 4 ; -
FIG. 6 is a vertical cross-section diagram illustrating an N-type lateral double-diffused metal oxide semiconductor field effect transistor; -
FIG. 7 is a vertical cross-section diagram illustrating another N-type lateral double-diffused metal oxide semiconductor field effect transistor; -
FIG. 8 is a horizontal cross-section diagram further illustrating the N-type lateral double-diffused metal oxide semiconductor field effect transistor ofFIG. 6 orFIG. 7 ; -
FIG. 9 is a vertical cross-section diagram illustrating yet another N-type lateral double-diffused metal oxide semiconductor field effect transistor; -
FIG. 10 is a horizontal cross-section diagram further illustrating the N-type lateral double-diffused metal oxide semiconductor field effect transistor ofFIG. 9 ; -
FIG. 11 is a vertical cross-section diagram illustrating an exemplary inverter comprising the transistors ofFIGS. 1 and 6 ; -
FIG. 12 is a vertical cross-section diagram illustrating another exemplary inverter comprising the transistors ofFIGS. 2 and 7 ; -
FIG. 13 is a vertical cross-section diagram illustrating yet another exemplary inverter comprising the transistors ofFIGS. 4 and 9 ; and -
FIG. 14 is a vertical cross-section diagram illustrating two of the transistors ofFIG. 1 stacked. - As mentioned above, typically, a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET), like a conventional MOSFET transistor, comprises a channel region positioned laterally between a source region and a drain region. However, unlike the conventional MOSFET, the LDMOSFET is asymmetrical. Specifically, the drain region of the LDMOSFET is separated from the channel region by a relatively low-doped drain drift region, which provides ballasting resistance so that the LDMOSFET has a relatively high blocking voltage (i.e., a high maximum voltage that can be applied to the transistor). However, as operating voltages and device densities increase, LDMOSFETs with even higher blocking voltages and better transistor-to-substrate and/or transistor-to-transistor isolation are needed to prevent device failures.
- In view of the foregoing, disclosed herein are semiconductor structures. Each semiconductor structure can comprise a substrate and a laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.
- It should be noted that in the semiconductor structures described below, for illustration purposes, the first type conductivity is referred to as being P-type conductivity and the second type conductivity is referred to as being N-type conductivity. However, alternatively, the reverse can be true. That is, the first type conductivity can comprise N-type conductivity and the second type conductivity can comprise P-type conductivity. Those skilled in the art will recognize that different dopants can be used to achieve the different type conductivities and that the dopants may vary depending upon the different semiconductor materials used. For example, a silicon-based semiconductor material having N-type conductivity is typically doped with an N-type dopant (e.g., a Group V dopant, such as arsenic (As), phosphorous (P) or antimony (Sb)), whereas a silicon-based semiconductor material having P-type conductivity is typically doped with a P-type dopant (e.g., a Group III dopant, such as boron (B) or indium (In)). Alternatively, a gallium nitride (GaN)-based semiconductor material having P-type conductivity is typically doped with magnesium (Mg), whereas a gallium nitride (GaN)-based semiconductor material having a N-type conductivity is typically doped with silicon (Si). Those skilled in the art will also recognize that different conductivity levels will depend upon the relative concentration levels of the dopants.
- Referring to
FIGS. 1 and 2 disclosed herein is asemiconductor structure 100 comprising abulk semiconductor substrate 101. For example, thesemiconductor substrate 101 can comprise a bulk silicon substrate or any other bulk semiconductor substrate. Thesemiconductor substrate 101 can have a first type conductivity (e.g., P-type conductivity) at a relatively low conductivity level. For example, thesemiconductor substrate 101 can comprise a P− substrate. - The
semiconductor structure 100 can further comprise atransistor 1A, as inFIG. 1 , or 1B, as inFIG. 2 , on thesemiconductor substrate 101 and, particularly, a P-type lateral double-diffused metal oxide semiconductor field effect transistor (PLDMOSFET) on thesubstrate 101. - Specifically, the
transistor substrate 101. For purposes of this disclosure, an “intra-transistor well” refers to a well (i.e., a dopant implant region), which is an active component of the transistor. These intra-transistor wells can comprise, for example, a firstintra-transistor well 104 having the first type conductivity (e.g., a P-well); a second intra-transistor well 105 positioned laterally adjacent to the firstintra-transistor well 104 and having a second type conductivity (e.g., an N-well); a third intra-transistor well 106 positioned laterally adjacent to the secondintra-transistor well 105 and having the first type conductivity (e.g., another P-well); and a fourthintra-transistor well 107 positioned laterally adjacent to the thirdintra-transistor well 106 and having the second type conductivity (e.g., another N-well). Each of these intra-transistor wells 104-107 can be positioned at thetop surface 120 of thesemiconductor substrate 101 and can extend vertically into thesemiconductor substrate 101 some predetermined depth (e.g., a same predetermined depth 121). - It should be noted that the third intra-transistor well 106 can be physically separated from the fourth
intra-transistor well 107 by aspace 141, as shown. In this case, thespace 141 between the thirdintra-transistor well 106 and fourthintra-transistor well 107 will have the same doping type and conductivity level as thelower portion 191 of the substrate 101 (e.g., P−). Alternatively, the third intra-transistor well 106 can be immediately adjacent to (i.e., can abut) the fourth intra-transistor well 107 (not shown). - The
transistor gate structure 130 on thetop surface 120 of thesubstrate 101. Afirst side 131 of thegate structure 130 can extend laterally over the thirdintra-transistor well 106. Asecond side 132 of thegate structure 130 can extend laterally over the fourthintra-transistor well 107 and can define thechannel region 140 of thetransistor gate structure 130 can comprise a gate dielectric layer (e.g., a gate oxide layer, a high-k gate dielectric layer or other suitable gate dielectric layer) and a gate conductor layer (e.g., a polysilicon gate conductor layer, a metal gate conductor layer, a dual work function gate conductor layer or other suitable gate conductor layer) on the gate dielectric layer. - The
transistor top surface 120 of thesubstrate 101 on either side of thegate structure 130, adrain region 111, asource region 112, various contact regions (e.g., 113 and, optionally, 119) and atrench isolation structure 110 that electrically isolates these regions. - Specifically, the
drain region 111 can be positioned within the first intra-transistor well 104 at thetop surface 120 of thesubstrate 101 adjacent to thefirst side 131 of thegate structure 130 and thesource region 112 can be positioned within the fourthintra-transistor well 107 at thetop surface 120 of thesubstrate 101 adjacent to thesecond side 132 of thegate structure 130. Thedrain region 111 andsource region 112 can be asymmetric with respect to thegate structure 130 and, specifically, thedrain region 111 can be positioned farther from thegate structure 130 than thesource region 112, as shown. Thedrain region 111 and thesource region 112 can each comprise doped regions having the first type conductivity at a relatively high conductivity level (e.g., a P+ drain region and a P+ source region). - Additionally, a contact region 113 (also referred to herein as a body contact region), having the second type conductivity at a relatively high conductivity level (e.g., an N+ contact region), can be positioned within the fourth
intra-transistor well 107 at thetop surface 120 of thesubstrate 101 so as to allow that fourthintra-transistor well 107 to be electrically biased. Within the fourth intra-transistor well, thesource region 112 can be positioned closer to thegate structure 130 than thecontact region 113. Optionally, as shown inFIG. 2 , thetransistor 1B can further comprise acontact region 119, having the second type conductivity at a relatively high conductivity level (e.g., an N+ contact region), within the second intra-transistor well 105 at thetop surface 120 of thesubstrate 101 so as to effectively form a junction field effect transistor. Thus, thecontact region 119 will be closer to thegate structure 130 than thedrain region 111. - In any case, a patterned
trench isolation structure 110 at thetop surface 120 of thesubstrate 101 can electrically isolate thedrain region 111,source region 112, and contact regions (e.g., thecontact region 113 and, if applicable, the contact region 119). Thistrench isolation structure 110 can comprise, for example, a conventional shallow trench isolation (STI) structure) comprising a patterned trench, which is filled with one or more isolation materials (e.g., silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and/or any other suitable isolation material). - The
transistor intra-transistor band 103 within thesubstrate 101. For purposes of this disclosure, an “intra-transistor band” refers to a band (i.e., a buried dopant implant region within the substrate and separated from the top surface by some predetermined distance), which is an active component of the transistor. Theintra-transistor band 103 can be positioned in thesubstrate 101 below and in contact with the firstintra-transistor well 104, the secondintra-transistor well 105, the thirdintra-transistor well 106 and the fourthintra-transistor well 107. Thisintra-transistor band 103 can have the first type conductivity (e.g., a P-band). - The
semiconductor structure 100 can further comprise, within thesubstrate 101, a first isolation well 108, a second isolation well 109 and anisolation band 102. For purposes of this disclosure, an “isolation well” refers to a well (i.e., a dopant implant region) that electrically isolates adjacent devices and/or components thereof. Such isolation wells can be positioned at the top surface of the semiconductor substrate and can extend vertically into the semiconductor substrate some predetermined depth (e.g., the samepredetermined depth 121 as the intra-transistor wells). For purposes of this disclosure, an “isolation band” refers to a band (i.e., a buried dopant implant region within the substrate and separated from the top surface by some predetermined distance), which electrically isolates devices and components thereof from the lower portion of the substrate. - In this case, the first isolation well 108 can be positioned laterally around (i.e., can border) the
transistor FIG. 3 ) and can have the second type conductivity (e.g., an N-type isolation well). The second isolation well 109 can be positioned laterally between the fourthintra-transistor well 107 and the first isolation well 108, can have the first type conductivity (e.g., a P-type isolation well), and can extend vertically to theintra-transistor band 103. Theisolation band 102 can be below and in contact with the first isolation well 108 and theintra-transistor band 103. More specifically, theisolation band 102 can have vertical portion aligned below and in contact with the first isolation well 108. This vertical portion can further be positioned laterally around (i.e., can border) theintra-transistor band 103. Additionally, theisolation band 102 can have a horizontal portion that separates the bottom surface of theintra-transistor band 103 and thelower portion 191 of thesubstrate 101. Thisisolation band 102 can have the second type conductivity (e.g., an N-band). Theisolation band 102 in combination with the first isolation well 108, which also has the second type conductivity, can electrically isolate thetransistor lower portion 191 of thesubstrate 101 and from any adjacent devices (not shown) on thesubstrate 101. - It should be noted that, optionally, the
semiconductor structure 100 can further comprise anadditional contact region 115 that allows the well 108 and, thereby theband 102 to be electrically biased. More specifically, thesemiconductor structure 100 can further comprise acontact region 115, having the second type at a relatively high conductivity level (e.g., an N+ contact region), within the first isolation well 108 at the top surface of thesubstrate 101 so as to allow that isolation well 108 and, thereby theband 102 below to be electrically biased. As with theother contact regions contact region 115 can be electrically isolated by thetrench isolation region 110. - In such a
semiconductor structure 100, thetransistor drain drift region 150 located within theintra-transistor band 103 between the secondintra-transistor well 105 and theisolation band 102. This fully-depleteddrain drift region 150 will ensure that thetransistor transistor isolation band 102 from thelower portion 191 of thesubstrate 101 and from adjacent devices on thesubstrate 101, thetransistor substrate 101 with minimal risk of shorts. - Referring to
FIG. 4 , also disclosed herein is anothersemiconductor structure 200 comprising abulk semiconductor substrate 201. For example, thesemiconductor substrate 201 can comprise a bulk silicon substrate or any other bulk semiconductor substrate. Thesemiconductor substrate 201 can have a first type conductivity (e.g., P-type conductivity) at a relatively low conductivity level. For example, thesemiconductor substrate 201 can comprise a P− substrate. - The
semiconductor structure 200 can further comprise atransistor 2 on thesemiconductor substrate 201 and, particularly, a P-type lateral double-diffused metal oxide semiconductor field effect transistor (PLDMOSFET) on thesubstrate 201. - Specifically, the
transistor 2 can comprise a plurality ofintra-transistor wells substrate 201. For purposes of this disclosure, an “intra-transistor well” refers to a well (i.e., a dopant implant region), which is an active component of the transistor. These intra-transistor wells can comprise a firstintra-transistor well 204 having the first type conductivity (e.g., a P-well) and a second intra-transistor well 207 positioned laterally adjacent to the firstintra-transistor well 204 and having a second type conductivity (e.g., an N-well). Theseintra-transistor wells top surface 220 of thesemiconductor substrate 201 and can extend vertically into thesemiconductor substrate 201 some predetermined depth (e.g., a same predetermined depth 221). - It should be noted that the first
intra-transistor well 204 can be physically separated from the second intra-transistor well 207 by aspace 241, as shown. In this case, thespace 241 between the firstintra-transistor well 204 and secondintra-transistor well 207 will have the same doping type and conductivity level as thelower portion 291 of the substrate 201 (e.g., P−). Alternatively, the firstintra-transistor well 204 can be immediately adjacent to (i.e., can abut) the secondintra-transistor well 207. - The
transistor 2 can further comprise agate structure 230 on thetop surface 220 of thesubstrate 201. Afirst side 231 of thegate structure 230 can extend laterally over the firstintra-transistor well 204. Asecond side 232 of thegate structure 230 can extend laterally over the secondintra-transistor well 207 and can define thechannel region 240 of thetransistor 2. Thegate structure 230 can comprise a gate dielectric layer (e.g., a gate oxide layer, a high-k gate dielectric layer or other suitable gate dielectric layer) and a gate conductor layer (e.g., a polysilicon gate conductor layer, a metal gate conductor layer, a dual work function gate conductor layer or other suitable gate conductor layer) on the gate dielectric layer. - The
transistor 2 can further comprise, at thetop surface 220 of thesubstrate 201 on either side of thegate structure 230, adrain region 211, asource region 212, various contact regions (e.g., 213 and 219) and atrench isolation structure 210 that electrically isolates these regions. - Specifically, the
transistor 2 can further comprise adrain region 211 within the first intra-transistor well 204 at thetop surface 220 of thesubstrate 201 adjacent to thefirst side 231 of thegate structure 230 and asource region 212 within the second intra-transistor well 207 at thetop surface 220 of thesubstrate 201 adjacent to thesecond side 232 of thegate structure 230. Thesource region 212 and drainregion 211 can be asymmetric with respect to thegate structure 230 and, specifically, thedrain region 211 can be positioned farther from thegate structure 230 than thesource region 212, as shown. Thedrain region 211 and thesource region 212 can comprise doped regions having the first type conductivity at a relatively high conductivity level (e.g., a P+ drain region and a P+ source region). - The
transistor 2 can further comprise anintra-transistor band 203 within thesubstrate 201. For purposes of this disclosure, an “intra-transistor band” refers to a band (i.e., a buried dopant implant region within the substrate and separated from the top surface by some predetermined distance) that is an active component of the transistor. Theintra-transistor band 203 can be in thesubstrate 201 below and in contact with the firstintra-transistor well 204 and the secondintra-transistor well 207. Thisintra-transistor band 203 can have the first type conductivity (e.g., a P-band). - Additionally, a contact region 213 (also referred to herein as a body contact region), having the second type conductivity at a relatively high conductivity level (e.g., an N+ contact region), can be positioned within the second intra-transistor well 207 at the
top surface 220 of thesubstrate 201 so as to allow that second intra-transistor well 207 to be electrically biased. Within the second intra-transistor well, thesource region 212 can be positioned closer to thegate structure 230 than thecontact region 213. Thetransistor 2 can further comprise anothercontact region 219, having the second type conductivity at a relatively high conductivity level (e.g., an N+ contact region), within the first intra-transistor well 204 at thetop surface 220 of thesubstrate 201 so as to effectively form a junction field effect transistor. Within the firstintra-transistor well 204, thecontact region 219 can be positioned closer to thegate structure 230 than thedrain region 211. - In any case, a patterned
trench isolation structure 210 at thetop surface 220 of thesubstrate 201 can electrically isolate thedrain region 211,source region 212, andcontact regions trench isolation structure 210 can comprise, for example, a conventional shallow trench isolation (STI) structure) comprising a patterned trench, which is filled with one or more isolation materials (e.g., silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and/or any other suitable isolation material). - The
semiconductor structure 200 can further comprise, within thesubstrate 201, a first isolation well 208, a second isolation well 209 and anisolation band 202. For purposes of this disclosure, an “isolation well refers” to a well (i.e., a dopant implant region) that electrically isolates adjacent devices and/or components thereof. Such isolation wells can be positioned at the top surface of the semiconductor substrate and can extend vertically into the semiconductor substrate some predetermined depth (e.g., the samepredetermined depth 221 as the intra-transistor wells). For purposes of this disclosure, an “isolation band” refers to a band (i.e., a buried dopant implant region within the substrate and separated from the top surface by some predetermined distance), which electrically isolates devices and components thereof from the lower portion of the substrate. - In this case, the first isolation well 208 can be positioned laterally around (i.e., can border) the transistor 2 (see the cross-section diagram of
FIG. 5 ) and can have the second type conductivity (e.g., an N-type isolation well). The second isolation well 209 can be positioned laterally between the secondintra-transistor well 207 and the first isolation well 208, can have the first type conductivity (e.g., a P-type isolation well) and can extend vertically to theintra-transistor band 203. Theisolation band 202 can be below and in contact with the first isolation well 208 and theintra-transistor band 203. More specifically, theisolation band 202 can have vertical portion aligned below and in contact with the first isolation well 208. This vertical portion can further be positioned laterally around (i.e., can border) theintra-transistor band 203. Additionally, theisolation band 202 can have a horizontal portion that separates the bottom surface of theintra-transistor band 203 and thelower portion 291 of thesubstrate 201. Thisisolation band 202 can have the second type conductivity (e.g., an N-band). Theisolation band 202 in combination with the first isolation well 208, which also has the second type conductivity, can electrically isolate thetransistor 2 from thelower portion 291 of thesubstrate 201 and from any adjacent devices (not shown) on thesubstrate 201. - It should be noted that, optionally, the
semiconductor structure 200 can further comprise anadditional contact region 215 that allows the well 208 and, thereby theband 202 to be electrically biased. More specifically, thesemiconductor structure 200 can further comprise acontact region 215, having the second conductivity type at a relatively high conductivity level (e.g., an N+ contact region), within the first isolation well 208 at thetop surface 220 of thesubstrate 201 so as to allow that isolation well 208 and, thereby theband 202 below to be electrically biased. As with theother contact regions contact region 215 can be electrically isolated by thetrench isolation region 210. - In such a
semiconductor structure 200, thetransistor 2 will have a fully-depleted deepdrain drift region 250 located within theintra-transistor band 203 and firstintra-transistor well 204 betweencontact region 219 and theisolation band 202. This fully-depleteddrain drift region 250 will ensure that thetransistor 2 has a relatively high blocking voltage. Furthermore, because thetransistor 2 is electrically isolated by the first isolation well 208 andisolation band 202 from thelower portion 291 of thesubstrate 201 and from adjacent devices on thesubstrate 201, thetransistor 2 can be placed in relatively close proximity to adjacent devices in order to increase device density on thesubstrate 201 with minimal risk of shorts. - Referring to
FIGS. 6 and 7 disclosed herein is yet anothersemiconductor structure 600 comprising abulk semiconductor substrate 601. For example, thesemiconductor substrate 601 can comprise a bulk silicon substrate or any other bulk semiconductor substrate. Thesemiconductor substrate 601 can have a first type conductivity (e.g., P-type conductivity) at a relatively low conductivity level. For example, thesemiconductor substrate 601 can comprise a P− substrate. - The
semiconductor structure 600 can further comprise atransistor 6A, as inFIG. 6 , or 6B, as inFIG. 7 , on thesemiconductor substrate 601 and, particularly, an N-type lateral double-diffused metal oxide semiconductor field effect transistor (NLDMOSFET) on thesubstrate 601. - Specifically, this
transistor substrate 601. For purposes of this disclosure, an “intra-transistor well” refers to a well (i.e., a dopant implant region), which is an active component of the transistor. These intra-transistor wells can comprise a firstintra-transistor well 604 having a second type conductivity (e.g., an N-well); a second intra-transistor well 605 within the firstintra-transistor well 604 and having the first type conductivity (e.g., a P-well); and a third intra-transistor well 607 positioned laterally adjacent to the firstintra-transistor well 604 and having the first type conductivity (e.g., another P-well). In this case, the firstintra-transistor well 604 and the third intra-transistor well 607 can extend afirst depth 621 into thesubstrate 601 from thetop surface 620, the second intra-transistor well 605 can extend asecond depth 622 into thesubstrate 601 from thetop surface 620 and thefirst depth 621 can be deeper than the second depth 622 (i.e., the second intra-transistor 605 well can be a more shallow well than the first and third intra-transistor wells). - It should be noted that the first
intra-transistor well 604 can be physically separated from the third intra-transistor well 607 by aspace 641, as shown. In this case, thespace 641 between the firstintra-transistor well 604 and third intra-transistor well 607 will have the same doping type and conductivity level as thelower portion 691 of the substrate 601 (e.g., P−). Alternatively, the firstintra-transistor well 604 can be immediately adjacent to (i.e., can abut) the third intra-transistor well 607 (not shown). - The transistor 6 can further comprise a
gate structure 630 on thetop surface 620 of thesubstrate 601. Afirst side 631 of thegate structure 630 can extend laterally over the firstintra-transistor well 604. Asecond side 632 of thegate structure 630 can extend laterally over the thirdintra-transistor well 607 and can define thechannel region 640 of the transistor 6. Thegate structure 630 can comprise a gate dielectric layer (e.g., a gate oxide layer, a high-k gate dielectric layer or other suitable gate dielectric layer) and a gate conductor layer (e.g., a polysilicon gate conductor layer, a metal gate conductor layer, a dual work function gate conductor layer or other suitable gate conductor layer) on the gate dielectric layer. - The transistor 6 can further comprise, at the
top surface 620 of thesubstrate 601 on either side of thegate structure 630, adrain region 611, asource region 612, various contact regions (e.g., 613 and, optionally, 619) and atrench isolation structure 610 that electrically isolates these regions. - Specifically, the transistor can comprise a
drain region 611 within the first intra-transistor within the first intra-transistor well 604 at thetop surface 620 of thesubstrate 601 adjacent to thefirst side 631 of thegate structure 630 and asource region 612 within the third intra-transistor well 607 at thetop surface 620 of thesubstrate 601 adjacent to thesecond side 632 of thegate structure 630. Thedrain region 611 andsource region 612 can be asymmetric with respect to thegate structure 630 and, specifically, thedrain region 611 can be positioned farther from thegate structure 630 than thesource region 612, as shown. Thedrain region 611 and thesource region 612 can each have the second type conductivity at a relatively high conductivity level (e.g., a N+ drain region and a N+ source region). - Additionally, a contact region 613 (also referred to herein as a body contact region), having the first conductivity type at a relatively high conductivity level (e.g., a P+ contact region), can be positioned within the third intra-transistor well 607 at the
top surface 620 of thesubstrate 601 so as to allow that third intra-transistor well 607 to be electrically biased. Within the thirdintra-transistor well 607, thesource region 612 can be positioned closer to thegate structure 630 than thecontact region 613. Optionally, as shown inFIG. 7 , thetransistor 6B can further comprise acontact region 619, having the first conductivity type at a relatively high conductivity level (e.g., another P+ contact region), within the second intra-transistor well 605 at thetop surface 620 of thesubstrate 601 so as to effectively form a junction field effect transistor. Within the firstintra-transistor well 604, thecontact region 619 can be positioned closer to thegate structure 630 than thedrain region 611. - In any case, a patterned
trench isolation structure 610 at thetop surface 620 of thesubstrate 601 can electrically isolate thedrain region 611,source region 612, and contact regions (e.g., thecontact region 613 and, if applicable, the contact region 619). Thistrench isolation structure 610 can comprise, for example, a conventional shallow trench isolation (STI) structure) comprising a patterned trench, which is filled with one or more isolation materials (e.g., silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and/or any other suitable isolation material). - The
semiconductor structure 600 can further comprise, within thesubstrate 601, afirst isolation band 603, a first isolation well 608, a second isolation well 609 and asecond isolation band 602. For purposes of this disclosure, an “isolation well” refers to a well (i.e., a dopant implant region) that electrically isolates adjacent devices and/or components thereof. Such isolation wells can be positioned at the top surface of the semiconductor substrate and can extend vertically into the semiconductor substrate some predetermined depth (e.g., the samepredetermined depth 621 as the first and third intra-transistor wells). For purposes of this disclosure, an “isolation band” refers to a band (i.e., a buried dopant implant region within the substrate and separated from the top surface by some predetermined distance), which electrically isolates devices and components thereof from the lower portion of the substrate. - In this case, the
first isolation band 603 can be positioned below and in contact with the firstintra-transistor well 604. Thisfirst isolation band 603 can have the first type conductivity (e.g., a P-type isolation band). The first isolation well 608 can have the second type conductivity (e.g., an N-type isolation well) and can be positioned laterally around (i.e., can border) thetransistor FIG. 8 ). The second isolation well 609 can have the first type conductivity (e.g., a P-type isolation well) and can be positioned laterally between the first isolation well 608 and the first intra-transistor well 604 of thetransistor first isolation band 603. Thesecond isolation band 602 can be below and in contact with the first isolation well 608, thefirst isolation band 603 and the third intra-transistor well 607 of thetransistor second isolation band 602 can have a vertical portion aligned below and in contact with the first isolation well 608. Additionally, thesecond isolation band 602 can have a horizontal portion that separates the bottom surfaces of thefirst isolation band 603 and the third intra-transistor well 607 from thelower portion 691 of thesubstrate 601. Thesecond isolation band 602 can have the second type conductivity (e.g., an N-type isolation band). Thesecond isolation band 602 in combination with the first isolation well 608, which also has the second type conductivity, can electrically isolate thetransistor lower portion 691 of thesubstrate 601 and from any adjacent devices (not shown) on thesubstrate 601. - It should be noted that, optionally, the
semiconductor structure 600 can further compriseadditional contact regions wells bands semiconductor structure 600 can further comprise acontact region 614, having the first conductivity type at a relatively high conductivity level (e.g., a P+ contact region), within the second isolation well 609 at thetop surface 620 of thesubstrate 601 so as to allow that isolation well 609 and, thereby theband 603 below to be electrically biased. Thesemiconductor structure 600 can also further comprise acontact region 615, having the second conductivity type at a relatively high conductivity level (e.g., an N+ contact region), within the first isolation well 608 at thetop surface 620 of thesubstrate 601 so as to allow that isolation well 608 and, thereby theband 602 below to be electrically biased. As with theother contact regions contact regions trench isolation region 610. - In such a
semiconductor structure 600, thetransistor drain drift region 650 located within the firstintra-transistor well 604 between the secondintra-transistor well 605 and thefirst isolation band 603. This fully-depleteddrain drift region 650 will ensure that thetransistor transistor isolation band 602 from thelower portion 691 of thesubstrate 601 and from adjacent devices on thesubstrate 601, thetransistor substrate 601 with minimal risk of shorts. - Referring to
FIG. 9 disclosed herein is yet anothersemiconductor structure 900 comprising abulk semiconductor substrate 901. For example, thesemiconductor substrate 901 can comprise a bulk silicon substrate or any other bulk semiconductor substrate. Thesemiconductor substrate 901 can have a first type conductivity (e.g., P-type conductivity) at a relatively low conductivity level. For example, thesemiconductor substrate 901 can comprise a P− substrate. - The
semiconductor structure 900 can further comprise atransistor 9 on thesemiconductor substrate 901 and, particularly, an N-type lateral double-diffused metal oxide semiconductor field effect transistor (NLDMOSFET) on thesubstrate 901. - Specifically, this
transistor 9 can comprise plurality of intra-transistor wells within thesubstrate 901. For purposes of this disclosure, an “intra-transistor well” refers to a well (i.e., a dopant implant region), which is an active component of the transistor. These intra-transistor wells can comprise a firstintra-transistor well 904 having a second type conductivity (e.g., an N-well) and a second intra-transistor well 907 positioned laterally adjacent to the firstintra-transistor well 904 and having the first type conductivity (e.g., a P-well). Each of theseintra-transistor wells top surface 920 of thesemiconductor substrate 901 and can extend vertically into thesemiconductor substrate 901 some predetermined depth (e.g., a same predetermined depth 921). - It should be noted that the first
intra-transistor well 904 can be physically separated from the second intra-transistor well 907 by aspace 941, as shown. In this case, thespace 941 between the firstintra-transistor well 904 and secondintra-transistor well 907 will have the same doping type and conductivity level as thelower portion 991 of the substrate 901 (e.g., P−). Alternatively, the firstintra-transistor well 904 can be immediately adjacent to (i.e., can abut) the second intra-transistor well 907 (not shown). - The
transistor 9 can further comprise agate structure 930 on thetop surface 920 of thesubstrate 901. Afirst side 931 of thegate structure 930 can extend laterally over the firstintra-transistor well 904. Asecond side 932 of thegate structure 930 can extend laterally over the secondintra-transistor well 907 and can define thechannel region 940 of thetransistor 9. Thegate structure 930 can comprise a gate dielectric layer (e.g., a gate oxide layer, a high-k gate dielectric layer or other suitable gate dielectric layer) and a gate conductor layer (e.g., a polysilicon gate conductor layer, a metal gate conductor layer, a dual work function gate conductor layer or other suitable gate conductor layer) on the gate dielectric layer. - The
transistor 9 can further comprise, at thetop surface 920 of thesubstrate 901 on either side of thegate structure 930, adrain region 911, asource region 612, various contact regions (e.g., 913 and 919) and atrench isolation structure 910 that electrically isolates these regions. - Specifically, the
transistor 9 can comprise adrain region 911 within the first intra-transistor within the first intra-transistor well 904 at thetop surface 920 of thesubstrate 901 adjacent to thefirst side 931 of thegate structure 930 and asource region 912 within the second intra-transistor well 907 at thetop surface 920 of thesubstrate 901 adjacent to thesecond side 932 of thegate structure 930. Thedrain region 911 andsource region 912 can be asymmetric with respect to thegate structure 930 and, specifically, thedrain region 911 can be positioned farther from thegate structure 930 than thesource region 912, as shown. Thedrain region 911 and thesource region 912 can each have the second type conductivity at a relatively high conductivity level (e.g., a N+ drain region and a N+ source region). - Additionally, a contact region 913 (also referred to herein as a body contact region), having the first conductivity type at a relatively high conductivity level (e.g., a P+ contact region), can be positioned within the second intra-transistor well 907 at the
top surface 920 of thesubstrate 901 so as to allow that second intra-transistor well 907 to be electrically biased. Within the second intra-transistor well, thesource region 912 can be positioned closer to thegate structure 930 than thecontact region 913. Thetransistor 9 can further comprise acontact region 919, having the first conductivity type at a relatively high conductivity level (e.g., another P+ contact region), within the first intra-transistor well 905 at thetop surface 920 of thesubstrate 901 so as to effectively form a junction field effect transistor. Within the firstintra-transistor well 904, thecontact region 919 can be positioned closer to thegate structure 930 than thedrain region 911. - In any case, a patterned
trench isolation structure 910 at thetop surface 920 of thesubstrate 901 can electrically isolate thedrain region 911,source region 912, andcontact regions trench isolation structure 910 can comprise, for example, a conventional shallow trench isolation (STI) structure) comprising a patterned trench, which is filled with one or more isolation materials (e.g., silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and/or any other suitable isolation material). - The
semiconductor structure 900 can further comprise, within thesubstrate 901, afirst isolation band 903, a first isolation well 908, a second isolation well 909 and asecond isolation band 902. For purposes of this disclosure, an “isolation well” refers to a well (i.e., a dopant implant region) that electrically isolates adjacent devices and/or components thereof. Such isolation wells can be positioned at the top surface of the semiconductor substrate and can extend vertically into the semiconductor substrate some predetermined depth (e.g., the samepredetermined depth 921 as the first and second intra-transistor wells). For purposes of this disclosure, an “isolation band” refers to a band (i.e., a buried dopant implant region within the substrate and separated from the top surface by some predetermined distance), which electrically isolates devices and components thereof from the lower portion of the substrate. - In this case, the
first isolation band 903 can be positioned below and in contact with the firstintra-transistor well 904. Thisfirst isolation band 903 can have the first type conductivity (e.g., a P-type isolation band). The first isolation well 908 can have the second type conductivity (e.g., an N-type isolation well) and can be positioned laterally around (i.e., can border) the transistor 9 (see the cross-section diagram ofFIG. 10 ). The second isolation well 909 can have the first type conductivity (e.g., a P-type isolation well) and can be positioned laterally between the first isolation well 908 and the first intra-transistor well 904 of thetransistor 9 and can extend vertically to thefirst isolation band 903. Thesecond isolation band 902 can be below and in contact with the first isolation well 908, thefirst isolation band 903 and the second intra-transistor well 907 of thetransistor 9. More specifically, thesecond isolation band 902 can have a vertical portion aligned below and in contact with the first isolation well 608. Additionally, thesecond isolation band 902 can have a horizontal portion that separates the bottom surfaces of thefirst isolation band 903 and the second intra-transistor well 907 from thelower portion 991 of thesubstrate 901. Thesecond isolation band 902 can have the second type conductivity (e.g., an N-type isolation band). Thesecond isolation band 902 in combination with the first isolation well 908, which also has the second type conductivity, can electrically isolate thetransistor 9 from thelower portion 991 of thesubstrate 901 and from any adjacent devices (not shown) on thesubstrate 901. - It should be noted that, optionally, the
semiconductor structure 900 can further compriseadditional contact regions wells bands semiconductor structure 900 can further comprise acontact region 914, having the first conductivity type at a relatively high conductivity level (e.g., a P+ contact region), within the second isolation well 909 at thetop surface 920 of thesubstrate 901 so as to allow that isolation well 909 and, thereby theband 903 below to be electrically biased. Thesemiconductor structure 900 can also further comprise acontact region 915, having the second conductivity type at a relatively high conductivity level (e.g., an N+ contact region), within the first isolation well 908 at thetop surface 920 of thesubstrate 901 so as to allow that isolation well 908 and, thereby theband 902 below to be electrically biased. As with theother contact regions contact regions trench isolation region 910. - In such a
semiconductor structure 900, thetransistor 9 will have a fully depleted deepdrain drift region 950 located within the firstintra-transistor well 904 betweencontact region 919 and thefirst isolation band 903. This fully-depleteddrain drift region 950 will ensure that thetransistor 9 has a relatively high blocking voltage. Furthermore, because thetransistor 9 is electrically isolated by the first isolation well 908 andisolation band 902 from thelower portion 991 of thesubstrate 901 and from adjacent devices on thesubstrate 901, thetransistor 9 can be placed in relatively close proximity to adjacent devices in order to increase device density on thesubstrate 901 with minimal risk of shorts. - Also disclosed herein are semiconductor structures comprising multiple ones of the above-described transistors in either logic circuit (e.g., inverter) configuration or a stacked LDMOSFET configuration.
- For example,
FIG. 11 is a cross-section diagram illustrating asemiconductor structure 1100 wherein thetransistor 1A ofFIGS. 1 and 6A ofFIG. 6 are arranged on thesame substrate 1101 as a logic circuit (e.g., inverter) configuration. That is, thetransistor 1A (e.g., a PLDMOSFET) is positioned laterally adjacent to thetransistor 6A (e.g., an NLDMOSFET) on thesame substrate 1101. It should be noted that in this case thetransistors isolation wells wells transistors transistor lower portion 1191 of thesemiconductor substrate 1101 below byisolation bands isolation bands - Similarly,
FIG. 12 is a cross-section diagram illustrating asemiconductor structure 1200 wherein thetransistor 1B ofFIGS. 2 and 6B ofFIG. 7 are arranged on thesame substrate 1201 as a logic circuit (e.g., inverter) configuration. That is, thetransistor 1B (e.g., a PLDMOSFET) is positioned laterally adjacent to thetransistor 6B (e.g., an NLDMOSFET) on thesame substrate 1201. It should be noted that in this case thetransistors isolation wells wells transistors transistor lower portion 1291 of thesemiconductor substrate 1201 below byisolation bands isolation bands - Similarly,
FIG. 13 is a cross-section diagram illustrating asemiconductor structure 1300 wherein thetransistor 2 ofFIGS. 4 and 9 ofFIG. 9 are arranged on thesame substrate 1301 as a logic circuit (e.g., inverter) configuration. That is, the transistor 2 (e.g., a PLDMOSFET) is positioned laterally adjacent to the transistor 9 (e.g., an NLDMOSFET) on thesame substrate 1301. It should be noted that in this case thetransistors isolation wells wells transistors transistor lower portion 1391 of thesemiconductor substrate 1301 below byisolation bands isolation bands -
FIG. 14 is a cross-section diagram illustrating asemiconductor structure 1400 wherein two oftransistors 1A ofFIG. 1 (e.g., two PDLMOSFETs) are stacked together on thesame substrate 1401. That is, afirst transistor 1A is positioned laterally adjacent to anothertransistor 1A on thesame substrate 1401. It should be noted that in this case two thetransistors 1A can share a fourth intra-transistor well 107 (within which theirrespective source regions 112 are located) as well as thecontact region 113 to that well 107. The twotransistors 1A can be laterally surrounded by a single isolation well 108, having the second type conductivity, as discussed in detail above. Additionally, the twotransistors 1A can be electrically isolated from thelower portion 1491 of thesemiconductor substrate 1401 below by asingle isolation band 102 that extends laterally below both transistors. It should be understood that the other disclosedLDMOSFETs - Those skilled in the art will recognize that the above-described semiconductor structures can be formed using standard complementary metal oxide semiconductor (CMOS) fabrication processes. For example, multiple masked dopant implantation processes can be performed to create, within a bulk semiconductor substrate, the multiple discrete dopant implant regions (i.e., the various wells and bands described) having the desired conductivity type and level and as well as the relative positioning. Additional masked dopant implantation processes can be performed in order to form the source, drain and contact regions described. Alternatively, multiple in-situ doped epitaxial growth processes can be performed in order to form the source, drain and contact regions described.
- Therefore, disclosed above are semiconductor structures. Each semiconductor structure can comprise a substrate and a laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
- The descriptions of the various embodiments of the present invention have been presented above for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (20)
1. A semiconductor structure comprising:
a semiconductor substrate having a top surface and a first type conductivity;
a transistor on said semiconductor substrate, said transistor comprising:
a first intra-transistor well in said semiconductor substrate and having a second type conductivity;
a second intra-transistor well in said semiconductor substrate within said first intra-transistor well and having said first type conductivity, said first intra-transistor well extending deeper into said semiconductor substrate than said second intra-transistor well;
a third intra-transistor well in said semiconductor substrate, positioned laterally adjacent to said first intra-transistor well and having said first type conductivity, said first intra-transistor well and said third intra-transistor well extending a same depth into said semiconductor substrate;
a drain region within said first intra-transistor well at said top surface of said semiconductor substrate; and,
a source region within said third intra-transistor well at said top surface of said semiconductor substrate, said drain region and said source region having said second type conductivity;
a first isolation band in said semiconductor substrate below and in contact with said first intra-transistor well, said first isolation band having said first type conductivity;
a first isolation well positioned laterally around said transistor and having said second type conductivity;
a second isolation well positioned laterally between said first intra-transistor well and said first isolation well and extending vertically to said first isolation band, said second isolation well having said first type conductivity; and
a second isolation band in said semiconductor substrate and having said second type conductivity, said second isolation band being below said first isolation well, said first isolation band and said second intra-transistor well such that said transistor is electrically isolated from a lower portion of said semiconductor substrate,
said first intra-transistor well having a drain drift region between said second intra-transistor well and said first isolation band.
2. The semiconductor structure of claim 1 , said drain drift region being fully depleted.
3. The semiconductor structure of claim 1 , further comprising a gate structure on said top surface closer to said source region than said drain region, said gate structure having a first side above said first intra-transistor well and a second side above said third intra-transistor well.
4. The semiconductor structure of claim 1 , said third intra-transistor well being immediately adjacent to said first intra-transistor well.
5. The semiconductor structure of claim 1 , said third intra-transistor well being physically separated from said first intra-transistor well.
6. The semiconductor structure of claim 1 , further comprising a contact region within said second intra-transistor well at said top surface of said semiconductor substrate, said contact region having said first type conductivity.
7. The semiconductor structure of claim 1 , said transistor comprising a N-type transistor and said semiconductor structure further comprising a P-type transistor on said semiconductor substrate positioned laterally adjacent to said first isolation well, said second isolation band extending laterally below said P-type transistor.
8. A semiconductor structure comprising:
a semiconductor substrate having a top surface and a first type conductivity;
a transistor on said semiconductor substrate, said transistor comprising:
a first intra-transistor well in said semiconductor substrate and having a second type conductivity;
a second intra-transistor well in said semiconductor substrate within said first intra-transistor well and having said first type conductivity, said first intra-transistor well extending deeper into said semiconductor substrate than said second intra-transistor well;
a third intra-transistor well in said semiconductor substrate, positioned laterally adjacent to said first intra-transistor well and having said first type conductivity, said first intra-transistor well and said third intra-transistor well being physically separated and extending a same depth into said semiconductor substrate;
a drain region within said first intra-transistor well at said top surface of said semiconductor substrate; and,
a source region within said third intra-transistor well at said top surface of said semiconductor substrate, said drain region and said source region having said second type conductivity;
a first isolation band in said semiconductor substrate below and in contact with said first intra-transistor well, said first isolation band having said first type conductivity;
a first isolation well positioned laterally around said transistor and having said second type conductivity;
a second isolation well positioned laterally between said first intra-transistor well and said first isolation well and extending vertically to said first isolation band, said second isolation well having said first type conductivity; and
a second isolation band in said semiconductor substrate and having said second type conductivity, said second isolation band being below said first isolation well, said first isolation band and said second intra-transistor well such that said transistor is electrically isolated from a lower portion of said semiconductor substrate,
said first intra-transistor well having a drain drift region between said second intra-transistor well and said first isolation band.
9. The semiconductor structure of claim 8 , said drain drift region being fully depleted.
10. The semiconductor structure of claim 8 , further comprising a gate structure on said top surface closer to said source region than said drain region, said gate structure having a first side above said first intra-transistor well and a second side above said third intra-transistor well.
11. The semiconductor structure of claim 10 , said gate structure being aligned above a space between said first intra-transistor well and said third intra-transistor well, said space having a same conductivity type and level as a lower portion of said semiconductor substrate below said second isolation band.
12. The semiconductor structure of claim 8 , further comprising a contact region within said second intra-transistor well at said top surface of said semiconductor substrate, said contact region having said first type conductivity.
13. The semiconductor structure of claim 8 , said transistor comprising a N-type transistor and said semiconductor structure further comprising a P-type transistor on said semiconductor substrate positioned laterally adjacent to said first isolation well, said second isolation band extending laterally below said P-type transistor.
14. A semiconductor structure comprising:
a semiconductor substrate having a top surface and a first type conductivity;
a transistor on said semiconductor substrate, said transistor comprising:
a first intra-transistor well in said semiconductor substrate and having a second type conductivity;
a second intra-transistor well in said semiconductor substrate, positioned laterally adjacent to said first intra-transistor well and having said first type conductivity, said first intra-transistor well and said second intra-transistor well extending a same depth into said semiconductor substrate;
a drain region within said first intra-transistor well at said top surface of said semiconductor substrate;
a source region within said second intra-transistor well at said top surface of said semiconductor substrate, said drain region and said source region having said second type conductivity; and,
a contact region within said first intra-transistor well at said top surface of said semiconductor substrate between said drain region and said second intra-transistor well, said contact region having said first type conductivity;
a first isolation band in said semiconductor substrate below and in contact with said first intra-transistor well, said first isolation band having said first type conductivity;
a first isolation well positioned laterally around said transistor and having said second type conductivity;
a second isolation well positioned laterally between said first intra-transistor well and said first isolation well and extending vertically to said first isolation band, said second isolation well having said first type conductivity; and
a second isolation band in said semiconductor substrate and having said second type conductivity, said second isolation band being below said first isolation well, said first isolation band and said second intra-transistor well such that said transistor is electrically isolated from a lower portion of said semiconductor substrate,
said first intra-transistor well having a drain drift region between said contact region and said first isolation band.
15. The semiconductor structure of claim 14 , said drain drift region being fully depleted.
16. The semiconductor structure of claim 14 , further comprising a gate structure on said top surface closer to said source region than said drain region, said gate structure having a first side above said first intra-transistor well and a second side above said second intra-transistor well.
17. The semiconductor structure of claim 14 , said first intra-transistor well being immediately adjacent to said second intra-transistor well.
18. The semiconductor structure of claim 14 , said first intra-transistor well being physically separated from said second intra-transistor well.
19. The semiconductor structure of claim 18 , further comprising a gate structure aligned above a space between said first intra-transistor and said second intra-transistor well, said space having a same conductivity type and level as a lower portion of said semiconductor substrate below said second isolation band.
20. The semiconductor structure of claim 14 , said transistor comprising an N-type transistor and said semiconductor structure further comprising a P-type transistor on said semiconductor substrate positioned laterally adjacent to said first isolation well, said second isolation band extending laterally below said P-type transistor.
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US15/067,307 US20160197080A1 (en) | 2013-08-06 | 2016-03-11 | High voltage lateral double-diffused metal oxide semiconductor field effect transistor (ldmosfet) having a deep fully depleted drain drift region |
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US13/959,777 US9059278B2 (en) | 2013-08-06 | 2013-08-06 | High voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) having a deep fully depleted drain drift region |
US14/672,865 US9349732B2 (en) | 2013-08-06 | 2015-03-30 | High voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) having a deep fully depleted drain drift region |
US15/067,307 US20160197080A1 (en) | 2013-08-06 | 2016-03-11 | High voltage lateral double-diffused metal oxide semiconductor field effect transistor (ldmosfet) having a deep fully depleted drain drift region |
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US14/672,865 Expired - Fee Related US9349732B2 (en) | 2013-08-06 | 2015-03-30 | High voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) having a deep fully depleted drain drift region |
US15/067,307 Abandoned US20160197080A1 (en) | 2013-08-06 | 2016-03-11 | High voltage lateral double-diffused metal oxide semiconductor field effect transistor (ldmosfet) having a deep fully depleted drain drift region |
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US14/672,865 Expired - Fee Related US9349732B2 (en) | 2013-08-06 | 2015-03-30 | High voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) having a deep fully depleted drain drift region |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10756187B1 (en) | 2019-03-28 | 2020-08-25 | Texas Instruments Incorporated | Extended drain MOS with dual well isolation |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10192863B2 (en) | 2014-03-21 | 2019-01-29 | Texas Instruments Incorporated | Series connected ESD protection circuit |
CN107146814B (en) * | 2016-03-01 | 2020-09-11 | 世界先进积体电路股份有限公司 | High voltage semiconductor device and method for manufacturing the same |
US10256340B2 (en) | 2016-04-28 | 2019-04-09 | Vanguard International Semiconductor Corporation | High-voltage semiconductor device and method for manufacturing the same |
EP3261126A1 (en) * | 2016-06-22 | 2017-12-27 | Vanguard International Semiconductor Corporation | High-voltage semiconductor device and method for manufacturing the same |
CN107634056B (en) * | 2016-07-07 | 2021-06-29 | 联华电子股份有限公司 | Semiconductor device and method of forming the same |
CN112968060B (en) * | 2019-11-27 | 2024-08-13 | 上海积塔半导体有限公司 | Full isolation based on BCD process LDNMOS (Low-Density NMOS) manufacturing method and chip |
US11444076B2 (en) * | 2020-08-03 | 2022-09-13 | Globalfoundries U.S. Inc. | Integrated circuit structure with avalanche junction to doped semiconductor over semiconductor well |
KR20220094544A (en) * | 2020-12-29 | 2022-07-06 | 삼성전자주식회사 | Semiconductor device, nonvolatile memory device including the same, electronic system including the same, and method for fabricating the same |
CN114975574A (en) * | 2021-02-19 | 2022-08-30 | 联华电子股份有限公司 | High voltage semiconductor device |
Family Cites Families (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5156989A (en) * | 1988-11-08 | 1992-10-20 | Siliconix, Incorporated | Complementary, isolated DMOS IC technology |
US5146298A (en) | 1991-08-16 | 1992-09-08 | Eklund Klas H | Device which functions as a lateral double-diffused insulated gate field effect transistor or as a bipolar transistor |
US5286995A (en) | 1992-07-14 | 1994-02-15 | Texas Instruments Incorporated | Isolated resurf LDMOS devices for multiple outputs on one die |
US6729886B2 (en) | 2002-06-11 | 2004-05-04 | Texas Instruments Incorporated | Method of fabricating a drain isolated LDMOS device |
US7667268B2 (en) | 2002-08-14 | 2010-02-23 | Advanced Analogic Technologies, Inc. | Isolated transistor |
US6750489B1 (en) * | 2002-10-25 | 2004-06-15 | Foveon, Inc. | Isolated high voltage PMOS transistor |
US7141455B2 (en) | 2002-11-25 | 2006-11-28 | Texas Instruments Incorporated | Method to manufacture LDMOS transistors with improved threshold voltage control |
US7087973B2 (en) | 2003-04-01 | 2006-08-08 | Micrel, Incorporated | Ballast resistors for transistor devices |
US6876035B2 (en) | 2003-05-06 | 2005-04-05 | International Business Machines Corporation | High voltage N-LDMOS transistors having shallow trench isolation region |
US7023050B2 (en) * | 2003-07-11 | 2006-04-04 | Salama C Andre T | Super junction / resurf LDMOST (SJR-LDMOST) |
US6903421B1 (en) | 2004-01-16 | 2005-06-07 | System General Corp. | Isolated high-voltage LDMOS transistor having a split well structure |
US6995428B2 (en) | 2004-02-24 | 2006-02-07 | System General Corp. | High voltage LDMOS transistor having an isolated structure |
US7224025B2 (en) | 2004-08-03 | 2007-05-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Isolated LDMOS IC technology |
US7122876B2 (en) | 2004-08-11 | 2006-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Isolation-region configuration for integrated-circuit transistor |
US7368786B2 (en) * | 2005-03-11 | 2008-05-06 | Freescale Semiconductor, Inc. | Process insensitive ESD protection device |
US7372104B2 (en) | 2005-12-12 | 2008-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage CMOS devices |
DE102006022105B4 (en) * | 2006-05-11 | 2012-03-08 | Infineon Technologies Ag | ESD protection element and ESD protection device for use in an electrical circuit |
US7355224B2 (en) | 2006-06-16 | 2008-04-08 | Fairchild Semiconductor Corporation | High voltage LDMOS |
US7538396B2 (en) * | 2007-01-19 | 2009-05-26 | Episil Technologies Inc. | Semiconductor device and complementary metal-oxide-semiconductor field effect transistor |
US7737526B2 (en) * | 2007-03-28 | 2010-06-15 | Advanced Analogic Technologies, Inc. | Isolated trench MOSFET in epi-less semiconductor sustrate |
US7671423B2 (en) | 2008-01-10 | 2010-03-02 | International Business Machines Corporation | Resistor ballasted transistors |
US7868423B2 (en) * | 2008-11-12 | 2011-01-11 | International Business Machines Corporation | Optimized device isolation |
US9142671B2 (en) | 2009-10-30 | 2015-09-22 | Vanguard International Semiconductor Corporation | Lateral double-diffused metal oxide semiconductor |
KR101128716B1 (en) | 2009-11-17 | 2012-03-23 | 매그나칩 반도체 유한회사 | Semiconductor device |
CN102130168B (en) | 2010-01-20 | 2013-04-24 | 上海华虹Nec电子有限公司 | Isolated LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof |
US8288235B2 (en) * | 2010-10-20 | 2012-10-16 | Globalfoundries Singapore Pte. Ltd. | Self-aligned body fully isolated device |
CN102456578B (en) | 2010-11-03 | 2013-09-04 | 凹凸电子(武汉)有限公司 | High-voltage transistor and manufacturing method thereof |
CN102569392B (en) | 2010-12-27 | 2014-07-02 | 中芯国际集成电路制造(北京)有限公司 | Laterally diffused metal oxide semiconductor (LDMOS) transistor, layout method and manufacture method |
TWI478336B (en) | 2011-05-06 | 2015-03-21 | Episil Technologies Inc | Resurf structure and ldmos device |
US8541862B2 (en) * | 2011-11-30 | 2013-09-24 | Freescale Semiconductor, Inc. | Semiconductor device with self-biased isolation |
US9024380B2 (en) * | 2012-06-21 | 2015-05-05 | Freescale Semiconductor, Inc. | Semiconductor device with floating RESURF region |
US20140001546A1 (en) * | 2012-06-29 | 2014-01-02 | Hubert M. Bode | Semiconductor device and driver circuit with a current carrying region and isolation structure interconnected through a resistor circuit, and method of manufacture thereof |
-
2013
- 2013-08-06 US US13/959,777 patent/US9059278B2/en not_active Expired - Fee Related
-
2015
- 2015-03-30 US US14/672,865 patent/US9349732B2/en not_active Expired - Fee Related
-
2016
- 2016-03-11 US US15/067,307 patent/US20160197080A1/en not_active Abandoned
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10756187B1 (en) | 2019-03-28 | 2020-08-25 | Texas Instruments Incorporated | Extended drain MOS with dual well isolation |
US11387323B2 (en) | 2019-03-28 | 2022-07-12 | Texas Instruments Incorporated | Extended drain MOS with dual well isolation |
Also Published As
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US9349732B2 (en) | 2016-05-24 |
US20150041890A1 (en) | 2015-02-12 |
US20150206880A1 (en) | 2015-07-23 |
US9059278B2 (en) | 2015-06-16 |
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