US20150249128A1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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US20150249128A1
US20150249128A1 US14/715,945 US201514715945A US2015249128A1 US 20150249128 A1 US20150249128 A1 US 20150249128A1 US 201514715945 A US201514715945 A US 201514715945A US 2015249128 A1 US2015249128 A1 US 2015249128A1
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layer
mosfet
semiconductor layer
oxide film
semiconductor device
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Jun Tamura
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a semiconductor device and its manufacturing method, in particular to a semiconductor device in which a plurality of types of elements are provided in a mixed manner and its manufacturing method.
  • silicon MOSFETs Metal-Oxide-Semiconductor Field-Effect Transistors
  • SOI Silicon on Insulator
  • SOS Silicon on Sapphire
  • a transmission loss, a harmonic distortion, and an inter-modulation distortion (IMD) are some examples of the important characteristics that indicate the performance of a high-frequency switch. These characteristics can be improved by reducing the CR product that is the product of the parasitic capacitance C and the on-resistance R of the MOSFET.
  • FIG. 5 is a cross section showing a structure of a typical semiconductor device 300 in which MOSFETs are formed on an SOI substrate.
  • the SOI substrate includes a p-type silicon substrate 314 .
  • the silicon substrate 314 includes a first region 310 and a second region 312 .
  • a high voltage transistor 313 is formed in the first region 310 .
  • Other examples of the semiconductor element that can be formed in the first region 310 include a vertical bipolar transistor.
  • a MOS field-effect transistor 315 having an SOI structure is formed in the second region 312 .
  • Examples of the circuit that can be formed in the second region 312 include a circuit for which a high-speed operation or low power consumption is necessary (for example, a circuit used in a portable information device or the like).
  • the high voltage transistor 313 includes a gate electrode 340 , source/drain 334 a and 336 a , and source/drain offsets 334 b and 336 b .
  • a p-type well 316 is formed in the silicon substrate 314 in the first region 310 .
  • a gate oxide film 338 is formed on the well 316 .
  • the thickness of the gate oxide film 338 is, for example, 40 to 100 nm.
  • Offset LOCOS oxide films 322 and 324 are formed above the well 316 so as to sandwich the gate oxide film 338 therebetween.
  • the gate electrode 340 is formed on the gate oxide film 338 .
  • One end of the gate electrode 340 is located on the offset LOCOS oxide film 322 .
  • the other end of the gate electrode 340 is located on the offset LOCOS oxide film 324 .
  • An n-type source/drain offset 334 b is formed in the well 316 beneath the offset LOCOS oxide film 322 .
  • An n-type source/drain 334 a is formed in the well 316 .
  • the n-type source/drain 334 a is located beside the source/drain offset 334 b .
  • An n-type source/drain offset 336 b is formed in the well 316 beneath the offset LOCOS oxide film 324 .
  • An n-type source/drain 336 a is formed in the well 316 .
  • the n-type source/drain 336 a is located beside the source/drain offset 336 b.
  • An element separation LOCOS oxide film 326 is formed at one end of the well 316 , and an element separation LOCOS oxide film 320 is formed at the other end of the well 316 .
  • a p-type channel stopper region 330 is formed in the well 316 beneath the element separation LOCOS oxide film 326 .
  • a p-type channel stopper region 332 is formed in the well 316 beneath the element separation LOCOS oxide film 320 .
  • An inter-layer insulating film 350 is formed above the silicon substrate 314 so as to cover the gate electrode 340 .
  • a through hole 342 for exposing the source/drain 334 a is formed in the inter-layer insulating film 350 .
  • An aluminum line 346 is formed on the inter-layer insulating film 350 .
  • the aluminum line 346 is also formed inside the through hole 342 and electrically connected to the source/drain 334 a .
  • a through hole 344 for exposing the source/drain 336 a is formed in the inter-layer insulating film 350 .
  • An aluminum line 348 is formed on the inter-layer insulating film 350 .
  • the aluminum line 348 is also formed inside the through hole 344 and electrically connected to the source/drain 336 a.
  • the MOS field-effect transistor 315 includes a gate electrode 360 and source/drain 354 and 356 .
  • a buried oxide film 318 is formed on the silicon substrate 314 in the second region 312 .
  • a silicon single-crystal layer is formed on the buried oxide film 318 .
  • a p-type body region 352 and n-type source/drain 354 and 356 are formed in this silicon single-crystal layer.
  • Element separation LOCOS oxide films 326 and 328 are formed on the buried oxide film 318 .
  • the MOS field-effect transistor 315 is insulated and separated from other elements by the element separation LOCOS oxide films 326 and 328 .
  • a gate oxide film 358 is formed on the body region 352 .
  • the thickness of the gate oxide film 358 is, for example, 3 to 10 nm.
  • An inter-layer insulating film 350 is formed above the silicon substrate 314 so as to cover the gate electrode 360 .
  • a through hole 362 for exposing the source/drain 354 is formed in the inter-layer insulating film 350 .
  • An aluminum line 366 is formed on the inter-layer insulating film 350 . The aluminum line 366 is also formed inside the through hole 362 and electrically connected to the source/drain 354 .
  • a through hole 364 for exposing the source/drain 356 is formed in the inter-layer insulating film 350 .
  • An aluminum line 368 is formed on the inter-layer insulating film 350 . The aluminum line 368 is also formed inside the through hole 364 and electrically connected to the source/drain 356 .
  • the semiconductor device 300 it is possible in the semiconductor device 300 to form both a high voltage MOSFET requiring a deep diffusion layer and a MOSFET having an SOI structure in the same substrate.
  • Patent literature 2 a drive circuit capable of controlling a slew rate with ease while preventing the increase in the circuit size has been proposed. Further, semiconductor devices of similar types have been disclosed (Patent literatures 3 and 4).
  • Patent literature 1 Japanese Unexamined Patent Application Publication No. 2001-7219
  • Patent literature 2 Japanese Unexamined Patent Application Publication No. 8-102498
  • Patent literature 2 Japanese Unexamined Patent Application Publication No. 2008-227084
  • Patent literature 4 Japanese Unexamined Patent Application Publication No. 2007-201240
  • the inventor has found that there is the following problem in the above-described semiconductor device.
  • a MOSFET having an SOI structure is used for reducing the parasitic capacitance and/or for high frequency use, it is required to suppress the effects caused by the support substrate. Therefore, the buried oxide film (BOX) layer needs to be formed with a large thickness.
  • a MOSFET having a thick buried oxide film layer is manufactured, a high difference in height is generated between the combined structure of the SOI substrate and the BOX layer and the support substrate as in the case of the semiconductor device 300 shown in FIG. 5 . As a result, the focus is deviated in the lithography process due to the difference in height, and thereby deteriorating the accuracy in dimensions of the device.
  • a semiconductor device includes: a first MOSFET formed on a high-resistance substrate; and a second MOSFET that is monolithic-integrated with the first MOSFET on the high-resistance substrate, in which the first MOSFET includes: a first semiconductor layer formed on the high-resistance substrate; and a second semiconductor layer formed above the first semiconductor layer, the second semiconductor layer serving as a well layer of the first MOSFET, and the second MOSFET includes: a first insulating layer formed on the high-resistance substrate, first insulating layer being sandwiched between two trenches and thus having a mesa-shape in its upper part, an upper surface of the mesa-shape being positioned at the same height as the first semiconductor layer; a second insulating layer formed on the mesa-shape of the first insulating layer; and a third semiconductor layer formed on the second insulating layer, the third semiconductor layer serving as a well layer of the second MOSFET
  • a semiconductor device includes: a first MOSFET formed on a high-resistance substrate; and a second MOSFET that is monolithic-integrated with the first MOSFET on the high-resistance substrate, in which the first MOSFET includes: a first semiconductor layer formed on the high-resistance substrate; and a second semiconductor layer formed above the first semiconductor layer, the second semiconductor layer serving as a well layer of the first MOSFET, and the second MOSFET includes: a first insulating layer formed on the high-resistance substrate, the first insulating layer having a mesa-shape in its upper part, the mesa-shape being formed by forming trenches in the first semiconductor layer and then performing oxidation treatment from a side and a bottom of the trenches and thereby being sandwiched between two trenches: a second insulating layer formed on the mesa-shape of the first insulating layer; and a third semiconductor layer formed on the second insulating layer
  • a manufacturing method of a semiconductor device includes: forming a first semiconductor layer on the high-resistance substrate; forming a second insulating layer on the first semiconductor layer; forming a third semiconductor layer on the second insulating layer, the third semiconductor layer serving as a well layer of a second MOSFET; removing the second insulating layer and the third semiconductor layer in a first region and forming an opening in the second insulating layer and the third semiconductor layer in a second region; forming trenches by etching the first semiconductor layer in the opening formed in the second insulating layer and the third semiconductor layer in the second region, and thereby forming a mesa-shape sandwiched between two trenches in the the first semiconductor layer located below the second insulating layer and the third semiconductor layer; forming a first insulating layer by performing oxidation treatment from a side and a bottom of the trenches, the first insulating layer being sandwiched between two trenches and thus having a mesa-shap
  • a semiconductor device and its manufacturing method in which a transistor to be formed on an insulating layer can be suitably monolithic-integrated.
  • FIG. 1 is a cross section schematically showing a structure of a semiconductor device 100 according to a first embodiment
  • FIG. 2A is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment
  • FIG. 2B is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment
  • FIG. 2C is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment
  • FIG. 2D is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment
  • FIG. 2E is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment
  • FIG. 2F is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment
  • FIG. 2G is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment
  • FIG. 2H is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment
  • FIG. 2I is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment
  • FIG. 2J is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment
  • FIG. 2K is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment
  • FIG. 2L is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment
  • FIG. 2M is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment
  • FIG. 2N is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment
  • FIG. 2O is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment
  • FIG. 2P is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment
  • FIG. 3 is a cross section schematically showing a manufacturing method of a semiconductor device 200 according to a second embodiment
  • FIG. 4A is a cross section schematically showing a manufacturing method of a substrate Sub 2 of a semiconductor device 200 according to a second embodiment
  • FIG. 4B is a cross section schematically showing a manufacturing method of a substrate Sub 2 of a semiconductor device 200 according to a second embodiment.
  • FIG. 5 is a cross section schematically showing a semiconductor device 300 .
  • FIG. 1 is a cross section schematically showing a structure of a semiconductor device 100 according to the first embodiment.
  • the semiconductor device 100 includes a logic circuit region 101 and a switch circuit region 102 that are monolithic-integrated on a high-resistance substrate 1 .
  • a logic MOSFET 101 a is formed in the logic circuit region 101 .
  • Switch MOSFETs 102 a and 102 b are formed in the switch circuit region 102 .
  • an epitaxial layer 2 is formed on the high-resistance substrate 1 .
  • LOCOS oxide films 6 a which are insulating layers, are formed above the epitaxial layer 2 .
  • the logic MOSFET 101 a is formed on the well layer 8 . Note that the part of the epitaxial layer 2 on which no well layer 8 is formed and the LOCOS oxide films 6 a are covered by a gate oxide film 9 a.
  • a structure of the logic MOSFET 101 a is explained.
  • Two n-type diffusion layers 12 a are formed in the upper part of the well layer 8 .
  • the two diffusion layers 12 a serve as the source and the drain, respectively, of the logic MOSFET 101 a .
  • a gate oxide film 9 a which is an insulating film, is formed between the two diffusion layers 12 a .
  • the gate oxide film 9 a is formed between the well layer 8 and the gate electrode 10 a .
  • the gate electrode 10 a is made of, for example, polysilicon, and the gate oxide film 9 a is composed of a silicon oxide film.
  • a silicide 13 a is formed on the gate oxide film 10 a .
  • Silicides 13 b are formed on the diffusion layers 12 a .
  • the sidewall of the gate oxide film 10 a is covered by a sidewall 11 .
  • an inter-layer insulating film 14 which covers the logic MOSFET 101 a , is formed.
  • a contact hole is formed in the inter-layer insulating film 14 above each of the silicides 13 a and 13 b.
  • an LOCOS oxide film 6 b which is an insulating layer, is formed on the high-resistance substrate 1 .
  • Trenches 5 are formed in the LOCOS oxide film 6 b .
  • an upper part of the LOCOS oxide film, which is sandwiched between the trenches 5 has a mesa-shape.
  • the trenches 5 are filled with an oxide film 7 .
  • a structure of the switch MOSFET 102 a is explained.
  • a buried oxide film 3 (thickness of 0.1 to 0.4 ⁇ m) and an SOI layer 4 (thickness no greater than 0.1 ⁇ m) are formed on the LOCOS oxide film 6 b .
  • the buried oxide film 3 which is an insulating layer, is made of, for example, silicon oxide, and the SOI layer 4 is made of, for example, silicon.
  • Diffusion layers 12 b are formed in the upper part of the SOI layer 4 .
  • the two diffusion layers 12 b serve as the source and the drain, respectively, of the switch MOSFET 102 a .
  • a gate oxide film 9 b which is an insulating film, is formed between the upper surface of the SOI layer 4 and a gate electrode 10 b .
  • the gate electrode 10 b is made of, for example, polysilicon, and the gate oxide film 9 b is made of silicon oxide.
  • a silicide 13 c is formed on the gate oxide film 10 b .
  • Silicides 13 d are formed on the diffusion layers 12 b .
  • the sidewall of the gate electrode 10 b is covered by a sidewall 11 .
  • an inter-layer insulating film 14 which covers the switch MOSFET 102 a , is formed.
  • a contact hole is formed in the inter-layer insulating film 14 above each of the silicides 13 c and 13 d . Note that the structure of a switch MOSFET 102 b is similar to that of the switch MOSFET 102 a , and therefore its explanation is omitted.
  • the logic circuit region 101 corresponds to the first region and the switch circuit region 102 corresponds to the second region.
  • the logic MOSFET 101 a corresponds to the first MOSFET and the switch MOSFETs 102 a and 102 b correspond to the second MOSFET.
  • the epitaxial layer 2 , the well layer 8 , the SOI layer 4 , and an interface carrier suppression layer 15 correspond to the first to fourth semiconductor layers respectively.
  • the LOCOS oxide film 6 b and the buried oxide film 3 correspond to the first and second oxide films respectively.
  • the gate oxide films 9 a and 9 b correspond to the first and second gate insulating films respectively.
  • the diffusion layers 12 a correspond to the first and second diffusion layers.
  • the diffusion layers 12 b correspond to the third and fourth diffusion layers.
  • the LOCOS oxide films 6 a correspond to the first and second element separations.
  • FIGS. 2A to 2P are cross sections schematically showing a manufacturing method of the semiconductor device 100 .
  • an epitaxial layer 2 is formed on a high-resistance substrate 1 by, for example, MOCVD (Metal Organic Chemical Vapor Deposition) or the like.
  • MOCVD Metal Organic Chemical Vapor Deposition
  • a buried oxide film 3 and an SOI layer 4 are formed by wafer bonding using a smart-cut method, and thereby manufacturing an SOI substrate ( FIG. 2A ).
  • a photoresist 31 is formed by photo lithography.
  • the photoresist 31 has openings in the switch circuit region 102 . Further, no photoresist 31 is formed in the logic circuit region 101 ( FIG. 2B ). Then, dry-etching is performed by using the photoresist 31 as a mask and the buried oxide film 3 and the SOI layer 4 are thereby removed. After the etching is finished, the photoresist 31 is removed. Note that the width of the remaining buried oxide film 3 and the SOI layer 4 is no greater than 0.6 ⁇ m ( FIG. 2C ).
  • an oxide film 21 and a nitride film 22 which are used as masks in subsequent processes, are formed in the logic circuit region 101 and the switch circuit region 102 .
  • a silicon oxide can be used for the oxide film 21 and a silicon nitride can be used for the nitride film 22 .
  • Each of the oxide film 21 and the nitride film 22 can be formed by, for example, a plasma CVD method ( FIG. 2D ).
  • a mask pattern used for LOCOS oxide film formation is formed. Specifically, a photoresist 32 is formed by photo lithography. The photoresist 32 is formed above the buried oxide film 3 and the SOI layer 4 remaining in the switch circuit region 102 . Further, an opening(s) is formed in the part of the photoresist 32 in which an element separation in the polysilicon film 10 is to be formed. Then, nitride film dry-etching and oxide film dry-etching are performed by using the photoresist 32 as a mask, and the buried oxide film 3 and the SOI layer 4 located inside the openings of the photoresist 32 are thereby removed.
  • silicon dry-etching is performed and trenches 5 a are formed in the epitaxial layer 2 . Note that this etching is performed in such a manner that the trenches 5 a do not penetrate the epitaxial layer 2 ( FIG. 2E ).
  • the photoresist 32 is removed.
  • a photoresist 33 is formed by photo lithography.
  • the photoresist 33 is formed so as to cover the logic circuit region 101 . Note that no photoresist 33 is formed in the switch circuit region 102 .
  • silicon dry-etching is performed by using the photoresist 33 and the nitride film 22 as masks, and trenches 5 b in the switch circuit region 102 are thereby formed in such a manner the trenches 5 b penetrate the epitaxial layer 2 and reaches the high-resistance substrate 1 ( FIG. 2F ).
  • the photoresist 33 is removed.
  • LOCOS oxidation is performed and LOCOS oxide films 6 a and 6 b are thereby formed.
  • the oxidation spreads from the bottom (downward) and the side (horizontal direction) of the trenches. That is, since the oxidation spreads in the horizontal direction, the epitaxial layer 2 located below the buried oxide film 3 and the SOI layer 4 are entirely oxidized. Since the oxidation spreads downward, the high-resistance substrate 1 is oxidized in the bottom direction.
  • the thickness of the LOCOS oxide film 6 b from the bottom to the buried oxide film 3 becomes a sufficient thickness equal to or greater than 2.0 ⁇ m.
  • the LOCOS oxide film 6 b located below the buried oxide film 3 and the SOI layer 4 expands in the horizontal direction.
  • the oxidation of the trench parts advances and LOCOS oxide films 6 a are thereby formed.
  • the LOCOS oxide films 6 a are formed into such a shape that the LOCOS oxide film 6 a swells beyond the upper surface of the nitride film 22 due to the volume expansion ( FIG. 2G ).
  • an oxide film 7 is formed.
  • the oxide film may be a silicon oxide and can be formed by using a plasma CVD method ( FIG. 2H ). Then, a flattening process is performed and the part of the oxide film 7 that is located above the nitride film 22 is thereby removed. Note that the oxide film 7 is flattened by CMP (Chemical Mechanical Polishing) or etch back ( FIG. 2I ).
  • CMP Chemical Mechanical Polishing
  • etch back FIG. 2I
  • a photoresist 34 is formed by photo lithography. The photoresist 34 is formed so as to cover the switch circuit region 102 but is not formed on the logic circuit region 101 . Then, for example, wet-etching is performed by using the photoresist 34 as a mask and the oxide film 7 remaining in the logic circuit region 101 is removed ( FIG. 2J ).
  • a well layer 8 in the logic circuit region 101 is formed.
  • the nitride film 22 is removed by wet-etching. Note that some of the nitride film 22 may remain on the side of the buried oxide film 3 and the SOI layer 4 through the oxide film 21 . However, the illustration of remaining nitride film 22 is omitted in subsequent figures for simplifying the figures.
  • a photoresist 35 is formed by photo lithography. The photoresist 35 covers the switch circuit region 102 , and an opening is formed in the photoresist 35 in a region where the well layer 8 in the logic circuit region 101 is to be formed.
  • the well layer 8 is formed in a region sandwiched between the LOCOS oxide films 6 a , which function as element separations. Therefore, the opening is formed in the region sandwiched between the LOCOS oxide films 6 a . Then, ion implantation is performed by using the photoresist 35 as a mask and the well layer 8 is thereby formed ( FIG. 2K ).
  • the photoresist 35 is removed. Then, the oxide film 21 and the part of the LOCOS oxide films 6 a protruding above the epitaxial layer 2 are removed by, for example, wet-etching. Note that some of the oxide film 21 may remain on the side of the buried oxide film 3 and the SOI layer 4 . However, the illustration of remaining oxide film 21 is omitted in subsequent figures for simplifying the figures.
  • gate oxidation is performed, so that a gate oxide film 9 a is formed on the logic circuit region 101 and gate oxide films 9 b are formed on the SOI layer 4 ( FIG. 2L ).
  • a polysilicon film 10 which is the material for the gate electrode, is formed in the logic circuit region 101 and the switch circuit region 102 .
  • the polysilicon film 10 can be formed by, for example, an LPCVD (Low Pressure Chemical Vapor Deposition) method ( FIG. 2M ).
  • a photoresist 36 is formed by photo lithography.
  • the photoresist 36 is formed in the parts in which the gate electrodes are to be formed, i.e., in the parts of the polysilicon film 10 that are formed on the SOI layer 4 and the well layer 8 .
  • the polysilicon film 10 located inside the openings of the photoresist 36 is removed by, for example, dry-etching.
  • a gate electrode 10 a of the logic MOSFET 101 a is formed in the logic circuit region 101 and gate electrodes 10 b of the switch MOSFETs 102 a and 102 b are formed in the switch circuit region 102 ( FIG. 2N ).
  • the photoresist 36 is removed.
  • LDD ion implantation is performed by using the gate electrodes 10 a and 10 b as masks in order to form an LDD (Lightly Doped Drain) structure.
  • an oxide film is formed by, for example, a plasma CVD method and the formed oxide film is etched back by, for example, dry-etching.
  • sidewalls 11 are formed on the sides of the gate electrodes 10 a and 10 b .
  • ion implantation is performed and sources and drains are formed ( FIG. 2O ). Note that in FIG.
  • the source regions and the drain regions which are formed by the LDD ion implantation and the subsequent ion implantation, are shown as diffusion layers 12 a and diffusion layers 12 b in the logic circuit region 101 and the switch circuit region 102 respectively.
  • silicides 13 a to 13 d are formed on the surface of the gate electrodes and the diffusion layers by, for example, a sputtering method.
  • the silicide 13 a is formed on the gate electrode 10 a and the silicide 13 b is formed on the diffusion layers 12 a .
  • the silicide 13 c is formed on the gate electrodes 10 b and the silicide 13 d is formed on the diffusion layers 12 b ( FIG. 2P ).
  • an inter-layer insulating film 14 is formed by a known inter-layer insulating film forming technique. As a result, the semiconductor device 100 shown in FIG. 1 can be formed.
  • the LOCOS oxide film 6 b for the switch MOSFETs 102 a and 102 b is formed by using trenches formed in the substrate Sub 1 (epitaxial layer 2 and high-resistance substrate 1 ). Therefore, even when an LOCOS oxide film 6 b having a thickness equal to or greater than 2.0 ⁇ m is formed, the LOCOS oxide film 6 b never protrudes beyond the upper surface of the substrate Sub 1 (upper surface of epitaxial layer 2 ). As a result, it is possible to prevent the occurrence of a difference in height due to the LOCOS oxide film formation. Note that other differences in height that are generated during the manufacturing process are similar to those generated in an ordinary semiconductor manufacturing process. Therefore, according to this structure and this manufacturing method, it is possible to prevent the occurrence of a high difference in height that would be otherwise generated when the LOCOS oxide film is formed and thereby to provide a semiconductor device having high accuracy in dimensions and an excellent yield.
  • FIG. 3 is a cross section schematically showing a structure of a semiconductor device 200 according to the second embodiment.
  • the semiconductor device 200 includes an interface carrier suppression layer 15 below the LOCOS oxide film 6 b . That is, a substrate Sub 2 of the semiconductor device 200 has such a structure that an interface carrier suppression layer 15 is added in the substrate Sub 1 of the semiconductor device 200 .
  • the interface carrier suppression layer 15 is formed as a layer having a smaller specific resistance than that of the high-resistance substrate 1 .
  • the other structure of the semiconductor device 200 is similar to that of the semiconductor device 100 , and therefore its explanation is omitted.
  • FIGS. 4A and 4B are cross sections schematically showing a manufacturing method of the substrate Sub 2 of the semiconductor device 200 .
  • the manufacturing method of the semiconductor device 200 is similar to that of the semiconductor device 100 except that the process shown in FIG. 2A is replaced by the processes shown in FIGS. 4A and 4B .
  • a photoresist 37 is formed above the epitaxial layer 2 so as to cover only the logic circuit region 101 ( FIG. 4A )
  • an interface carrier suppression layer 15 is formed in a region at a predetermined depth of the high-resistance substrate 1 by high-energy ion implantation ( FIG. 4B ).
  • the subsequent manufacturing processes performed after the photoresist 37 is removed are similar to those shown in FIGS. 2B to 2P expect for the presence of the interface carrier suppression layer 15 , and therefore their explanation is omitted.
  • the interface carrier suppression layer 15 is formed below the LOCOS oxide film 6 b . This feature can prevent the occurrence of a depletion layer within the high-resistance substrate in the region below the LOCOS oxide film 6 b . Therefore, according to this structure and this manufacturing method, it is possible not only to obtain similar advantageous effects to those of the semiconductor device 100 and its manufacturing method but also to provide a semiconductor device that can excellently perform a high-speed operation and its manufacturing method.
  • the trenches 5 b may be formed in such a manner that they do not penetrate the epitaxial layer 2 . Further, the trenches 5 b may penetrate the interface carrier suppression layer 15 or may not penetrate the interface carrier suppression layer 15 .

Abstract

A semiconductor device includes a first MOSFET and a second MOSFET that is monolithic-integrated with the first MOSFET on a high-resistance substrate. The first MOSFET includes a first semiconductor layer formed on the high-resistance substrate and a second semiconductor layer formed above the first layer. The second semiconductor layer serves as a well layer of the first MOSFET. The second MOSFET includes a first insulating layer formed on the high-resistance substrate and having a mesa-shape in its upper part, the mesa-shape being formed by being sandwiched between two trenches filled with an oxide film formed in the first semiconductor layer. A second insulating layers formed on the mesa-shape of the first insulating layer and a third semiconductor layer is formed on the second insulating layer, the third semiconductor layer serving as a well layer of the second MOSFET.

Description

    RELATED APPLICATIONS
  • This application is a Continuation application of U.S. patent application Ser. No. 14/007,760, filed on Sep. 26, 2013, which claims priority as a 371 application of PCT/JP2012/001285, filed on Feb. 24, 2012, which further claims priority from JPA No. 2011-072699, filed on Mar. 29, 2011, incorporated herein by reference.
    • TECHNICAL FIELD
  • The present invention relates to a semiconductor device and its manufacturing method, in particular to a semiconductor device in which a plurality of types of elements are provided in a mixed manner and its manufacturing method.
    • BACKGROUND ART
  • As transmission/reception select switches in portable electronic devices such as mobile phones, compound semiconductor elements have been used in the past. However, the improvement in the high-frequency characteristics of silicon MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) that has been achieved by forming silicon MOSFETs on SOI (Silicon on Insulator) substrates or SOS (Silicon on Sapphire) substrates is remarkable in recent years. As a result, opportunities for silicon MOSFETs to be applied as high-frequency switches of portable electronic devices are increasing.
  • A transmission loss, a harmonic distortion, and an inter-modulation distortion (IMD) are some examples of the important characteristics that indicate the performance of a high-frequency switch. These characteristics can be improved by reducing the CR product that is the product of the parasitic capacitance C and the on-resistance R of the MOSFET.
  • Therefore, it has been attempted to reduce the parasitic capacitance C and the on-resistance R by reducing the element size of a MOSFET and thereby reducing the channel length. As a method for reducing a parasitic capacitance C, reduction in the capacitance of source/drain diffusion layers and the miniaturization of a gate length achieved by adopting a thin-film SOI substrate have been known. A thin-film SOI substrate used for such purposes is manufactured, for example, by a smart-cut method.
  • A typical semiconductor device in which MOSFETs are formed on an SOI substrate (Patent literature 1) is explained. FIG. 5 is a cross section showing a structure of a typical semiconductor device 300 in which MOSFETs are formed on an SOI substrate. In the semiconductor device 300, the SOI substrate includes a p-type silicon substrate 314. The silicon substrate 314 includes a first region 310 and a second region 312. A high voltage transistor 313 is formed in the first region 310. Other examples of the semiconductor element that can be formed in the first region 310 include a vertical bipolar transistor. A MOS field-effect transistor 315 having an SOI structure is formed in the second region 312. Examples of the circuit that can be formed in the second region 312 include a circuit for which a high-speed operation or low power consumption is necessary (for example, a circuit used in a portable information device or the like).
  • Next, details of the first region 310 are explained. The high voltage transistor 313 includes a gate electrode 340, source/ drain 334 a and 336 a, and source/ drain offsets 334 b and 336 b. A p-type well 316 is formed in the silicon substrate 314 in the first region 310. A gate oxide film 338 is formed on the well 316. The thickness of the gate oxide film 338 is, for example, 40 to 100 nm. Offset LOCOS oxide films 322 and 324 are formed above the well 316 so as to sandwich the gate oxide film 338 therebetween. The gate electrode 340 is formed on the gate oxide film 338. One end of the gate electrode 340 is located on the offset LOCOS oxide film 322. The other end of the gate electrode 340 is located on the offset LOCOS oxide film 324.
  • An n-type source/drain offset 334 b is formed in the well 316 beneath the offset LOCOS oxide film 322. An n-type source/drain 334 a is formed in the well 316. The n-type source/drain 334 a is located beside the source/drain offset 334 b. An n-type source/drain offset 336 b is formed in the well 316 beneath the offset LOCOS oxide film 324. An n-type source/drain 336 a is formed in the well 316. The n-type source/drain 336 a is located beside the source/drain offset 336 b.
  • An element separation LOCOS oxide film 326 is formed at one end of the well 316, and an element separation LOCOS oxide film 320 is formed at the other end of the well 316. A p-type channel stopper region 330 is formed in the well 316 beneath the element separation LOCOS oxide film 326. A p-type channel stopper region 332 is formed in the well 316 beneath the element separation LOCOS oxide film 320. An inter-layer insulating film 350 is formed above the silicon substrate 314 so as to cover the gate electrode 340. A through hole 342 for exposing the source/drain 334 a is formed in the inter-layer insulating film 350. An aluminum line 346 is formed on the inter-layer insulating film 350. The aluminum line 346 is also formed inside the through hole 342 and electrically connected to the source/drain 334 a. A through hole 344 for exposing the source/drain 336 a is formed in the inter-layer insulating film 350. An aluminum line 348 is formed on the inter-layer insulating film 350. The aluminum line 348 is also formed inside the through hole 344 and electrically connected to the source/drain 336 a.
  • Next, details of the second region 312 are explained. The MOS field-effect transistor 315 includes a gate electrode 360 and source/ drain 354 and 356. A buried oxide film 318 is formed on the silicon substrate 314 in the second region 312. A silicon single-crystal layer is formed on the buried oxide film 318. A p-type body region 352 and n-type source/ drain 354 and 356 are formed in this silicon single-crystal layer. Element separation LOCOS oxide films 326 and 328 are formed on the buried oxide film 318. The MOS field-effect transistor 315 is insulated and separated from other elements by the element separation LOCOS oxide films 326 and 328.
  • A gate oxide film 358 is formed on the body region 352. The thickness of the gate oxide film 358 is, for example, 3 to 10 nm. An inter-layer insulating film 350 is formed above the silicon substrate 314 so as to cover the gate electrode 360. A through hole 362 for exposing the source/drain 354 is formed in the inter-layer insulating film 350. An aluminum line 366 is formed on the inter-layer insulating film 350. The aluminum line 366 is also formed inside the through hole 362 and electrically connected to the source/drain 354. A through hole 364 for exposing the source/drain 356 is formed in the inter-layer insulating film 350. An aluminum line 368 is formed on the inter-layer insulating film 350. The aluminum line 368 is also formed inside the through hole 364 and electrically connected to the source/drain 356.
  • That is, it is possible in the semiconductor device 300 to form both a high voltage MOSFET requiring a deep diffusion layer and a MOSFET having an SOI structure in the same substrate.
  • Further, a drive circuit capable of controlling a slew rate with ease while preventing the increase in the circuit size has been proposed (Patent literature 2). Further, semiconductor devices of similar types have been disclosed (Patent literatures 3 and 4).
    • CITATION LIST Patent Literature
  • Patent literature 1: Japanese Unexamined Patent Application Publication No. 2001-7219
    Patent literature 2: Japanese Unexamined Patent Application Publication No. 8-102498
    Patent literature 2: Japanese Unexamined Patent Application Publication No. 2008-227084
    Patent literature 4: Japanese Unexamined Patent Application Publication No. 2007-201240
    • SUMMARY OF INVENTION Technical Problem
  • However, the inventor has found that there is the following problem in the above-described semiconductor device. In general, when a MOSFET having an SOI structure is used for reducing the parasitic capacitance and/or for high frequency use, it is required to suppress the effects caused by the support substrate. Therefore, the buried oxide film (BOX) layer needs to be formed with a large thickness. When a MOSFET having a thick buried oxide film layer is manufactured, a high difference in height is generated between the combined structure of the SOI substrate and the BOX layer and the support substrate as in the case of the semiconductor device 300 shown in FIG. 5. As a result, the focus is deviated in the lithography process due to the difference in height, and thereby deteriorating the accuracy in dimensions of the device. Further, this also leads to the occurrence of unremoved films at the height-difference part and makes the etching conditions more complicated in the dry-etching process. Therefore, restrictions on devices that can be manufactured and the reduction in yield are unavoidable in the above-described semiconductor device.
    • Solution to Problem
  • A semiconductor device according to an aspect of the present invention includes: a first MOSFET formed on a high-resistance substrate; and a second MOSFET that is monolithic-integrated with the first MOSFET on the high-resistance substrate, in which the first MOSFET includes: a first semiconductor layer formed on the high-resistance substrate; and a second semiconductor layer formed above the first semiconductor layer, the second semiconductor layer serving as a well layer of the first MOSFET, and the second MOSFET includes: a first insulating layer formed on the high-resistance substrate, first insulating layer being sandwiched between two trenches and thus having a mesa-shape in its upper part, an upper surface of the mesa-shape being positioned at the same height as the first semiconductor layer; a second insulating layer formed on the mesa-shape of the first insulating layer; and a third semiconductor layer formed on the second insulating layer, the third semiconductor layer serving as a well layer of the second MOSFET. In this way, even if the first insulating layer is formed, the first insulating layer does not protrude upward beyond the second semiconductor layer. Therefore, it is possible to reduce the difference in height that is generated between the first and second MOSFETs.
  • A semiconductor device according to an aspect of the present invention includes: a first MOSFET formed on a high-resistance substrate; and a second MOSFET that is monolithic-integrated with the first MOSFET on the high-resistance substrate, in which the first MOSFET includes: a first semiconductor layer formed on the high-resistance substrate; and a second semiconductor layer formed above the first semiconductor layer, the second semiconductor layer serving as a well layer of the first MOSFET, and the second MOSFET includes: a first insulating layer formed on the high-resistance substrate, the first insulating layer having a mesa-shape in its upper part, the mesa-shape being formed by forming trenches in the first semiconductor layer and then performing oxidation treatment from a side and a bottom of the trenches and thereby being sandwiched between two trenches: a second insulating layer formed on the mesa-shape of the first insulating layer; and a third semiconductor layer formed on the second insulating layer, the third semiconductor layer serving as a well layer of the second MOSFET. In this way, even if the first insulating layer is formed, the first insulating layer does not protrude upward beyond the second semiconductor layer. Therefore, it is possible to reduce the difference in height that is generated between the first and second MOSFETs.
  • A manufacturing method of a semiconductor device according to an aspect of the present invention includes: forming a first semiconductor layer on the high-resistance substrate; forming a second insulating layer on the first semiconductor layer; forming a third semiconductor layer on the second insulating layer, the third semiconductor layer serving as a well layer of a second MOSFET; removing the second insulating layer and the third semiconductor layer in a first region and forming an opening in the second insulating layer and the third semiconductor layer in a second region; forming trenches by etching the first semiconductor layer in the opening formed in the second insulating layer and the third semiconductor layer in the second region, and thereby forming a mesa-shape sandwiched between two trenches in the the first semiconductor layer located below the second insulating layer and the third semiconductor layer; forming a first insulating layer by performing oxidation treatment from a side and a bottom of the trenches, the first insulating layer being sandwiched between two trenches and thus having a mesa-shape in its upper part; and forming a second semiconductor layer above the first semiconductor layer in the first region, the second semiconductor layer serving as a well layer of a first MOSFET. In this way, even if the first insulating layer is formed, the first insulating layer does not protrude upward beyond the second semiconductor layer. Therefore, it is possible to reduce the difference in height that is generated between the first and second MOSFETs.
    • Advantageous Effects of Invention
  • According to the present invention, it is possible to provide a semiconductor device and its manufacturing method in which a transistor to be formed on an insulating layer can be suitably monolithic-integrated.
    • BRIEF DESCRIPTION OF DRAWINGS
  • FIG. 1 is a cross section schematically showing a structure of a semiconductor device 100 according to a first embodiment;
  • FIG. 2A is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment;
  • FIG. 2B is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment;
  • FIG. 2C is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment;
  • FIG. 2D is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment;
  • FIG. 2E is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment;
  • FIG. 2F is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment;
  • FIG. 2G is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment;
  • FIG. 2H is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment;
  • FIG. 2I is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment;
  • FIG. 2J is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment;
  • FIG. 2K is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment;
  • FIG. 2L is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment;
  • FIG. 2M is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment;
  • FIG. 2N is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment;
  • FIG. 2O is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment;
  • FIG. 2P is a cross section schematically showing a manufacturing method of a semiconductor device 100 according to a first embodiment;
  • FIG. 3 is a cross section schematically showing a manufacturing method of a semiconductor device 200 according to a second embodiment;
  • FIG. 4A is a cross section schematically showing a manufacturing method of a substrate Sub2 of a semiconductor device 200 according to a second embodiment;
  • FIG. 4B is a cross section schematically showing a manufacturing method of a substrate Sub2 of a semiconductor device 200 according to a second embodiment; and
  • FIG. 5 is a cross section schematically showing a semiconductor device 300.
    •  DESCRIPTION OF EMBODIMENTS Example 1
  • Embodiments according to the present invention are explained hereinafter with reference to the drawings. The same symbols are assigned to the same components throughout the drawings, and their duplicated explanation is omitted as necessary.
    • First Embodiment
  • A semiconductor device 100 according to a first embodiment of the present invention is explained. FIG. 1 is a cross section schematically showing a structure of a semiconductor device 100 according to the first embodiment. The semiconductor device 100 includes a logic circuit region 101 and a switch circuit region 102 that are monolithic-integrated on a high-resistance substrate 1. As shown in FIG. 1, for example, a logic MOSFET 101 a is formed in the logic circuit region 101. Switch MOSFETs 102 a and 102 b are formed in the switch circuit region 102.
  • In the logic circuit region 101, an epitaxial layer 2 is formed on the high-resistance substrate 1. The high-resistance substrate 1 is made of, for example, silicon having a specific resistance of ρs=10 kΩ·cm. The epitaxial layer is made of, for example, n-type silicon having a specific resistance of ρe=10 to 20 kΩ·cm. LOCOS oxide films 6 a, which are insulating layers, are formed above the epitaxial layer 2. A well layer 8 made of p-type silicon, for example, is formed between two LOCOS oxide films 6 a. The logic MOSFET 101 a is formed on the well layer 8. Note that the part of the epitaxial layer 2 on which no well layer 8 is formed and the LOCOS oxide films 6 a are covered by a gate oxide film 9 a.
  • A structure of the logic MOSFET 101 a is explained. Two n-type diffusion layers 12 a, for example, are formed in the upper part of the well layer 8. The two diffusion layers 12 a serve as the source and the drain, respectively, of the logic MOSFET 101 a. A gate oxide film 9 a, which is an insulating film, is formed between the two diffusion layers 12 a. The gate oxide film 9 a is formed between the well layer 8 and the gate electrode 10 a. Note that the gate electrode 10 a is made of, for example, polysilicon, and the gate oxide film 9 a is composed of a silicon oxide film. A silicide 13 a is formed on the gate oxide film 10 a. Silicides 13 b are formed on the diffusion layers 12 a. The sidewall of the gate oxide film 10 a is covered by a sidewall 11. Further, an inter-layer insulating film 14, which covers the logic MOSFET 101 a, is formed. A contact hole is formed in the inter-layer insulating film 14 above each of the silicides 13 a and 13 b.
  • In the switch circuit region 102, an LOCOS oxide film 6 b, which is an insulating layer, is formed on the high-resistance substrate 1. Trenches 5 are formed in the LOCOS oxide film 6 b. As a result, an upper part of the LOCOS oxide film, which is sandwiched between the trenches 5, has a mesa-shape. The trenches 5 are filled with an oxide film 7.
  • A structure of the switch MOSFET 102 a is explained. A buried oxide film 3 (thickness of 0.1 to 0.4 μm) and an SOI layer 4 (thickness no greater than 0.1 μm) are formed on the LOCOS oxide film 6 b. The buried oxide film 3, which is an insulating layer, is made of, for example, silicon oxide, and the SOI layer 4 is made of, for example, silicon. Diffusion layers 12 b are formed in the upper part of the SOI layer 4. The two diffusion layers 12 b serve as the source and the drain, respectively, of the switch MOSFET 102 a. A gate oxide film 9 b, which is an insulating film, is formed between the upper surface of the SOI layer 4 and a gate electrode 10 b. Note that the gate electrode 10 b is made of, for example, polysilicon, and the gate oxide film 9 b is made of silicon oxide. A silicide 13 c is formed on the gate oxide film 10 b. Silicides 13 d are formed on the diffusion layers 12 b. The sidewall of the gate electrode 10 b is covered by a sidewall 11. Further, an inter-layer insulating film 14, which covers the switch MOSFET 102 a, is formed. A contact hole is formed in the inter-layer insulating film 14 above each of the silicides 13 c and 13 d. Note that the structure of a switch MOSFET 102 b is similar to that of the switch MOSFET 102 a, and therefore its explanation is omitted.
  • Note that in the semiconductor device 100, the logic circuit region 101 corresponds to the first region and the switch circuit region 102 corresponds to the second region. The logic MOSFET 101 a corresponds to the first MOSFET and the switch MOSFETs 102 a and 102 b correspond to the second MOSFET. The epitaxial layer 2, the well layer 8, the SOI layer 4, and an interface carrier suppression layer 15 correspond to the first to fourth semiconductor layers respectively. The LOCOS oxide film 6 b and the buried oxide film 3 correspond to the first and second oxide films respectively. The gate oxide films 9 a and 9 b correspond to the first and second gate insulating films respectively. The diffusion layers 12 a correspond to the first and second diffusion layers. The diffusion layers 12 b correspond to the third and fourth diffusion layers. The LOCOS oxide films 6 a correspond to the first and second element separations. The above-described correlations between the terms are also applied to the following explanation.
  • Next, a manufacturing method of the semiconductor device 100 is explained. FIGS. 2A to 2P are cross sections schematically showing a manufacturing method of the semiconductor device 100. Firstly, an epitaxial layer 2 is formed on a high-resistance substrate 1 by, for example, MOCVD (Metal Organic Chemical Vapor Deposition) or the like. Then, a buried oxide film 3 and an SOI layer 4 are formed by wafer bonding using a smart-cut method, and thereby manufacturing an SOI substrate (FIG. 2A).
  • Next, a photoresist 31 is formed by photo lithography. The photoresist 31 has openings in the switch circuit region 102. Further, no photoresist 31 is formed in the logic circuit region 101 (FIG. 2B). Then, dry-etching is performed by using the photoresist 31 as a mask and the buried oxide film 3 and the SOI layer 4 are thereby removed. After the etching is finished, the photoresist 31 is removed. Note that the width of the remaining buried oxide film 3 and the SOI layer 4 is no greater than 0.6 μm (FIG. 2C).
  • Next, an oxide film 21 and a nitride film 22, which are used as masks in subsequent processes, are formed in the logic circuit region 101 and the switch circuit region 102. For example, a silicon oxide can be used for the oxide film 21 and a silicon nitride can be used for the nitride film 22. Each of the oxide film 21 and the nitride film 22 can be formed by, for example, a plasma CVD method (FIG. 2D).
  • Next, a mask pattern used for LOCOS oxide film formation is formed. Specifically, a photoresist 32 is formed by photo lithography. The photoresist 32 is formed above the buried oxide film 3 and the SOI layer 4 remaining in the switch circuit region 102. Further, an opening(s) is formed in the part of the photoresist 32 in which an element separation in the polysilicon film 10 is to be formed. Then, nitride film dry-etching and oxide film dry-etching are performed by using the photoresist 32 as a mask, and the buried oxide film 3 and the SOI layer 4 located inside the openings of the photoresist 32 are thereby removed. Next, silicon dry-etching is performed and trenches 5 a are formed in the epitaxial layer 2. Note that this etching is performed in such a manner that the trenches 5 a do not penetrate the epitaxial layer 2 (FIG. 2E).
  • After the above-described etching is finished, the photoresist 32 is removed. After the photoresist 32 is removed, a photoresist 33 is formed by photo lithography. The photoresist 33 is formed so as to cover the logic circuit region 101. Note that no photoresist 33 is formed in the switch circuit region 102. Then, silicon dry-etching is performed by using the photoresist 33 and the nitride film 22 as masks, and trenches 5 b in the switch circuit region 102 are thereby formed in such a manner the trenches 5 b penetrate the epitaxial layer 2 and reaches the high-resistance substrate 1 (FIG. 2F).
  • After the above-described etching is finished, the photoresist 33 is removed. After the photoresist 33 is removed, LOCOS oxidation is performed and LOCOS oxide films 6 a and 6 b are thereby formed. In the switch circuit region 102, the oxidation spreads from the bottom (downward) and the side (horizontal direction) of the trenches. That is, since the oxidation spreads in the horizontal direction, the epitaxial layer 2 located below the buried oxide film 3 and the SOI layer 4 are entirely oxidized. Since the oxidation spreads downward, the high-resistance substrate 1 is oxidized in the bottom direction. As a result, the thickness of the LOCOS oxide film 6 b from the bottom to the buried oxide film 3 becomes a sufficient thickness equal to or greater than 2.0 μm. Note that when LOCOS oxidation is performed, the volume increases in comparison to before the oxidation. Therefore, the LOCOS oxide film 6 b located below the buried oxide film 3 and the SOI layer 4 expands in the horizontal direction. Meanwhile, in the logic circuit region 101, the oxidation of the trench parts advances and LOCOS oxide films 6 a are thereby formed. Note that the LOCOS oxide films 6 a are formed into such a shape that the LOCOS oxide film 6 a swells beyond the upper surface of the nitride film 22 due to the volume expansion (FIG. 2G).
  • Next, an oxide film 7 is formed. For example, the oxide film may be a silicon oxide and can be formed by using a plasma CVD method (FIG. 2H). Then, a flattening process is performed and the part of the oxide film 7 that is located above the nitride film 22 is thereby removed. Note that the oxide film 7 is flattened by CMP (Chemical Mechanical Polishing) or etch back (FIG. 2I). After the flattening process is finished, a photoresist 34 is formed by photo lithography. The photoresist 34 is formed so as to cover the switch circuit region 102 but is not formed on the logic circuit region 101. Then, for example, wet-etching is performed by using the photoresist 34 as a mask and the oxide film 7 remaining in the logic circuit region 101 is removed (FIG. 2J).
  • Next, a well layer 8 in the logic circuit region 101 is formed. Firstly, the nitride film 22 is removed by wet-etching. Note that some of the nitride film 22 may remain on the side of the buried oxide film 3 and the SOI layer 4 through the oxide film 21. However, the illustration of remaining nitride film 22 is omitted in subsequent figures for simplifying the figures. Next, a photoresist 35 is formed by photo lithography. The photoresist 35 covers the switch circuit region 102, and an opening is formed in the photoresist 35 in a region where the well layer 8 in the logic circuit region 101 is to be formed. The well layer 8 is formed in a region sandwiched between the LOCOS oxide films 6 a, which function as element separations. Therefore, the opening is formed in the region sandwiched between the LOCOS oxide films 6 a. Then, ion implantation is performed by using the photoresist 35 as a mask and the well layer 8 is thereby formed (FIG. 2K).
  • After the ion implantation is finished, the photoresist 35 is removed. Then, the oxide film 21 and the part of the LOCOS oxide films 6 a protruding above the epitaxial layer 2 are removed by, for example, wet-etching. Note that some of the oxide film 21 may remain on the side of the buried oxide film 3 and the SOI layer 4. However, the illustration of remaining oxide film 21 is omitted in subsequent figures for simplifying the figures. After that, gate oxidation is performed, so that a gate oxide film 9 a is formed on the logic circuit region 101 and gate oxide films 9 b are formed on the SOI layer 4 (FIG. 2L).
  • Next, gate electrodes are formed. Firstly, a polysilicon film 10, which is the material for the gate electrode, is formed in the logic circuit region 101 and the switch circuit region 102. The polysilicon film 10 can be formed by, for example, an LPCVD (Low Pressure Chemical Vapor Deposition) method (FIG. 2M). Then, a photoresist 36 is formed by photo lithography. The photoresist 36 is formed in the parts in which the gate electrodes are to be formed, i.e., in the parts of the polysilicon film 10 that are formed on the SOI layer 4 and the well layer 8. Next, the polysilicon film 10 located inside the openings of the photoresist 36 is removed by, for example, dry-etching. As a result, a gate electrode 10 a of the logic MOSFET 101 a is formed in the logic circuit region 101 and gate electrodes 10 b of the switch MOSFETs 102 a and 102 b are formed in the switch circuit region 102 (FIG. 2N).
  • After the gate electrodes are formed, the photoresist 36 is removed. Then, LDD ion implantation is performed by using the gate electrodes 10 a and 10 b as masks in order to form an LDD (Lightly Doped Drain) structure. Next, an oxide film is formed by, for example, a plasma CVD method and the formed oxide film is etched back by, for example, dry-etching. As a result, sidewalls 11 are formed on the sides of the gate electrodes 10 a and 10 b. After that, ion implantation is performed and sources and drains are formed (FIG. 2O). Note that in FIG. 2O, for simplifying the figure, the source regions and the drain regions, which are formed by the LDD ion implantation and the subsequent ion implantation, are shown as diffusion layers 12 a and diffusion layers 12 b in the logic circuit region 101 and the switch circuit region 102 respectively.
  • Next, silicides 13 a to 13 d are formed on the surface of the gate electrodes and the diffusion layers by, for example, a sputtering method. The silicide 13 a is formed on the gate electrode 10 a and the silicide 13 b is formed on the diffusion layers 12 a. The silicide 13 c is formed on the gate electrodes 10 b and the silicide 13 d is formed on the diffusion layers 12 b (FIG. 2P).
  • Finally, an inter-layer insulating film 14 is formed by a known inter-layer insulating film forming technique. As a result, the semiconductor device 100 shown in FIG. 1 can be formed.
  • In the above-described semiconductor device 100 and its manufacturing method, the LOCOS oxide film 6 b for the switch MOSFETs 102 a and 102 b is formed by using trenches formed in the substrate Sub1 (epitaxial layer 2 and high-resistance substrate 1). Therefore, even when an LOCOS oxide film 6 b having a thickness equal to or greater than 2.0 μm is formed, the LOCOS oxide film 6 b never protrudes beyond the upper surface of the substrate Sub1 (upper surface of epitaxial layer 2). As a result, it is possible to prevent the occurrence of a difference in height due to the LOCOS oxide film formation. Note that other differences in height that are generated during the manufacturing process are similar to those generated in an ordinary semiconductor manufacturing process. Therefore, according to this structure and this manufacturing method, it is possible to prevent the occurrence of a high difference in height that would be otherwise generated when the LOCOS oxide film is formed and thereby to provide a semiconductor device having high accuracy in dimensions and an excellent yield.
    • Second Embodiment
  • Next, a semiconductor device 200 according to a second embodiment of the present invention is explained. FIG. 3 is a cross section schematically showing a structure of a semiconductor device 200 according to the second embodiment. The semiconductor device 200 includes an interface carrier suppression layer 15 below the LOCOS oxide film 6 b. That is, a substrate Sub2 of the semiconductor device 200 has such a structure that an interface carrier suppression layer 15 is added in the substrate Sub1 of the semiconductor device 200. The interface carrier suppression layer 15 is formed as a layer having a smaller specific resistance than that of the high-resistance substrate 1. The other structure of the semiconductor device 200 is similar to that of the semiconductor device 100, and therefore its explanation is omitted.
  • Next, a manufacturing method of the semiconductor device 200 is explained. The manufacturing method of the semiconductor device 200 is different in the manufacturing method of the substrate. FIGS. 4A and 4B are cross sections schematically showing a manufacturing method of the substrate Sub2 of the semiconductor device 200. The manufacturing method of the semiconductor device 200 is similar to that of the semiconductor device 100 except that the process shown in FIG. 2A is replaced by the processes shown in FIGS. 4A and 4B.
  • In this manufacturing method, by using photo lithography, a photoresist 37 is formed above the epitaxial layer 2 so as to cover only the logic circuit region 101 (FIG. 4A) Then, an interface carrier suppression layer 15 is formed in a region at a predetermined depth of the high-resistance substrate 1 by high-energy ion implantation (FIG. 4B). The subsequent manufacturing processes performed after the photoresist 37 is removed are similar to those shown in FIGS. 2B to 2P expect for the presence of the interface carrier suppression layer 15, and therefore their explanation is omitted.
  • In general, when a MOSFET having an SOI structure is applied to a high-speed device, a depletion layer is sometimes generated within the high-resistance substrate in a region below a thick oxide film such as the LOCOS oxide film 6 b. As a result, a situation that a high-speed operation of the semiconductor device is hindered may occur. However, in the above-described semiconductor device 200 and its manufacturing method, the interface carrier suppression layer 15 is formed below the LOCOS oxide film 6 b. This feature can prevent the occurrence of a depletion layer within the high-resistance substrate in the region below the LOCOS oxide film 6 b. Therefore, according to this structure and this manufacturing method, it is possible not only to obtain similar advantageous effects to those of the semiconductor device 100 and its manufacturing method but also to provide a semiconductor device that can excellently perform a high-speed operation and its manufacturing method.
  • Note that the present invention is not limited to the above-described embodiments, and modifications can be made as appropriate without departing from the spirit of the present invention. For example, the trenches 5 b may be formed in such a manner that they do not penetrate the epitaxial layer 2. Further, the trenches 5 b may penetrate the interface carrier suppression layer 15 or may not penetrate the interface carrier suppression layer 15.
  • The above-mentioned materials for the oxide film, the nitride film, and so on are mere examples. For example, other insulating films such as a silicon oxide film, a silicon nitride film, and a silicon oxynitride film can be also applied. Further, the semiconductor (silicon) conductive types are also mere examples. For example, the p-type and the n-type may be interchanged.
  • This application is based upon and claims the benefit of priority from Japanese patent application No. 2011-72699, filed on Mar. 29, 2011, the disclosure of which is incorporated herein in its entirety by reference.
    • INDUSTRIAL APPLICABILITY Reference Signs List
    • 1 HIGH-RESISTANCE SUBSTRATE
    • 2 EPITAXIAL LAYER
    • 3 BURIED OXIDE FILM
    • 4 SOI LAYER
    • 5 TRENCH
    • 6A, 6B LOCOS OXIDE FILM
    • 7 OXIDE FILM
    • 8 WELL LAYER
    • 9A, 9B GATE OXIDE FILM
    • 10 POLYSILICON FILM
    • 10A, 10B GATE ELECTRODE
    • 11 SIDEWALL
    • 12A, 12B DIFFUSION LAYER
    • 13A-13D SILICIDE
    • 14 INTER-LAYER INSULATING FILM
    • 15 INTERFACE CARRIER SUPPRESSION LAYER
    • 21 OXIDE FILM
    • 22 NITRIDE FILM
    • 31-37 PHOTORESIST
    • 100, 200, 300 SEMICONDUCTOR DEVICE
    • 101 LOGIC CIRCUIT REGION
    • 102 SWITCH CIRCUIT REGION
    • 101A LOGIC MOSFET
    • 102A, 102B SWITCH MOSFET
    • 310 FIRST REGION
    • 312 SECOND REGION
    • 313 HIGH WITHSTAND-VOLTAGE TRANSISTOR
    • 314 SILICON SUBSTRATE
    • 315 MOS FIELD-EFFECT TRANSISTOR
    • 316 WELL
    • 318 BURIED OXIDE FILM
    • 320, 326, 328 ELEMENT SEPARATION LOCOS OXIDE FILM
    • 322, 324 OFFSET LOCOS OXIDE FILM
    • 330, 332 CHANNEL STOPPER REGION
    • 334A, 336A, 354, 356 SOURCE/DRAIN
    • 334B, 336B SOURCE/DRAIN OFFSET
    • 338, 358 GATE OXIDE FILM
    • 340, 360 GATE ELECTRODE
    • 342, 344, 362, 364 THROUGH HOLE
    • 346, 348, 366, 368 ALUMINUM LINE
    • 350 INTER-LAYER INSULATING FILM
    • 352 BODY REGION
    • Sub1, Sub2 SUBSTRATE

Claims (6)

1. A semiconductor device comprising:
a first MOSFET formed on a high-resistance substrate; and
a second MOSFET that is monolithic-integrated with the first MOSFET on the high-resistance substrate,
wherein the first MOSFET comprises:
a first semiconductor layer formed on the high-resistance substrate; and
a second semiconductor layer formed above the first semiconductor layer, the second semiconductor layer serving as a well layer of the first MOSFET, and the second MOSFET comprises:
a first insulating layer formed on the high-resistance substrate, the first insulating layer having a mesa-shape in its upper part, the mesa-shape being formed by being sandwiched between two trenches formed in the first semiconductor layer, the two trenches being filled with an oxide film;
a second insulating layer formed on the mesa-shape of the first insulating layer; and
a third semiconductor layer formed on the second insulating layer, the third semiconductor layer serving as a well layer of the second MOSFET.
2. The semiconductor device according to claim 1, wherein the first MOSFET further comprises:
first and second element separations formed above the first semiconductor layer so as to sandwich the second semiconductor layer therebetween;
first and second diffusion layers formed above the second semiconductor layer, the first and second diffusion layers being apart from each other;
a first gate insulating film formed on the second semiconductor layer located between the first and second diffusion layers; and
a first gate electrode formed on the first gate insulating film, and
the second MOSFET further comprises:
third and fourth diffusion layers formed above the third semiconductor layer,
the third and fourth diffusion layers being apart from each other;
a second gate insulating film formed on the third semiconductor layer located between the third and fourth diffusion layers; and
a second gate electrode formed on the second gate insulating film.
3. The semiconductor device according to claim 1, further comprising a fourth semiconductor layer formed between the high-resistance substrate and the first insulating layer, the fourth semiconductor layer having a smaller specific resistance than that of the high-resistance substrate.
4. The semiconductor device according to claim 1, wherein a trench is formed in the first semiconductor layer formed on the high-resistance substrate of the second MOSFET, the trench being formed so as not to penetrate the first semiconductor layer.
5. The semiconductor device according to claim 1, wherein a trench is formed in the first semiconductor layer formed on the high-resistance substrate of the second MOSFET, the trench being formed so as to reach the high-resistance substrate.
6. The semiconductor device according to claim 3, wherein a trench is formed in the first semiconductor layer formed on the high-resistance substrate of the second MOSFET, the trench being formed so as to penetrate that first semiconductor layer and reach the fourth semiconductor layer.
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