JP3344047B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. The present invention can provide a semiconductor element having good crystallinity even for a narrow fine element.

[0002]

2. Description of the Related Art As a conventional semiconductor device manufacturing technique, FIG.
As shown in FIG. 1, the L-SPE method (lateral solid layer growth method) is known. In this technique, lateral solid layer growth is performed on the underlying oxide film layer 5 shown in the figure from the left end of the Si substrate layer 6. As a result, the source or drain regions 4a and 4b and the semiconductor layer 1, the gate insulating layer 2,
A gate electrode 3 is formed.

The device shown in FIG. 8 can be used as an impurity-controlled SOI device by injecting an impurity into a semiconductor layer denoted by reference numeral 1 and has a gate electrode 3 and a Si substrate layer 6 formed of two gates. By using the semiconductor layer 1 as a depletion layer control type, it is also possible to use it as a depletion layer control P-type XMOS transistor. In the semiconductor device structure by the L-SPE method, an integrated circuit combining an SOI and a bulk device can be formed by using the SOI structure and other parts of the Si substrate layer 6 together. Benefits can be expected.

However, in the structure by the L-SPE method, the crystallinity of the semiconductor layer 1 is not as high as that of a bulk, and therefore, a good device comparable to a bulk transistor has not been obtained.

[0005] A similar situation is the so-called XMO described below.
The same can be said for the S transistor. That is, conventionally, the M has a structure in which gates are formed on opposing surfaces of the semiconductor region.
An OS transistor is known, and as this kind of technology, a so-called XMOS is known (Japanese Patent Application Laid-Open No. 57-1).
No. 8364, "CALCULATED THR"
ESHOLD-VOLTAGE CHARACTERI
STICS OF ANXMOS TRANSISTO
R HAVING AN ADDITIONAL BO
TTOM GATE "(S.S.E. 27, Nos8 /
9, pp 828, 1984)).

FIG. 7 is a schematic cross-sectional view of an XMOS transistor according to the conventional solid-phase epitaxial growth technique. As shown in the figure, this MOS transistor has a gate electrode G1 and a gate electrode G shown by reference numerals 13a and 13b on opposite surfaces of a semiconductor layer 11 which is a semiconductor region.
2 is formed. More specifically, a low impurity concentration p ⁻ -type, n ⁻ -type, or intrinsic i-type semiconductor layer 11 serving as a channel forming portion is sandwiched, and a gate portion, that is, a gate insulating layer 12 is interposed therebetween. First and second
Of the gate electrodes 13a (G1) and 13b (G2) are opposed to each other. On both sides of the portion sandwiched between the gate electrodes 13a and 13b, the semiconductor layer 11 is doped with n-type or p-type impurities, for example, impurities by ion implantation, to form source or drain regions 14a and 14b.
Are formed respectively. The transistor having this structure does not cause punch-through, has good switching characteristics, can control the characteristics without introducing impurities into the channel region, and can control the gate electrode 13a (G
Since the control voltage can be independently applied to 1) and 13b (G2), the control has a high degree of freedom.

However, with respect to the XMOS by such a lateral solid phase epitaxial growth technique, an element having good carrier mobility, for example, cannot be obtained because the crystallinity of the epitaxial growth layer is incomplete.

[0008]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems of the prior art, and to provide a narrow and fine element having good crystallinity and good characteristics. It is an object of the present invention to provide a semiconductor device in which an integrated circuit can be formed by incorporating another semiconductor element such as a device into the same semiconductor device.

In addition, a semiconductor device which can easily form a narrow element having good characteristics as described above and another semiconductor element such as a bulk device on the same plane by a series of steps can be easily manufactured. The aim is to provide a method.

[0010]

[0011]

[0012]

[0013]

According to a first aspect of the present invention, a narrow semiconductor projection and a wide semiconductor substrate region separated from the projection by a recess are formed on a semiconductor substrate. A method of manufacturing a semiconductor device, comprising forming an element in each of a narrow semiconductor region and a wide semiconductor substrate region by insulating the base to separate the semiconductor protrusion into a narrow semiconductor region. A method of manufacturing a semiconductor device, wherein the semiconductor protrusion is separated from the protrusion by selectively performing ion implantation only on the base of the semiconductor protrusion and insulating the base. The above object is achieved.

According to a second aspect of the present invention, there is provided the method of manufacturing a semiconductor device according to the first aspect, wherein the ion implantation is an oxygen ion implantation.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the second aspect, wherein the ion implantation is a nitrogen ion implantation.

[0016] A fourth aspect of the present invention, 請, characterized in that together with performing ion implantation into the base alone, and configured to perform insulation of the base portion covering the mask to expose the base portion only
A method for manufacturing a semiconductor device according to any one of claims 1 to 3 , which achieves the above object.

[0017] The invention of claim 5, performs a silicon ion implantation into the base only, in claim 1, characterized in that a configuration in which insulation of the base portion covering the mask to expose the base portion only A method for manufacturing a semiconductor device as described above, whereby the above object is achieved.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to any one of the first to fifth aspects, wherein the ion implantation is performed by oblique ion implantation. Things.

According to the invention of claim 1 of the present application, the semiconductor projection has a narrow convex area, and the other area of the semiconductor substrate on which the element is formed is a large semiconductor substrate area separated by the semiconductor projection and the concave. It can be preferably carried out in the following mode.

[0020]

In the semiconductor device of the present invention, the base of the semiconductor protrusion on the semiconductor substrate forms an isolated semiconductor region by insulation, and an element is formed in the semiconductor region. Even if it is miniaturized, the element is formed in a semiconductor region having good crystallinity, and the characteristics are good. In addition, since an element having such characteristics and an element such as a bulk transistor are further formed in another region of the semiconductor substrate, an integrated circuit can be formed for the same semiconductor device.

According to the method of manufacturing a semiconductor device of the present invention, a narrow semiconductor projection and a wide semiconductor substrate region separated from the projection by a recess are formed on a semiconductor substrate. The semiconductor protrusions are separated into narrow semiconductor regions, and elements are formed in the narrow semiconductor regions and the wide semiconductor substrate regions. An advantageous semiconductor device that can be manufactured can be easily and satisfactorily obtained on the same semiconductor substrate plane in a series of steps.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. However, needless to say, the present invention is not limited by the embodiments described below.

Embodiment 1 This embodiment is an example of application to a Si semiconductor integrated circuit device.
Although this example is a reference example, description of the embodiment according to the present invention
Therefore, in the present specification, for the sake of convenience,
It will be described.

As shown in FIG. 1, the semiconductor device of this embodiment has a semiconductor projection 21 on a semiconductor substrate 26, and the base of the semiconductor projection 21 is insulated (an insulation portion is indicated by reference numeral 25). An element is formed in the semiconductor region (projection) 21 and an element (a source / drain region of this element is formed in another region 21 ′ of the semiconductor substrate 26). (Indicated by reference numeral 24 ').

In particular, the semiconductor projection 21 forms a narrow convex region (the width is narrow in the left-right direction in FIG. 1 and the cross section taken along the line AA 'in FIG. The source / drain region 24 is formed as shown in the figure.) The other region of the semiconductor substrate on which the element is formed has a wide semiconductor substrate region 21 ′ separated by the semiconductor protrusion 21 and the recess 28. No.

The manufacturing process of the semiconductor device of this embodiment is as follows.
This is as shown in FIGS. That is, a narrow semiconductor protrusion 21 and a wide semiconductor substrate region 21 ′ separated from the protrusion 21 by a concave portion 28 are formed on the semiconductor substrate 26 (FIG. 3), and the base of the semiconductor protrusion 21 is formed. The semiconductor protrusion is separated into a semiconductor region by insulation (FIGS. 4 and 5), and the narrow semiconductor region (projection) 21 and the wide semiconductor substrate region 2 are formed.
1 'is formed to obtain the structure shown in FIG.

Specifically, in this embodiment, a semiconductor device is manufactured by the following steps. As shown in FIG. 3, an oxide film, a polysilicon layer 23, and a nitride film (Si ₃ N ₄ ) layer 27 are formed on the upper surface of a Si substrate layer 26, and etching is performed by RIE using a resist as a mask. Is oxidized to form an oxide film 22, thereby forming a small island-shaped projection (semiconductor layer) 21 and a bulk semiconductor layer 21 'separated by a concave portion 28.

Next, a nitride film layer of about 100 nm is deposited by CVD, and thereafter, the nitride film layer is etched by RIE to form a sidewall 27 'as shown in FIG. Next, the bottom of the sidewall 27 'and the Si substrate layer 2
6 is etched with HF / HNO ₃ . Thereby, a shape in which the base of the semiconductor protrusion 21 is exposed as shown in FIG. 4 is obtained.

By oxidizing the structure of FIG. 4, the bottoms of the small island-like protrusions (semiconductor layers) 21 are separated by the LOCOS oxide film layer 25 coming from both sides, and
An OI structure is formed to have the shape shown in FIG. Also, the bulk semiconductor layer 21 'on the right side of FIG.
Only a part of the OCOS oxide film layer penetrates.

Next, the nitride films 27, 27 'are etched by RIE using the resist 29 shown by the broken line in FIG. 1 as a mask, as shown by 27 ", and then the polysilicon layers 23, 23' (FIG. 4) are removed. Gates 23, 23 'in FIG.
(G1 and G2, see also FIG. 2) except for the removal.

Then, while the resist 29 and the nitride film 27 "are kept attached, the source or drain regions 24 and 24 'are formed by ion implantation.
It is also possible to form an LDD structure by forming sidewalls with a nitride film before the source / drain ion implantation step. After the formation of the source / drain 24, the resist 29 and the nitride film 27 ″ are removed, and the gate 23 (G1) of the SOI portion and the gate 23 ′ of the bulk transistor portion are removed.
(G2) is formed.

FIG. 2 shows a cross section taken along the line AA 'of FIG. That is, the source or drain region 24 shown here
Is the semiconductor protrusion 21 below the gate 23 (G1) in FIG.
2, that is, right and left immediately below the gate 23 (G1) in FIG. The configuration in this case is a normal SOI structure, but the semiconductor protrusion 21 is a part of the protrusion of the bulk silicon substrate, and the protrusion semiconductor region 21 is LOC.
Since the structure is separated by the OS, the crystallinity of the protruding semiconductor region 21 is good, and the same mobility as that of the bulk portion can be obtained.

As can be seen from a series of steps shown in these figures, in this embodiment, the SOI portion and the bulk MOS
Since the transistors can be formed simultaneously and on the same surface, it is suitable for high integration.

In addition, it is possible to apply the SOI device to a location having the advantages of the SOI structure (such as no latch-up and a small capacitance between the source / drain and the substrate). In the region where mobility is reduced due to the accumulation of heat, the bulk MOS
An integrated circuit can be formed using transistors. Note that the word MOS here is not limited to a metal-oxide-insulator-semiconductor structure, but is a general term for a transistor having a conductive-insulator-semiconductor structure.

In this embodiment, a method for forming a normal SOI structure as the SOI portion has been described. However, instead of the gate 23 (G1) of the SOI portion in FIG. The XMOS transistor (see FIG. 7) which can operate at high speed by the double gate structure and depletion layer control by arranging the source / drain regions as shown in FIG. It can be manufactured and can coexist with a bulk transistor.

The bulk portion is not limited to a MOS transistor, but may be a bipolar transistor, a CCD, or the like.
It is also possible to form them on the same substrate as the SOI structure.

According to this embodiment, a device having good crystallinity can be obtained as an SOI device.

Further, the SOI device and the bulk device can be formed in the same step and on the same plane, which is suitable for integration into an integrated circuit.

Further, by applying this embodiment, it is possible to use a conventional impurity control type device or a depletion layer control type double gate structure XMOS structure as a SOI device, and to use a MOS, bipolar, CCD And the like can be formed, and it is possible to obtain an LSI by an optimal combination of an SOI and a bulk device.

Embodiment 2 In Embodiment 1 described above, only the base of the semiconductor protrusion is exposed and covered with a mask, and the semiconductor protrusion is separated by at least insulating the base.
Specifically, the LOCOS method was used. However, in this embodiment, the semiconductor protrusion is selectively ion-implanted only into the base to insulate the base, thereby separating the protrusion. . In particular, in this embodiment, the ion implantation is performed by oxygen ion implantation. The ion implantation is performed by oblique ion implantation.

In this embodiment, after the structures of FIGS. 3 and 4 are sequentially formed in the same manner as in the first embodiment, as shown in FIG.
The semiconductor protrusion 21 is selectively ion-implanted only into its base to insulate the base. Thereby, the semiconductor protrusion 21 is separated.

That is, in this embodiment, after removing the semiconductor layer 26 at the base of the semiconductor protrusion 21 as shown in FIG. 4 of the first embodiment, ion implantation of oxygen is performed instead of performing LOCOS oxidation as shown in FIG. Performed to achieve insulation. The oxide layer constituting the insulating portion is indicated by reference numeral 25 '.

In particular, in this embodiment, oblique ion implantation I was performed. The angle of the oblique ion implantation and the amount of oxygen
It is optimally determined according to the shape and properties of the insulating region to be formed.

According to this embodiment, the projection 21 can be insulated by the existing simple technique of oblique ion implantation, which is advantageous. In other respects, the third embodiment has the same effect as the first embodiment.

In oblique ion implantation, the lower side of the nitride film sidewall 27 'may be formed slightly obliquely as shown in FIG.

Embodiment 3 In this embodiment, the base of the semiconductor protrusion is insulated by oblique ion implantation in the same manner as in Embodiment 2, but here, ion implantation of nitrogen is performed instead of oxygen. In the second embodiment,
Insulation is achieved by silicon oxide, whereas insulation is achieved by silicon nitride in this embodiment.

Also in this embodiment, the angle of oblique ion implantation and the amount of nitrogen to be implanted are optimally determined according to the shape and properties of the insulating region to be formed.

According to the present embodiment, the protrusion 21 can be insulated by the existing simple technique of oblique ion implantation, which is advantageous. In other respects, the same effects as those of the first embodiment can be obtained. Have.

Embodiment 4 In this embodiment, oxygen ions are implanted only into the base in the same manner as in Embodiment 2, but thereafter, the base is insulated with a mask in a state where only the base is exposed. And a configuration similar to that of the first embodiment is adopted.

That is, the LOCOS method and the ion implantation method are used together to perform element isolation by reliable insulation.

In addition, this embodiment can achieve the same functions and effects as the above embodiments.

Embodiment 5 This embodiment also uses the LOCOS method and the ion implantation method in combination. In this embodiment, silicon is ion-implanted, and then LOCOS oxidation is performed. The base of the semiconductor protrusion is easily oxidized by ion implantation of silicon, and is then oxidized, so that insulation is ensured by formation of a reliable oxide layer, and element isolation is performed.

This embodiment can also achieve the same effects as the above embodiments.

[0054]

According to the present invention, it is possible to form a fine element having a narrow width and good characteristics with good crystallinity. Such an element and further other semiconductor elements such as a bulk device can be formed. Can be integrated into the same semiconductor device to form an integrated circuit.

A method of manufacturing a semiconductor device in which a narrow element having good characteristics and another semiconductor element such as a bulk device can be easily formed on the same plane in a series of steps. Could be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment.

FIG. 2 is a diagram illustrating another cross section of the semiconductor device according to the first embodiment, which is a cross-sectional view taken along line AA ′ of FIG. 1;

FIG. 3 is a cross-sectional view showing a step of Example 1 (1).

FIG. 4 is a sectional view showing a step of the first embodiment (2).

FIG. 5 is a sectional view showing a step of the first embodiment (3).

FIG. 6 is a cross-sectional view showing a process of the second embodiment.

FIG. 7 is a diagram showing a conventional technique.

FIG. 8 is a diagram showing a conventional technique.

[Explanation of symbols]

 Reference Signs List 21 semiconductor protrusion (narrow semiconductor region) 21 'wide semiconductor substrate region 25, 25' insulating region 28 recess

Claims (6)

(57) [Claims] A semiconductor projection having a narrow width and a wide semiconductor substrate region separated from the projection by a concave portion is formed on a semiconductor substrate. The base of the semiconductor projection is insulated to separate the semiconductor projection. A method for manufacturing a semiconductor device in which elements are formed in the narrow semiconductor region and the wide semiconductor substrate region, wherein the semiconductor protrusion is selectively provided only at the base thereof. A method for manufacturing a semiconductor device, comprising: separating a projection by performing ion implantation to insulate the base. 2. A method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation is oxygen ion implantation. 3. The method according to claim 2 , wherein the ion implantation is nitrogen ion implantation. 4. The method according to claim 1, further comprising performing ion implantation only on the base.
4. The method of manufacturing a semiconductor device according to claim 1, wherein only the base is exposed and the base is insulated by covering with a mask. 5. The semiconductor device according to claim 1 , wherein silicon ions are implanted only into the base portion, and the base portion is exposed and covered with a mask to insulate the base portion. Production method. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the ion implantation is an oblique ion implantation.