US20150046765A1 - Data processing apparatus and data processing method - Google Patents

Data processing apparatus and data processing method Download PDF

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US20150046765A1
US20150046765A1 US14/386,830 US201414386830A US2015046765A1 US 20150046765 A1 US20150046765 A1 US 20150046765A1 US 201414386830 A US201414386830 A US 201414386830A US 2015046765 A1 US2015046765 A1 US 2015046765A1
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code
parity check
bits
check matrix
column
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Yuji Shinohara
Makiko YAMAMOTO
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Saturn Licensing LLC
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Sony Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/1177—Regular LDPC codes with parity-check matrices wherein all rows and columns have the same row weight and column weight, respectively
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
    • H03M13/356—Unequal error protection [UEP]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes

Definitions

  • the present technology relates to data processing apparatuses and data processing methods, and more specifically to data processing apparatuses and data processing methods which enable provision of, for example, LDPC codes that achieve good error-rate performance.
  • LDPC Low Density Parity Check
  • DVB Digital Video Broadcasting-S.2
  • NPL next-generation terrestrial digital broadcasting technologies
  • LDPC codes have a performance closer to the Shannon limit for larger code lengths.
  • LDPC codes have the feature of high block error probability performance, and have a further advantage in showing substantially no error floor phenomena, which is observed in the decoding characteristics of turbo codes and the like.
  • LDPC codes will now be described in more detail.
  • LDPC codes are linear codes, and may or may not be binary. The following description will be given in the context of binary LDPC codes.
  • An LDPC code has the most striking feature that it is defined by a sparse parity check matrix.
  • sparse matrix refers to a matrix having a very small number of elements of 1 (or a matrix whose elements are almost zeros).
  • FIG. 1 illustrates an example of a parity check matrix H of an LDPC code.
  • the weight of each column (column weight) (i.e., the number of 1s) is 3 and the weight of each row (row weight) is 6.
  • a generator matrix G is generated on the basis of a parity check matrix H.
  • a code word i.e., an LDPC code
  • the generator matrix G is a K ⁇ N matrix
  • the code word (or LDPC code) generated by the encoding device is received on the receiver side via a certain communication path.
  • An LDPC code can be decoded using the message passing algorithm, which is an algorithm called probabilistic decoding proposed by Gallager and which is based on belief propagation on a so-called Tanner graph with variable nodes (also referred to as “message nodes”) and check nodes.
  • the variable nodes and the check nodes will also be hereinafter referred to simply as “nodes” as appropriate.
  • FIG. 2 illustrates an LDPC code decoding procedure
  • a message output from a check node is represented by u j
  • a message output from a variable node is represented by v i .
  • step S 11 an LDPC code is received, and a message (check node message) u j is initialized to “0”.
  • a variable k of a counter for repetitive processing which takes an integer value, is initialized to “0”.
  • step S 12 a message (variable node message) v i is determined by performing computation given by Expression (1) (variable node computation) on the basis of a reception value u 0i obtained through the reception of the LDPC code.
  • a message u j is further determined by performing computation given by Expression (2) (check node computation) on the basis of the message v i .
  • d v and d c in Expressions (1) and (2) are arbitrarily selectable parameters indicating the number of is in the vertical direction (columns) and the horizontal direction (rows) of the parity check matrix H, respectively.
  • d v and d c in Expressions (1) and (2) are arbitrarily selectable parameters indicating the number of is in the vertical direction (columns) and the horizontal direction (rows) of the parity check matrix H, respectively.
  • the check node computation of Expression (2) is actually performed by creating in advance a table of a function R(v 1 , v 2 ) given by Expression (3), which is defined by one output for two inputs v 1 and v 2 , and sequentially (or recursively) using the table in the manner given by Expression (4).
  • step S 12 furthermore, the variable k is incremented by “1”. Then, the process proceeds to step S 13 .
  • step S 13 it is determined whether the variable k is larger than a certain number of times of repetitive decoding C. If it is determined in step S 13 that the variable k is not larger than C, the process returns to step S 12 , and subsequently, similar processing is repeatedly performed.
  • step S 13 If it is determined in step S 13 that the variable k is larger than C, the process proceeds to step S 14 .
  • step S 14 a message v i as a final output result of decoding is determined by performing computation given by Expression (5), and is output. Then, the LDPC code decoding process ends.
  • Expression (5) the computation of Expression (5) is performed using, unlike the variable node computation of Expression (1), the messages u j from all the edges connected to a variable node.
  • FIG. 3 illustrates an example of a parity check matrix H of a (3, 6) LDPC code (with a code rate of 1/2 and a code length of 12).
  • the column weight is 3 and the row weight is 6.
  • FIG. 4 illustrates a Tanner graph of the parity check matrix H illustrated in FIG. 3 .
  • a check node is represented by a plus “+” sign
  • a check node and a variable node correspond to each row and column of the parity check matrix H, respectively.
  • a connection between a check node and a variable node is an edge, and corresponds to an element of “1” in the parity check matrix.
  • An edge indicates that a code bit corresponding to a variable node has a constraint corresponding to a check node.
  • variable node computation and check node computation are repeatedly performed.
  • FIG. 5 illustrates variable node computation to be performed at a variable node.
  • a message v i corresponding to an edge for which calculation is to be performed is determined through the variable node computation of Expression (1) using messages u 1 and u 2 from the remaining edges connected to the variable node and also using a reception value u 0i .
  • the messages corresponding to the other edges are also determined in a similar way.
  • FIG. 6 illustrates check node computation to be performed at a check node.
  • a message u j corresponding to an edge for which calculation is to be performed is determined through the check node computation of Expression (7) using messages v 1 , v 2 , v 3 , v 4 , and v 5 from the remaining edges connected to the check node.
  • the messages corresponding to the other edges are also determined in a similar way.
  • the functions ⁇ (x) and ⁇ ⁇ 1 (x) may be implemented in hardware by using an LUT (Look Up Table), where the same LUT is used for both functions.
  • NPL 1 DVB-S.2: ETSI EN 302 307 V1.2.1 (2009-08)
  • an LDPC code is mapped to symbols (or is symbolized) of orthogonal modulation (digital modulation) such as QPSK (Quadrature Phase Shift Keying).
  • QPSK Quadrature Phase Shift Keying
  • a 4k image has a resolution of 3840 pixels horizontally and 2160 pixels vertically, providing approximately four times the pixel resolution of full high definition.
  • LDPC codes having code rates which are easily set to a somewhat large number of code rates, the number of which is greater than or equal to, for example, the number of code rates demanded for data transmission, be employed.
  • LDPC codes have high resistance to errors (i.e., high robustness), that is, good error-rate performance, no matter which code rate of LDPC code is to be employed.
  • the present technology has been made in view of the foregoing situation, and is intended to provide LDPC codes having good error-rate performance.
  • a first data processing apparatus or data processing method of the present technology includes an encoding unit configured to encode or an encoding step of encoding information bits into an LDPC (Low Density Parity Check) code having a code length of 64800 bits and a code rate of 24/30 on the basis of a parity check matrix of the LDPC code, wherein the LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table showing positions of elements of 1 in the information matrix portion in units of 360 columns, including
  • LDPC Low Density Parity Check
  • a second data processing apparatus or data processing method of the present technology includes a decoding unit configured to decode or a decoding step of decoding an LDPC (Low Density Parity Check) code having a code length of 64800 bits and a code rate of 24/30 on the basis of a parity check matrix of the LDPC code, wherein the LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table showing positions of elements of 1 in the information matrix portion in units of 360 columns, including
  • LDPC Low Density Parity Check
  • a third data processing apparatus or data processing method of the present technology includes an encoding unit configured to encode or an encoding step of encoding information bits into an LDPC (Low Density Parity Check) code having a code length of 64800 bits and a code rate of 25/30 on the basis of a parity check matrix of the LDPC code, wherein the LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table showing positions of elements of 1 in the information matrix portion in units of 360 columns, including
  • LDPC Low Density Parity Check
  • a fourth data processing apparatus or data processing method of the present technology includes a decoding unit configured to decode or a decoding step of decoding an LDPC (Low Density Parity Check) code having a code length of 64800 bits and a code rate of 25/30 on the basis of a parity check matrix of the LDPC code, wherein the LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table showing positions of elements of 1 in the information matrix portion in units of 360 columns, including
  • LDPC Low Density Parity Check
  • a fifth data processing apparatus or data processing method of the present technology includes an encoding unit configured to encode or an encoding step of encoding information bits into an LDPC (Low Density Parity Check) code having a code length of 64800 bits and a code rate of 26/30 on the basis of a parity check matrix of the LDPC code, wherein the LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table showing positions of elements of 1 in the information matrix portion in units of 360 columns, including
  • LDPC Low Density Parity Check
  • a sixth data processing apparatus or data processing method of the present technology includes a decoding unit configured to decode or a decoding step of decoding an LDPC (Low Density Parity Check) code having a code length of 64800 bits and a code rate of 26/30 on the basis of a parity check matrix of the LDPC code, wherein the LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table showing positions of elements of 1 in the information matrix portion in units of 360 columns, including
  • LDPC Low Density Parity Check
  • a seventh data processing apparatus or data processing method of the present technology includes an encoding unit configured to encode or an encoding step of encoding information bits into an LDPC (Low Density Parity Check) code having a code length of 64800 bits and a code rate of 27/30 on the basis of a parity check matrix of the LDPC code, wherein the LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table showing positions of elements of 1 in the information matrix portion in units of 360 columns, including
  • LDPC Low Density Parity Check

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US20190007061A1 (en) 2019-01-03
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US10804934B2 (en) 2020-10-13
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US20200403637A1 (en) 2020-12-24
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