US20150028384A1 - GaN TRANSISTORS WITH POLYSILICON LAYERS FOR CREATING ADDITIONAL COMPONENTS - Google Patents
GaN TRANSISTORS WITH POLYSILICON LAYERS FOR CREATING ADDITIONAL COMPONENTS Download PDFInfo
- Publication number
- US20150028384A1 US20150028384A1 US14/445,988 US201414445988A US2015028384A1 US 20150028384 A1 US20150028384 A1 US 20150028384A1 US 201414445988 A US201414445988 A US 201414445988A US 2015028384 A1 US2015028384 A1 US 2015028384A1
- Authority
- US
- United States
- Prior art keywords
- layer
- metal
- gate
- polysilicon layer
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 136
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 136
- 229910052751 metal Inorganic materials 0.000 claims abstract description 189
- 239000002184 metal Substances 0.000 claims abstract description 189
- 238000000034 method Methods 0.000 claims abstract description 42
- 239000011810 insulating material Substances 0.000 claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 claims abstract description 25
- 230000004888 barrier function Effects 0.000 claims description 57
- 238000000151 deposition Methods 0.000 claims description 24
- 238000002955 isolation Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 230000007704 transition Effects 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 4
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 4
- 230000008878 coupling Effects 0.000 claims 2
- 238000010168 coupling process Methods 0.000 claims 2
- 238000005859 coupling reaction Methods 0.000 claims 2
- 229910002704 AlGaN Inorganic materials 0.000 claims 1
- 150000002739 metals Chemical class 0.000 abstract description 36
- 239000010410 layer Substances 0.000 description 229
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 70
- 229910002601 GaN Inorganic materials 0.000 description 68
- 239000000463 material Substances 0.000 description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 230000008569 process Effects 0.000 description 11
- 239000003989 dielectric material Substances 0.000 description 10
- 239000010949 copper Substances 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 238000001878 scanning electron micrograph Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/7605—Making of isolation regions between components between components manufactured in an active substrate comprising AIII BV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
Definitions
- the present invention relates to the field of gallium nitride (GaN) devices and, more particularly, to the fabrication of GaN integrated circuits using one or more polysilicon layers to fabricate active and passive silicon devices.
- GaN gallium nitride
- Gallium nitride (GaN) semiconductor devices are increasingly desirable because of their ability to switch at high frequency, to carry large current, and to support high voltages. Development of these devices has generally been aimed at high power/high frequency applications. Devices fabricated for these types of applications are based on general device structures that exhibit high electron mobility and are referred to variously as heterojunction field effect transistors (HFET), high electron mobility transistors (HEMT), or modulation doped field effect transistors (MODFET). These types of devices can typically withstand high voltages, e.g., 30V-to-2000 Volts, while operating at high frequencies, e.g., 100 kHZ-100 GHz.
- HFET heterojunction field effect transistors
- HEMT high electron mobility transistors
- MODFET modulation doped field effect transistors
- a GaN HEMT device includes a nitride semiconductor with at least two nitride layers. Different materials formed on the semiconductor or on a buffer layer causes the layers to have different band gaps. The different material in the adjacent nitride layers also causes polarization, which contributes to a conductive two dimensional electron gas (2DEG) region near the junction of the two layers, specifically in the layer with the narrower band gap.
- 2DEG conductive two dimensional electron gas
- the nitride layers that cause polarization typically include a barrier layer of AlGaN adjacent to a layer of GaN to include the 2DEG, which allows charge to flow through the device. This barrier layer may be doped or undoped. Because the 2DEG region exists under the gate at zero gate bias, most gallium nitride devices are normally on, or depletion mode devices. If the 2DEG region is depleted, i.e. removed, below the gate at zero applied gate bias, the device can be an enhancement mode device. Enhancement mode devices are normally off and are desirable because of the added safety they provide and because they are easier to control with simple, low cost drive circuits. An enhancement mode device requires a positive bias applied at the gate in order to conduct current.
- FIGS. 1A-1H illustrate a conventional manufacturing process for fabricating an enhancement mode (normally off) GaN transistor.
- the exemplary device is formed by first depositing a number of layers on a substrate 10 , formed from silicon (Si), silicon carbide (SiC) or the like.
- a substrate 10 formed from silicon (Si), silicon carbide (SiC) or the like.
- AlN aluminum nitride
- AlGaN aluminum gallium nitride
- GaN gallium nitride
- an aluminum gallium nitride (AlGaN) barrier layer 14 is formed on the GaN layer 13 , a pGaN layer 15 is formed on the barrier layer 14 , and a gate metal 16 is formed on the pGaN layer 15 .
- AlGaN aluminum gallium nitride
- a photoresist 17 is deposited as a protecting layer on the gate metal 16 to define the gate pattern using the photoresist.
- the gate metal 16 and the pGaN material (i.e., crystal) 15 are etched with the photoresist 17 serving as the protecting layer.
- an insulating layer or film 18 is deposited and contact openings 19 A and 19 B are formed for the source and drain contacts.
- a first aluminum metal is deposited to define the metal pattern.
- the metal layer can form the source metal 20 A, the drain metal 20 B, and optionally a field plate 20 C.
- An interlayer dielectric is then deposited as shown in FIG. 1F .
- the insulator 18 is the same material as that deposited in FIG. 1C .
- vias 22 A and 22 B can be cut between metal layers as shown in FIG. 1G .
- the vias can be filled with tungsten to form a plug and a second aluminum metal layer can be deposited to form metals 21 A and 21 B.
- This step can be performed again as shown in FIG. 1H with additional vias cut 24 A and 24 B and additional metals 23 A and 23 B formed.
- a passivation layer 25 can then be deposited over the third aluminum metals 23 A and 23 B.
- FIG. 2 shows a scanning electron micrograph of the GaN structure formed by the process of FIGS. 1A-1H .
- One limitation of the process described above in FIGS. 1A-1H is that the device fabricated is a single enhancement mode device on a chip.
- a second limitation is that a GaN HEMT device, as mentioned above, uses a highly conductive electron gas (2DEG), and is therefore an n-channel transistor.
- 2DEG highly conductive electron gas
- GaN integrated circuits that include silicon active and inactive components that have otherwise been difficult to fabricate in gallium nitride.
- GaN transistor devices are disclosed herein that include polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same.
- the GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions.
- the device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.
- a method for manufacturing the GaN transistor device includes forming an EPI structure having a substrate, an AlGaN layer over the substrate, a GaN layer over the AlGaN layer, a barrier layer over the AlGaN layer, and a p-type GaN layer over the barrier layer; depositing a gate metal on the p-type GaN layer; and forming a photoresist over the gate metal and etching the gate metal and the p-type GaN layer.
- the method further includes depositing a first insulating layer; etching the first insulating layer to form a pair of contact windows in the insulating material; and forming a source metal and a drain metal in the pair of contact windows.
- a second insulating layer is deposited and a polysilicon layer is deposited on the second insulating layer.
- the manufacturing method further includes the steps of doping the polysilicon layer to form at least one n-type region and at least one p-type region in the polysilicon layer; depositing a third insulating layer and forming a first plurality of vias in the third insulating layer that are respectively coupled to the source metal, the drain metal, the at least one n-type region of the polysilicon layer and the at least one p-type region of the polysilicon layer; and forming a metal layer on the third insulating layer.
- FIGS. 1A-1H illustrate a conventional manufacturing process for fabricating an enhancement mode (normally off) GaN transistor.
- FIG. 2 illustrates shows a scanning electron micrograph of the GaN structure formed by the process of FIGS. 1A-1H .
- FIGS. 3A-3H illustrate an exemplary manufacturing process using a polysilicon layer to fabricate active and passive silicon devices in an GaN integrated circuit according to a first embodiment of the present invention.
- FIGS. 4A and 4B illustrate additional embodiments of a GaN integrated circuit according to an exemplary embodiment of the present invention.
- FIGS. 5A-5J illustrate an exemplary manufacturing process using a polysilicon layer to fabricate the devices in an GaN integrated circuit as shown in FIGS. 4A and/or 4 B.
- FIG. 6 illustrates yet another embodiment of a GaN integrated circuit according to the present invention.
- FIGS. 7A-7H illustrate an exemplary manufacturing process using a polysilicon layer to fabricate the device in an GaN integrated circuit as shown in FIG. 6 .
- FIG. 8 illustrates yet another variation of a GaN integrated circuit according to an exemplary embodiment of the present invention.
- FIGS. 9A-9I illustrate an exemplary manufacturing process using a polysilicon layer to fabricate the devices in an GaN integrated circuit as shown in FIG. 8 .
- FIGS. 3A-3H illustrate an exemplary manufacturing process using a polysilicon layer to fabricate active and passive silicon devices in an GaN integrated circuit according to a first embodiment of the present invention.
- an EPI structure includes a seed layer (e.g., aluminum nitride (AlN)) that is deposited on a substrate, formed from silicon (Si), silicon carbide (SiC) or the like. Further, one or more transition layers (e.g., aluminum gallium nitride (AlGaN)) are formed on the seed layer, and a channel layer (e.g., a gallium nitride (GaN) layer) is formed on the AlGaN layer. A barrier layer composed of aluminum gallium nitride (AlGaN), for example, is then formed on the channel layer, such that a two dimensional electron gas (2DEG) is formed at the junction between the channel layer and the barrier layer.
- a seed layer e.g., aluminum nitride (AlN)
- Si silicon
- SiC silicon carbide
- transition layers e.g., aluminum gallium nitride (AlGaN)
- a channel layer e.
- a pGaN layer is formed on the barrier layer, and a gate metal is formed on the pGaN layer.
- a photoresist is deposited as a protecting layer on the gate metal to define the gate pattern using the photoresist and the gate metal and pGaN material are etched.
- An insulating layer is then deposited and contact openings are formed in the insulating layer for the source and drain contacts.
- an aluminum metal is deposited to define the source metal, the drain metal, and optionally a field plate.
- An interlayer dielectric is then deposited on the metal contacts.
- FIG. 3A illustrates the resulting structure from these preliminary manufacturing steps.
- a substrate 110 is provided with an AlN seed layer 111 , an AlGaN layer 112 , a channel layer 113 comprised of GaN or the like, and an AlGaN barrier layer 114 formed thereon, from bottom layer to top layer.
- a gate contact comprised of the pGaN layer 115 and the gate metal 116 is formed on the AlGaN barrier layer 114 , as well as source metal 120 A, drain metal 120 B and field plate 120 C.
- an insulator 118 is disposed over the metal contacts and barrier layer.
- the gate contact/structure is formed using a patterned photoresist over the pGaN layer 115 and the gate metal 116 in the exemplary embodiment (as described above), the gate contact/structure can be formed using alternative methods as would be understood to one skilled in the art.
- the gate structure can be a recessed gate formed in the barrier layer 114 , and F-implanted (fluorine implanted) gate, or any other method for forming an enhancement mode device.
- a layer of polysilicon 121 is deposited on the insulating layer 118 and impurities are implanted to define regions with p-type doping, n-type doping and/or no doping. These regions will form the basis for p-n diodes, npn and pnp transistors, resistors, capacitors, and other active and passive elements.
- the polysilicon layer 121 includes an n-type region 121 A, a p-type region 121 B, and an undoped regions 121 C.
- a contact photo mask is then used to pattern and etch the polysilicon layer 121 as shown in FIG. 3C .
- an insulating layer 122 is then deposited over the polysilicon layer 121 .
- Vias 123 A- 123 E are then formed in the insulating layer 122 and insulating layer 118 (collectively shown as insulating layer 118 in FIG. 3E ).
- via 123 A connects source metal 120 A
- via 123 B connects drain metal 120 B
- via 123 C connects n-type region 121 A
- via 123 D connects p-type region 121 B
- via 123 E connects the undoped region 121 C.
- tungsten (W) or copper (Cu) plug technologies can be applied to the filling of smaller, higher aspect ratio vias 123 A- 123 E, while utilizing thin layers of TiN in a range of 0.01 to 0.1 ⁇ m thick for contacting the regions of the polysilicon layer 121 .
- vias are used in the exemplary embodiment, the connection to the metal and polysilicon can be done in many ways common in the industry.
- a metal layer is deposited to create interconnects, thereby adding silicon active and passive components to the GaN transistor.
- a metal layer 124 A electrically couples vias 123 A and 123 C and a second metal layer 124 B electrically couples via 123 B, 123 D, and 123 E.
- additional vias 125 A and 125 B and additional metal layers 126 A and 126 B can also be formed to the device as illustrated in FIG. 3G .
- a second polysilicon layer can be formed as shown in FIG. 3H .
- the second polysilicon layer 128 can be added to form n-channel and p-channel MOSFETs.
- FIG. 3H shows interconnects to two polysilicon layers 121 and 128 .
- the drain and source electrodes of a MOSFET are defined in polysilicon layers 121 and the gate electrode is defined in polysilicon layer 128 . As shown in both FIGS.
- the top-gate polysilicon device includes source and drain contacts that are coupled to the source and drain of the GaN FET disposed on barrier layer 114 .
- the source and drain contacts of the polysilicon FET are not coupled to the GaN FET, but instead left open for external connections, e.g., one or both of them could be connected to a metal interconnected and/or connected externally.
- one of either the source and drain contacts could be coupled to the GaN FET while the other contact could be connected externally.
- an n-channel and/or p-channel MOS device can be added by oxidizing the polysilicon and adding a metal or polysilicon gate electrode.
- multiple polysilicon layers can be added to create additional components such as poly-poly capacitors as well as the gates to polysilicon MOSFETs.
- silicon components can be used to create gate over voltage protection for the GaN transistor.
- the polysilicon can be used to create drain-source overvoltage protection for the GaN transistor and/or to create CMOS components that can be used in conjunction with the GaN transistor on the same chip.
- FIGS. 4A and 4B illustrate additional embodiments of a GaN integrated circuit according to an exemplary embodiment of the present invention.
- FIG. 4A illustrates a GaN integrated circuit having a bottom gate polysilicon device structure.
- the GaN device is formed on a substrate 211 , one or more transistor layers 212 (e.g., an AlN seed layer), a buffer layer 213 (e.g., an AlGaN layer), a channel layer 214 (e.g., GaN) and an AlGaN barrier layer 215 .
- transistor layers 212 e.g., an AlN seed layer
- a buffer layer 213 e.g., an AlGaN layer
- a channel layer 214 e.g., GaN
- AlGaN barrier layer 215 AlGaN barrier layer
- a pGaN layer 216 and gate metal 217 are formed on the barrier layer 215 and form the gate structure.
- Source and drain metals 220 and 221 are formed on the barrier layer 215 with vias 228 and 229 electrically connecting the source and drain metals 220 and 221 to metal contacts 232 and 233 , respectively.
- an isolation region 218 is formed by ion implantation or etching in the barrier layer 215 , the channel layer 214 and extending into the buffer layer 213 . The isolation region formed in the barrier layer and the channel layer electrically isolates a first portion of the 2DEG region from a second portion of the 2DEG region.
- the device further includes an insulating material 219 that electrically insulates and protects the device metals.
- a bottom gate 222 of the polysilicon FET is formed in the insulating material. It is noted that the bottom gate 222 can be a metal, polysilicon or other conductive material. It should be appreciated that the gate structure is formed above one portion of the 2DEG region while the bottom or back gate 222 is formed above a second portion of the 2DEG region that is isolated from the first region.
- a polysilicon layer is formed above the bottom gate.
- the polysilicon layer can comprise an n-type region 223 , a p-type region 224 and an n-type region 225 (i.e., an NPN layer for the source, gate and drain of the device), although it should be appreciated that the regions can be reversed to form a PNP layer.
- Vias 226 and 227 couple the doped regions 223 and 225 , respectively to metal contacts 230 and 231 .
- the device shown in FIG. 4A includes a bottom gate structure for a polysilicon FET that is disposed in an area of the circuit isolated from the active cells of the GaN FET.
- FIG. 4B illustrates an alternative embodiment of the device illustrated in FIG. 4A .
- the layers and components of the device in FIG. 4B are the same as 4 A and will not be repeated herein.
- the device shown in FIG. 4B differs in that the polysilicon FET 222 is formed in the active region of the circuit rather than the isolated region as it is disposed in the device shown in FIG. 4A .
- FIGS. 5A-5J illustrate an exemplary manufacturing process using a polysilicon layer to fabricate the devices in an GaN integrated circuit as shown in FIGS. 4A and/or 4 B. All process flows can be used to form bottom gate polysilicon FETs in both the active device area ( FIG. 4B ) or in the isolation area ( FIG. 4A ). A back gate formed by the polysilicon/gate metal prevents the effect of the 2DEG potential on the polysilicon FET.
- FIG. 5A illustrates an EPI structure, including, from bottom to top, silicon substrate 211 , transition layers 212 , a buffer material 213 (e.g., AlGaN), a channel layer 214 (e.g., GaN), and an barrier material 215 (e.g., AlGaN. Furthermore, a p-type GaN material 216 is formed on the barrier material 215 and a gate metal 217 is formed (i.e., deposited or grown) on the p-type GaN material 216 .
- a buffer material 213 e.g., AlGaN
- a channel layer 214 e.g., GaN
- barrier material 215 e.g., AlGaN.
- a p-type GaN material 216 is formed on the barrier material 215 and a gate metal 217 is formed (i.e., deposited or grown) on the p-type GaN material 216 .
- Isolation region 218 can be formed by covering the portion of device layer 215 and then etching down the exposed layers, at least below the channel layer 214 . The etched region can then be filled with oxide or other suitable isolating materials.
- the insulating material is etched using a contact photo mask to form contact openings and contact metals are deposited to form the source metal 120 , drain metal 121 , and optionally a field plate.
- an insulating material is then deposited on the structure, which is again shown as insulating material 119 in FIG. 5C .
- a bottom gate metal 222 is then deposited on the insulating material 219 as shown FIG. 5D and then etched as shown in FIG. 5E .
- the etched gate metal forms the bottom gate for the polysilicon FET as discussed above.
- FIG. 5F a gate insulator is deposited for the polysilicon FET.
- the gate insulator is illustrated as insulating material 219 .
- a polysilicon layer 240 is then deposited as shown in FIG. 5G and then etched as shown in FIG. 5H .
- the polysilicon layer 240 is etched such that the remaining portion of the layer is formed over the gate metal 222 .
- a step of masking and ion implanting the polysilicon layer is performed to form NPN or PNP layers.
- ion implanting of the polysilicon layer can result in an n-type region 223 , a p-type region 224 and an n-type region 225 (i.e., an NPN layer for the source, gate and drain of the device) or, alternatively, a PNP layer.
- an additional dielectric material is deposited (again shown as dielectric material 219 ), a plurality of vias are formed in the dielectric material 219 and filled with a conductive material such as tungsten (W), copper (Cu) or the like, and metal contacts are formed on top of the dielectric material 219 .
- vias 226 and 227 electrically coupled the doped regions 223 and 225 , respectively to metal contacts 230 and 231
- via 228 electrically couples the source metal 220 to the metal contact 232
- via 229 electrically couples the drain metal 221 to metal contact 233 .
- additional metal layers can be formed in a similar manner as that disclosed in the first embodiment, and, in particular, in FIG. 3G .
- FIG. 6 illustrates yet another embodiment of a GaN integrated circuit according to an exemplary embodiment of the present invention.
- the circuit illustrated in FIG. 6 is similar design to the GaN integrated circuit having a bottom gate polysilicon device structure as illustrated in FIG. 4A .
- FIG. 6 differs in that the bottom gate is formed using the pGaN layer and gate metal as the gate layer for the polysilicon FET, which effectively reduces the number of masks during fabrication as will become apparent from the exemplary process described below with respect to FIGS. 7A-7H .
- the GaN is formed on a substrate 311 , one or more transistor layers 312 (e.g., an AlN seed layer), a buffer layer 313 (e.g., an AlGaN layer), a channel layer 314 and an AlGaN barrier layer 315 . Moreover, a pGaN layer 316 and gate metal 317 are formed on the barrier layer 315 . An additional region of the pGaN layer 318 and gate metal 319 is formed on the barrier in the region isolated by isolation region 324 . The pGaN layer 318 and gate metal 319 form the gate layer for the polysilicon FET.
- transistor layers 312 e.g., an AlN seed layer
- a buffer layer 313 e.g., an AlGaN layer
- a channel layer 314 e.g., an AlGaN barrier layer
- a pGaN layer 316 and gate metal 317 are formed on the barrier layer 315 .
- source and drain metals 325 and 326 are formed on the barrier layer 315 with vias 328 and 327 electrically connecting the source and drain metals 325 and 326 to metal contacts 333 and 334 , respectively.
- an isolation region 324 is formed by ion implantation or etching in the buffer barrier layer 315 , the channel layer 314 and extending into the buffer layer 313 .
- the device further includes an insulating material 320 that electrically insulates and protects the device metals.
- a polysilicon layer is formed above the bottom gate 318 , 319 .
- the polysilicon layer can comprise an n-type region 321 , a p-type region 322 and an n-type region 323 (i.e., an NPN layer for the source, gate and drain of the device), although it should be appreciated that the regions can be reversed to form a PNP layer.
- Vias 330 and 329 couple the doped regions 321 and 323 , respectively to metal contacts 331 and 333 .
- the device shown in FIG. 6 includes a bottom gate structure for a polysilicon FET that is disposed in an area of the circuit isolated from the active cells of the GaN FET.
- the same structure can be formed with the gate structure for the polysilicon FET in the active region of the circuit (similar to the embodiment of FIG. 4B ), rather than in the isolated region as it is disposed in the device shown in FIG. 6 .
- FIGS. 7A-7H illustrate an exemplary manufacturing process using a polysilicon layer to fabricate the device in an GaN integrated circuit as shown in FIG. 6 . All process flows can be used to form bottom gate polysilicon FETs in both the isolation area ( FIG. 6 ) or the active region (not shown). A back gate formed by the polysilicon/gate metal prevents the effect of the 2DEG potential on the polysilicon FET.
- FIG. 7A illustrates an EPI structure, including, from bottom to top, silicon substrate 311 , transition layers 312 , a GaN buffer material 313 , a channel layer 314 , and an AlGaN barrier material 315 . Furthermore, a p-type GaN material 316 , 317 is formed on the barrier material 315 and a gate metal 317 , 319 is formed (i.e., deposited or grown) on the p-type GaN material 316 . Although not shown, these structures are formed by depositing a photoresist and etching the gate metal 317 , 319 and the p-type GaN material 316 , 318 using any known technique, e.g., plasma etching. After these structures are formed, an insulating layer 320 is deposited.
- a polysilicon layer 340 is deposited on the insulating layer 320 , which is then etched as shown in FIG. 7C .
- a step of masking and ion implanting the remaining polysilicon layer 340 is performed to form NPN or PNP layers.
- ion implanting of the polysilicon layer can result in an n-type region 321 , a p-type region 322 and an n-type region 323 (i.e., an NPN layer for the source, gate and drain of the device) or, alternatively, a PNP layer.
- an isolation region 324 is then formed by covering the portion of device layer and then etching down the exposed layers, at least below the channel layer 314 .
- the etched region can then be filled with oxide or other suitable isolating materials.
- isolation region 324 can be formed using any other techniques as would be understood to one skilled in the art and further that isolation region 324 can be formed at different stages in the process, for example, before the insulating layer 320 is deposited in step 7 A.
- the insulating material 320 is etched using a contact photo mask to form contact openings and contact metals are deposited to form the source metal 325 , drain metal 326 , and optionally a field plate.
- An additional insulating layer 320 is deposited ( FIG. 7G ) before a plurality of vias are formed in the dielectric material 320 and filled with a conductive material such as tungsten (W), copper (Cu) or the like, and metal contacts are formed on top of the dielectric material 320 .
- a conductive material such as tungsten (W), copper (Cu) or the like
- vias 330 and 329 electrically coupled the doped regions 321 and 323 , respectively to metal contacts 331 and 332
- via 328 electrically couples the source metal 325 to the metal contact 333
- via 327 electrically couples the drain metal 326 to metal contact 334 .
- additional metal layers can be formed in a similar manner as that disclosed in the first embodiment, and, in particular, in FIG. 3G .
- FIG. 8 illustrates yet another variation of a GaN integrated circuit according to an exemplary embodiment of the present invention.
- the circuit illustrated in FIG. 8 is a similar design to the GaN integrated circuit having a bottom gate polysilicon device structure as illustrated in FIG. 4A .
- FIG. 8 differs in that a metal layer that is normally used as a barrier layer for Metal 1 is used as the bottom gate for the polysilicon FET, which effectively reduces the number of masks during fabrication as will become apparent from the exemplary process described below with respect to FIGS. 9A-9I .
- a GaN integrated circuit includes a bottom gate polysilicon device structure and is formed on a substrate 411 , one or more transistor layers 412 (e.g., an AlN seed layer), a buffer layer 413 (e.g., an AlGaN layer), a channel layer 414 and an AlGaN barrier layer 415 .
- transistor layers 412 e.g., an AlN seed layer
- buffer layer 413 e.g., an AlGaN layer
- channel layer 414 and an AlGaN barrier layer 415 are similar to those of the EPI structure described above with reference to the embodiments discussed above.
- a pGaN layer 416 and gate metal 417 are formed on the barrier layer 415 .
- Source and drain metals 422 and 423 are formed on the barrier layer 415 with vias 428 and 427 electrically connecting the source and drain metals 422 and 423 to metal contacts 433 and 434 , respectively.
- an isolation region 418 is formed by ion implantation or etching in the buffer barrier layer 415 , the channel layer 414 and extending into the buffer layer 413 .
- the device further includes an insulating material 419 that electrically insulates and protects the device metals.
- a bottom gate 421 of the polysilicon FET is formed in the insulating material.
- the bottom gate 421 can be a metal, polysilicon or other conductive material.
- the metal layer extends under the source and drain metals 422 and 423 and is denoted as 420 .
- the device in FIG. 8 further includes a polysilicon layer that is formed above the bottom gate 421 .
- the polysilicon layer can comprise an n-type region 424 , a p-type region 425 and an n-type region 426 (i.e., an NPN layer for the source, gate and drain of the device), although it should be appreciated that the regions can be reversed to form a PNP layer.
- Vias 430 and 429 couple the doped regions 424 and 426 , respectively to metal contacts 431 and 432 .
- the device shown in FIG. 8 includes a bottom gate structure for a polysilicon FET that is disposed in an area of the circuit isolated from the active cells of the GaN FET.
- the bottom gate of the polysilicon FET 421 can be formed in the active region of the circuit rather than the isolated region as it is disposed in the device shown in FIG. 8 .
- FIGS. 9A-9I illustrate an exemplary manufacturing process using a polysilicon layer to fabricate the devices in an GaN integrated circuit as shown in FIG. 8 . All process flows can be used to form bottom gate polysilicon FETs in both the active device area (not shown) or in the isolation area ( FIG. 8 ). A back gate formed by the polysilicon/gate metal prevents the effect of the 2DEG potential on the polysilicon FET.
- an EPI structure is formed that includes, from bottom to top, silicon substrate 411 , transition layers 412 , a GaN buffer material 413 , a channel layer 414 , and an AlGaN barrier material 415 . Furthermore, a p-type GaN material 416 is formed on the barrier material 415 and a gate metal 417 is formed (i.e., deposited or grown) on the p-type GaN material 416 . After a photoresist is deposited and the gate metal 417 and the p-type GaN material 416 are etched, an isolation region 418 is then formed and an insulating material 419 is deposited over the EPI structure. Isolation region 418 can be formed by covering the portion of device layer 415 and then etching down the exposed layers, at least below the channel layer 414 . The etched region can then be filled with oxide or other suitable isolating materials.
- FIG. 9C illustrates the next step in which the barrier metal 440 and the insulating material 419 are etched to form contact openings and a contact metal (i.e., Metal 1 ) 441 is deposited to form the source metal, drain metal, and optionally a field plate.
- a contact metal i.e., Metal 1
- FIG. 9D the metal layer 441 and barrier metal 440 are etched for form the source metal 422 , drain metal 423 and barrier metal layer 421 for the polysilicon FET.
- the metal layer is etched over the barrier metal layer 421 , but is not etched where the source metal 422 and drain metal 423 are to be formed. In other words, the manufacturing processes must selectively determine which metal layers are to be etched.
- an insulating material is then deposited on the structure, which is again shown as insulating material 419 in FIG. 9E , and a polysilicon layer 442 is deposited on the insulating material 419 as shown in FIG. 9F .
- the polysilicon layer 442 is then etched using a contact photo mask such that the remaining portion of the layer is formed over the gate metal 421 as shown in FIG. 9G .
- a step of masking and ion implanting the polysilicon layer 442 is performed to form NPN or PNP layers.
- ion implanting of the polysilicon layer can result in an n-type region 424 , a p-type region 425 and an n-type region 426 (i.e., an NPN layer for the source, gate and drain of the device) or, alternatively, a PNP layer.
- an additional dielectric material is deposited (again shown as dielectric material 419 ), a plurality of vias are formed in the dielectric material 419 and filled with a conductive material such as tungsten (W), copper (Cu) or the like, and metal contacts are formed on top of the dielectric material 219 .
- vias 430 and 429 electrically coupled the doped regions 424 and 426 , respectively to metal contacts 431 and 432
- via 428 electrically couples the source metal 422 to the metal contact 433
- via 427 electrically couples the drain metal 423 to metal contact 434 .
- additional metal layers can be formed in a similar manner as that disclosed in the first embodiment, and, in particular, in FIG. 3G .
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Junction Field-Effect Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
- This application claims the benefit of U.S. Provisional Application No. 61/859,519, filed on Jul. 29, 2013, and U.S. Provisional Application No. 61/978,014, filed on Apr. 10, 2014, the entire contents of each of which are hereby incorporated by reference.
- 1. Field of the Invention
- The present invention relates to the field of gallium nitride (GaN) devices and, more particularly, to the fabrication of GaN integrated circuits using one or more polysilicon layers to fabricate active and passive silicon devices.
- 2. Description of the Related Art
- Gallium nitride (GaN) semiconductor devices are increasingly desirable because of their ability to switch at high frequency, to carry large current, and to support high voltages. Development of these devices has generally been aimed at high power/high frequency applications. Devices fabricated for these types of applications are based on general device structures that exhibit high electron mobility and are referred to variously as heterojunction field effect transistors (HFET), high electron mobility transistors (HEMT), or modulation doped field effect transistors (MODFET). These types of devices can typically withstand high voltages, e.g., 30V-to-2000 Volts, while operating at high frequencies, e.g., 100 kHZ-100 GHz.
- A GaN HEMT device includes a nitride semiconductor with at least two nitride layers. Different materials formed on the semiconductor or on a buffer layer causes the layers to have different band gaps. The different material in the adjacent nitride layers also causes polarization, which contributes to a conductive two dimensional electron gas (2DEG) region near the junction of the two layers, specifically in the layer with the narrower band gap.
- The nitride layers that cause polarization typically include a barrier layer of AlGaN adjacent to a layer of GaN to include the 2DEG, which allows charge to flow through the device. This barrier layer may be doped or undoped. Because the 2DEG region exists under the gate at zero gate bias, most gallium nitride devices are normally on, or depletion mode devices. If the 2DEG region is depleted, i.e. removed, below the gate at zero applied gate bias, the device can be an enhancement mode device. Enhancement mode devices are normally off and are desirable because of the added safety they provide and because they are easier to control with simple, low cost drive circuits. An enhancement mode device requires a positive bias applied at the gate in order to conduct current.
-
FIGS. 1A-1H illustrate a conventional manufacturing process for fabricating an enhancement mode (normally off) GaN transistor. As shown inFIG. 1A , the exemplary device is formed by first depositing a number of layers on asubstrate 10, formed from silicon (Si), silicon carbide (SiC) or the like. In particular, an aluminum nitride (AlN)seed layer 11 is deposited on thesubstrate 10, an aluminum gallium nitride (AlGaN)layer 12 is formed on theseed layer 11, and a gallium nitride (GaN)layer 13 is formed on theAlGaN layer 12. Furthermore, an aluminum gallium nitride (AlGaN)barrier layer 14 is formed on theGaN layer 13, apGaN layer 15 is formed on thebarrier layer 14, and agate metal 16 is formed on thepGaN layer 15. As further shown inFIG. 1A , aphotoresist 17 is deposited as a protecting layer on thegate metal 16 to define the gate pattern using the photoresist. - Next, as shown in
FIG. 1B , thegate metal 16 and the pGaN material (i.e., crystal) 15 are etched with thephotoresist 17 serving as the protecting layer. As then shown inFIGS. 1C and 1D , an insulating layer orfilm 18 is deposited andcontact openings FIG. 1E , the metal layer can form thesource metal 20A, thedrain metal 20B, and optionally afield plate 20C. An interlayer dielectric is then deposited as shown inFIG. 1F . In this example, theinsulator 18 is the same material as that deposited inFIG. 1C . - Once the interlayer dielectric 18 is deposited,
vias FIG. 1G . The vias can be filled with tungsten to form a plug and a second aluminum metal layer can be deposited to formmetals FIG. 1H with additional vias cut 24A and 24B andadditional metals passivation layer 25 can then be deposited over thethird aluminum metals FIG. 2 shows a scanning electron micrograph of the GaN structure formed by the process ofFIGS. 1A-1H . - One limitation of the process described above in
FIGS. 1A-1H is that the device fabricated is a single enhancement mode device on a chip. A second limitation is that a GaN HEMT device, as mentioned above, uses a highly conductive electron gas (2DEG), and is therefore an n-channel transistor. However, it is difficult to make a p-channel transistor due to very poor hole mobility in gallium nitride. Moreover, it is also difficult to fabricate other types of silicon devices in gallium nitride. - Accordingly, it would be desirable to have a process for forming GaN integrated circuits that include silicon active and inactive components that have otherwise been difficult to fabricate in gallium nitride.
- GaN transistor devices are disclosed herein that include polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.
- A method for manufacturing the GaN transistor device includes forming an EPI structure having a substrate, an AlGaN layer over the substrate, a GaN layer over the AlGaN layer, a barrier layer over the AlGaN layer, and a p-type GaN layer over the barrier layer; depositing a gate metal on the p-type GaN layer; and forming a photoresist over the gate metal and etching the gate metal and the p-type GaN layer. The method further includes depositing a first insulating layer; etching the first insulating layer to form a pair of contact windows in the insulating material; and forming a source metal and a drain metal in the pair of contact windows. Next, a second insulating layer is deposited and a polysilicon layer is deposited on the second insulating layer. After the polysilicon layer is deposited, the manufacturing method further includes the steps of doping the polysilicon layer to form at least one n-type region and at least one p-type region in the polysilicon layer; depositing a third insulating layer and forming a first plurality of vias in the third insulating layer that are respectively coupled to the source metal, the drain metal, the at least one n-type region of the polysilicon layer and the at least one p-type region of the polysilicon layer; and forming a metal layer on the third insulating layer.
- The features, objects, and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:
-
FIGS. 1A-1H illustrate a conventional manufacturing process for fabricating an enhancement mode (normally off) GaN transistor. -
FIG. 2 illustrates shows a scanning electron micrograph of the GaN structure formed by the process ofFIGS. 1A-1H . -
FIGS. 3A-3H illustrate an exemplary manufacturing process using a polysilicon layer to fabricate active and passive silicon devices in an GaN integrated circuit according to a first embodiment of the present invention. -
FIGS. 4A and 4B illustrate additional embodiments of a GaN integrated circuit according to an exemplary embodiment of the present invention. -
FIGS. 5A-5J illustrate an exemplary manufacturing process using a polysilicon layer to fabricate the devices in an GaN integrated circuit as shown inFIGS. 4A and/or 4B. -
FIG. 6 illustrates yet another embodiment of a GaN integrated circuit according to the present invention. -
FIGS. 7A-7H illustrate an exemplary manufacturing process using a polysilicon layer to fabricate the device in an GaN integrated circuit as shown inFIG. 6 . -
FIG. 8 illustrates yet another variation of a GaN integrated circuit according to an exemplary embodiment of the present invention. -
FIGS. 9A-9I illustrate an exemplary manufacturing process using a polysilicon layer to fabricate the devices in an GaN integrated circuit as shown inFIG. 8 . - In the following detailed description, reference is made to certain embodiments. These embodiments are described with sufficient detail to enable those skilled in the art to practice them. It is to be understood that other embodiments may be employed and that various structural, logical, and electrical changes may be made as well as variations in the materials used to form the various layers of the integrated circuits disclosed herein. The combinations of features disclosed in the following detailed description may not be necessary to practice the teachings in the broadest sense, and are instead taught merely to describe particularly representative examples of the present teachings.
-
FIGS. 3A-3H illustrate an exemplary manufacturing process using a polysilicon layer to fabricate active and passive silicon devices in an GaN integrated circuit according to a first embodiment of the present invention. - The initial steps of the first exemplary embodiment of the manufacturing process described herein employ the same or similar steps as those described above with respect to
FIGS. 1A-1F of a conventional fabrication technique of a GaN transistor. In particular, an EPI structure includes a seed layer (e.g., aluminum nitride (AlN)) that is deposited on a substrate, formed from silicon (Si), silicon carbide (SiC) or the like. Further, one or more transition layers (e.g., aluminum gallium nitride (AlGaN)) are formed on the seed layer, and a channel layer (e.g., a gallium nitride (GaN) layer) is formed on the AlGaN layer. A barrier layer composed of aluminum gallium nitride (AlGaN), for example, is then formed on the channel layer, such that a two dimensional electron gas (2DEG) is formed at the junction between the channel layer and the barrier layer. - In the exemplary embodiment, to form the gate a pGaN layer is formed on the barrier layer, and a gate metal is formed on the pGaN layer. Next, a photoresist is deposited as a protecting layer on the gate metal to define the gate pattern using the photoresist and the gate metal and pGaN material are etched. An insulating layer is then deposited and contact openings are formed in the insulating layer for the source and drain contacts. Next, an aluminum metal is deposited to define the source metal, the drain metal, and optionally a field plate. An interlayer dielectric is then deposited on the metal contacts.
-
FIG. 3A illustrates the resulting structure from these preliminary manufacturing steps. As shown, asubstrate 110 is provided with anAlN seed layer 111, anAlGaN layer 112, achannel layer 113 comprised of GaN or the like, and anAlGaN barrier layer 114 formed thereon, from bottom layer to top layer. Furthermore, a gate contact comprised of thepGaN layer 115 and thegate metal 116 is formed on theAlGaN barrier layer 114, as well assource metal 120A, drainmetal 120B andfield plate 120C. Furthermore, aninsulator 118 is disposed over the metal contacts and barrier layer. It is noted that while the gate contact/structure is formed using a patterned photoresist over thepGaN layer 115 and thegate metal 116 in the exemplary embodiment (as described above), the gate contact/structure can be formed using alternative methods as would be understood to one skilled in the art. For example, the gate structure can be a recessed gate formed in thebarrier layer 114, and F-implanted (fluorine implanted) gate, or any other method for forming an enhancement mode device. - Next, as shown in
FIG. 3B , a layer ofpolysilicon 121 is deposited on the insulatinglayer 118 and impurities are implanted to define regions with p-type doping, n-type doping and/or no doping. These regions will form the basis for p-n diodes, npn and pnp transistors, resistors, capacitors, and other active and passive elements. In the example shown inFIG. 3 , thepolysilicon layer 121 includes an n-type region 121A, a p-type region 121B, and anundoped regions 121C. A contact photo mask is then used to pattern and etch thepolysilicon layer 121 as shown inFIG. 3C . - Next, as shown in
FIG. 3D , an insulatinglayer 122 is then deposited over thepolysilicon layer 121.Vias 123A-123E are then formed in the insulatinglayer 122 and insulating layer 118 (collectively shown as insulatinglayer 118 inFIG. 3E ). In particular, via 123A connectssource metal 120A, via 123B connectsdrain metal 120B, via 123C connects n-type region 121A, via 123D connects p-type region 121B, and via 123E connects theundoped region 121C. In the exemplary embodiment, tungsten (W) or copper (Cu) plug technologies can be applied to the filling of smaller, higher aspect ratio vias 123A-123E, while utilizing thin layers of TiN in a range of 0.01 to 0.1 μm thick for contacting the regions of thepolysilicon layer 121. It should be appreciated that although vias are used in the exemplary embodiment, the connection to the metal and polysilicon can be done in many ways common in the industry. - Turning to
FIG. 3F , a metal layer is deposited to create interconnects, thereby adding silicon active and passive components to the GaN transistor. In particular, as shown in the exemplary embodiment, ametal layer 124A electrically couples vias 123A and 123C and asecond metal layer 124B electrically couples via 123B, 123D, and 123E. - In one refinement,
additional vias additional metal layers FIG. 3G . Alternatively or in addition thereto, a second polysilicon layer can be formed as shown inFIG. 3H . In particular, thesecond polysilicon layer 128 and coupled to anothermetal layer 126 by via 127. In the exemplary embodiment, thesecond polysilicon layer 128 can be added to form n-channel and p-channel MOSFETs.FIG. 3H shows interconnects to twopolysilicon layers polysilicon layers 121 and the gate electrode is defined inpolysilicon layer 128. As shown in bothFIGS. 3G and 3H , the top-gate polysilicon device includes source and drain contacts that are coupled to the source and drain of the GaN FET disposed onbarrier layer 114. It is reiterated that in an alternative embodiment, the source and drain contacts of the polysilicon FET are not coupled to the GaN FET, but instead left open for external connections, e.g., one or both of them could be connected to a metal interconnected and/or connected externally. Yet further, one of either the source and drain contacts could be coupled to the GaN FET while the other contact could be connected externally. These variations of the integrated device are contemplated by the disclosure herein and can be manufactured using the methods described inFIGS. 3A-3F with appropriate variations thereof. - In addition, it should be appreciated that many variations and modifications can be made to the exemplary manufacturing method illustrated in
FIGS. 3A-3H . For example, as shown inFIG. 3H , an n-channel and/or p-channel MOS device can be added by oxidizing the polysilicon and adding a metal or polysilicon gate electrode. Moreover, multiple polysilicon layers can be added to create additional components such as poly-poly capacitors as well as the gates to polysilicon MOSFETs. Further, silicon components can be used to create gate over voltage protection for the GaN transistor. Finally, the polysilicon can be used to create drain-source overvoltage protection for the GaN transistor and/or to create CMOS components that can be used in conjunction with the GaN transistor on the same chip. -
FIGS. 4A and 4B illustrate additional embodiments of a GaN integrated circuit according to an exemplary embodiment of the present invention. In particular,FIG. 4A illustrates a GaN integrated circuit having a bottom gate polysilicon device structure. As shown, the GaN device is formed on asubstrate 211, one or more transistor layers 212 (e.g., an AlN seed layer), a buffer layer 213 (e.g., an AlGaN layer), a channel layer 214 (e.g., GaN) and anAlGaN barrier layer 215. These layers are similar to the structure described about with reference to the first embodiment. As noted above, a 2DEG region is formed at the junction between thechannel layer 214 and thebarrier layer 215. - As further shown, a
pGaN layer 216 andgate metal 217 are formed on thebarrier layer 215 and form the gate structure. Source and drainmetals barrier layer 215 withvias metals metal contacts isolation region 218 is formed by ion implantation or etching in thebarrier layer 215, thechannel layer 214 and extending into thebuffer layer 213. The isolation region formed in the barrier layer and the channel layer electrically isolates a first portion of the 2DEG region from a second portion of the 2DEG region. The device further includes an insulatingmaterial 219 that electrically insulates and protects the device metals. As shown, abottom gate 222 of the polysilicon FET is formed in the insulating material. It is noted that thebottom gate 222 can be a metal, polysilicon or other conductive material. It should be appreciated that the gate structure is formed above one portion of the 2DEG region while the bottom or backgate 222 is formed above a second portion of the 2DEG region that is isolated from the first region. - Furthermore, a polysilicon layer is formed above the bottom gate. In particular, the polysilicon layer can comprise an n-
type region 223, a p-type region 224 and an n-type region 225 (i.e., an NPN layer for the source, gate and drain of the device), although it should be appreciated that the regions can be reversed to form a PNP layer.Vias doped regions metal contacts FIG. 4A includes a bottom gate structure for a polysilicon FET that is disposed in an area of the circuit isolated from the active cells of the GaN FET. -
FIG. 4B illustrates an alternative embodiment of the device illustrated inFIG. 4A . The layers and components of the device inFIG. 4B are the same as 4A and will not be repeated herein. The device shown inFIG. 4B differs in that thepolysilicon FET 222 is formed in the active region of the circuit rather than the isolated region as it is disposed in the device shown inFIG. 4A . -
FIGS. 5A-5J illustrate an exemplary manufacturing process using a polysilicon layer to fabricate the devices in an GaN integrated circuit as shown inFIGS. 4A and/or 4B. All process flows can be used to form bottom gate polysilicon FETs in both the active device area (FIG. 4B ) or in the isolation area (FIG. 4A ). A back gate formed by the polysilicon/gate metal prevents the effect of the 2DEG potential on the polysilicon FET. -
FIG. 5A illustrates an EPI structure, including, from bottom to top,silicon substrate 211, transition layers 212, a buffer material 213 (e.g., AlGaN), a channel layer 214 (e.g., GaN), and an barrier material 215 (e.g., AlGaN. Furthermore, a p-type GaN material 216 is formed on thebarrier material 215 and agate metal 217 is formed (i.e., deposited or grown) on the p-type GaN material 216. After a photoresist is deposited and thegate metal 217 and the p-type GaN material 216 are etched by any known technique, e.g., plasma etching, anisolation region 218 is then formed, an insulatingmaterial 219 is deposited over the EPI structure.Isolation region 218 can be formed by covering the portion ofdevice layer 215 and then etching down the exposed layers, at least below thechannel layer 214. The etched region can then be filled with oxide or other suitable isolating materials. - Next, as shown in
FIG. 5B , the insulating material is etched using a contact photo mask to form contact openings and contact metals are deposited to form the source metal 120,drain metal 121, and optionally a field plate. As before, an insulating material is then deposited on the structure, which is again shown as insulating material 119 inFIG. 5C . Abottom gate metal 222 is then deposited on the insulatingmaterial 219 as shownFIG. 5D and then etched as shown inFIG. 5E . The etched gate metal forms the bottom gate for the polysilicon FET as discussed above. - The manufacturing process continues to
FIG. 5F in which a gate insulator is deposited for the polysilicon FET. The gate insulator is illustrated as insulatingmaterial 219. Next, apolysilicon layer 240 is then deposited as shown inFIG. 5G and then etched as shown inFIG. 5H . In the exemplary embodiment, thepolysilicon layer 240 is etched such that the remaining portion of the layer is formed over thegate metal 222. Next, as illustrated inFIG. 5I , a step of masking and ion implanting the polysilicon layer is performed to form NPN or PNP layers. As noted above, ion implanting of the polysilicon layer can result in an n-type region 223, a p-type region 224 and an n-type region 225 (i.e., an NPN layer for the source, gate and drain of the device) or, alternatively, a PNP layer. - Finally, as shown in
FIG. 5J , an additional dielectric material is deposited (again shown as dielectric material 219), a plurality of vias are formed in thedielectric material 219 and filled with a conductive material such as tungsten (W), copper (Cu) or the like, and metal contacts are formed on top of thedielectric material 219. As shown,vias regions metal contacts source metal 220 to themetal contact 232, and via 229 electrically couples thedrain metal 221 tometal contact 233. Although not shown, it should be appreciated that additional metal layers can be formed in a similar manner as that disclosed in the first embodiment, and, in particular, inFIG. 3G . -
FIG. 6 illustrates yet another embodiment of a GaN integrated circuit according to an exemplary embodiment of the present invention. The circuit illustrated inFIG. 6 is similar design to the GaN integrated circuit having a bottom gate polysilicon device structure as illustrated inFIG. 4A .FIG. 6 differs in that the bottom gate is formed using the pGaN layer and gate metal as the gate layer for the polysilicon FET, which effectively reduces the number of masks during fabrication as will become apparent from the exemplary process described below with respect toFIGS. 7A-7H . - As shown in
FIG. 6 , the GaN is formed on asubstrate 311, one or more transistor layers 312 (e.g., an AlN seed layer), a buffer layer 313 (e.g., an AlGaN layer), achannel layer 314 and anAlGaN barrier layer 315. Moreover, apGaN layer 316 andgate metal 317 are formed on thebarrier layer 315. An additional region of thepGaN layer 318 andgate metal 319 is formed on the barrier in the region isolated byisolation region 324. ThepGaN layer 318 andgate metal 319 form the gate layer for the polysilicon FET. - Moreover, source and drain
metals barrier layer 315 withvias metals metal contacts isolation region 324 is formed by ion implantation or etching in thebuffer barrier layer 315, thechannel layer 314 and extending into thebuffer layer 313. The device further includes an insulatingmaterial 320 that electrically insulates and protects the device metals. Furthermore, a polysilicon layer is formed above thebottom gate type region 321, a p-type region 322 and an n-type region 323 (i.e., an NPN layer for the source, gate and drain of the device), although it should be appreciated that the regions can be reversed to form a PNP layer.Vias doped regions metal contacts FIG. 4A , the device shown inFIG. 6 includes a bottom gate structure for a polysilicon FET that is disposed in an area of the circuit isolated from the active cells of the GaN FET. Although not shown, it should also be appreciate that the same structure can be formed with the gate structure for the polysilicon FET in the active region of the circuit (similar to the embodiment ofFIG. 4B ), rather than in the isolated region as it is disposed in the device shown inFIG. 6 . -
FIGS. 7A-7H illustrate an exemplary manufacturing process using a polysilicon layer to fabricate the device in an GaN integrated circuit as shown inFIG. 6 . All process flows can be used to form bottom gate polysilicon FETs in both the isolation area (FIG. 6 ) or the active region (not shown). A back gate formed by the polysilicon/gate metal prevents the effect of the 2DEG potential on the polysilicon FET. -
FIG. 7A illustrates an EPI structure, including, from bottom to top,silicon substrate 311, transition layers 312, aGaN buffer material 313, achannel layer 314, and anAlGaN barrier material 315. Furthermore, a p-type GaN material barrier material 315 and agate metal type GaN material 316. Although not shown, these structures are formed by depositing a photoresist and etching thegate metal type GaN material layer 320 is deposited. - Next as shown in
FIG. 7B , apolysilicon layer 340 is deposited on the insulatinglayer 320, which is then etched as shown inFIG. 7C . Next, as illustrated inFIG. 7D , a step of masking and ion implanting the remainingpolysilicon layer 340 is performed to form NPN or PNP layers. As noted above, ion implanting of the polysilicon layer can result in an n-type region 321, a p-type region 322 and an n-type region 323 (i.e., an NPN layer for the source, gate and drain of the device) or, alternatively, a PNP layer. - As shown in
FIG. 7E , anisolation region 324 is then formed by covering the portion of device layer and then etching down the exposed layers, at least below thechannel layer 314. The etched region can then be filled with oxide or other suitable isolating materials. It should be appreciated thatisolation region 324 can be formed using any other techniques as would be understood to one skilled in the art and further thatisolation region 324 can be formed at different stages in the process, for example, before the insulatinglayer 320 is deposited in step 7A. - Next, as shown in
FIG. 7F , the insulatingmaterial 320 is etched using a contact photo mask to form contact openings and contact metals are deposited to form thesource metal 325,drain metal 326, and optionally a field plate. An additional insulatinglayer 320 is deposited (FIG. 7G ) before a plurality of vias are formed in thedielectric material 320 and filled with a conductive material such as tungsten (W), copper (Cu) or the like, and metal contacts are formed on top of thedielectric material 320. As shown inFIG. 7H , vias 330 and 329 electrically coupled the dopedregions metal contacts source metal 325 to themetal contact 333, and via 327 electrically couples thedrain metal 326 tometal contact 334. Although not shown, it should be appreciated that additional metal layers can be formed in a similar manner as that disclosed in the first embodiment, and, in particular, inFIG. 3G . -
FIG. 8 illustrates yet another variation of a GaN integrated circuit according to an exemplary embodiment of the present invention. The circuit illustrated inFIG. 8 is a similar design to the GaN integrated circuit having a bottom gate polysilicon device structure as illustrated inFIG. 4A .FIG. 8 differs in that a metal layer that is normally used as a barrier layer forMetal 1 is used as the bottom gate for the polysilicon FET, which effectively reduces the number of masks during fabrication as will become apparent from the exemplary process described below with respect toFIGS. 9A-9I . - As shown in
FIG. 8 , a GaN integrated circuit is provided that includes a bottom gate polysilicon device structure and is formed on asubstrate 411, one or more transistor layers 412 (e.g., an AlN seed layer), a buffer layer 413 (e.g., an AlGaN layer), achannel layer 414 and anAlGaN barrier layer 415. These layers are similar to those of the EPI structure described above with reference to the embodiments discussed above. - As further shown, a
pGaN layer 416 andgate metal 417 are formed on thebarrier layer 415. Source and drainmetals barrier layer 415 withvias metals metal contacts isolation region 418 is formed by ion implantation or etching in thebuffer barrier layer 415, thechannel layer 414 and extending into thebuffer layer 413. The device further includes an insulatingmaterial 419 that electrically insulates and protects the device metals. As shown, abottom gate 421 of the polysilicon FET is formed in the insulating material. It is noted that thebottom gate 421 can be a metal, polysilicon or other conductive material. Moreover, in this embodiment, the metal layer extends under the source and drainmetals FIG. 8 further includes a polysilicon layer that is formed above thebottom gate 421. The polysilicon layer can comprise an n-type region 424, a p-type region 425 and an n-type region 426 (i.e., an NPN layer for the source, gate and drain of the device), although it should be appreciated that the regions can be reversed to form a PNP layer.Vias doped regions metal contacts FIG. 8 includes a bottom gate structure for a polysilicon FET that is disposed in an area of the circuit isolated from the active cells of the GaN FET. Alternatively, the bottom gate of thepolysilicon FET 421 can be formed in the active region of the circuit rather than the isolated region as it is disposed in the device shown inFIG. 8 . -
FIGS. 9A-9I illustrate an exemplary manufacturing process using a polysilicon layer to fabricate the devices in an GaN integrated circuit as shown inFIG. 8 . All process flows can be used to form bottom gate polysilicon FETs in both the active device area (not shown) or in the isolation area (FIG. 8 ). A back gate formed by the polysilicon/gate metal prevents the effect of the 2DEG potential on the polysilicon FET. - Initially, as shown in
FIG. 9A , an EPI structure is formed that includes, from bottom to top,silicon substrate 411, transition layers 412, aGaN buffer material 413, achannel layer 414, and anAlGaN barrier material 415. Furthermore, a p-type GaN material 416 is formed on thebarrier material 415 and agate metal 417 is formed (i.e., deposited or grown) on the p-type GaN material 416. After a photoresist is deposited and thegate metal 417 and the p-type GaN material 416 are etched, anisolation region 418 is then formed and an insulatingmaterial 419 is deposited over the EPI structure.Isolation region 418 can be formed by covering the portion ofdevice layer 415 and then etching down the exposed layers, at least below thechannel layer 414. The etched region can then be filled with oxide or other suitable isolating materials. - Next, a
barrier metal 440 underMetal 1 is deposited as shown inFIG. 9B .FIG. 9C illustrates the next step in which thebarrier metal 440 and the insulatingmaterial 419 are etched to form contact openings and a contact metal (i.e., Metal 1) 441 is deposited to form the source metal, drain metal, and optionally a field plate. As further shown inFIG. 9D , themetal layer 441 andbarrier metal 440 are etched for form thesource metal 422,drain metal 423 andbarrier metal layer 421 for the polysilicon FET. It should be appreciated in the exemplary embodiment, the metal layer is etched over thebarrier metal layer 421, but is not etched where thesource metal 422 and drainmetal 423 are to be formed. In other words, the manufacturing processes must selectively determine which metal layers are to be etched. - As before, an insulating material is then deposited on the structure, which is again shown as insulating
material 419 inFIG. 9E , and apolysilicon layer 442 is deposited on the insulatingmaterial 419 as shown inFIG. 9F . Thepolysilicon layer 442 is then etched using a contact photo mask such that the remaining portion of the layer is formed over thegate metal 421 as shown inFIG. 9G . Then, in stepFIG. 9H , a step of masking and ion implanting thepolysilicon layer 442 is performed to form NPN or PNP layers. As noted above, ion implanting of the polysilicon layer can result in an n-type region 424, a p-type region 425 and an n-type region 426 (i.e., an NPN layer for the source, gate and drain of the device) or, alternatively, a PNP layer. - Finally, as shown in
FIG. 9I , an additional dielectric material is deposited (again shown as dielectric material 419), a plurality of vias are formed in thedielectric material 419 and filled with a conductive material such as tungsten (W), copper (Cu) or the like, and metal contacts are formed on top of thedielectric material 219. As shown,vias regions metal contacts source metal 422 to themetal contact 433, and via 427 electrically couples thedrain metal 423 tometal contact 434. Although not shown, it should be appreciated that additional metal layers can be formed in a similar manner as that disclosed in the first embodiment, and, in particular, inFIG. 3G . - The above description and drawings are only to be considered illustrative of specific embodiments, which achieve the features and advantages described herein. Modifications and substitutions to specific process conditions can be made. Accordingly, the embodiments of the invention are not considered as being limited by the foregoing description and drawings.
Claims (40)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/445,988 US9214461B2 (en) | 2013-07-29 | 2014-07-29 | GaN transistors with polysilicon layers for creating additional components |
US14/959,710 US9837438B2 (en) | 2013-07-29 | 2015-12-04 | GaN transistors with polysilicon layers used for creating additional components |
US15/655,508 US10312260B2 (en) | 2013-07-29 | 2017-07-20 | GaN transistors with polysilicon layers used for creating additional components |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201361859519P | 2013-07-29 | 2013-07-29 | |
US201461978014P | 2014-04-10 | 2014-04-10 | |
US14/445,988 US9214461B2 (en) | 2013-07-29 | 2014-07-29 | GaN transistors with polysilicon layers for creating additional components |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/959,710 Division US9837438B2 (en) | 2013-07-29 | 2015-12-04 | GaN transistors with polysilicon layers used for creating additional components |
Publications (2)
Publication Number | Publication Date |
---|---|
US20150028384A1 true US20150028384A1 (en) | 2015-01-29 |
US9214461B2 US9214461B2 (en) | 2015-12-15 |
Family
ID=52389762
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/445,988 Active US9214461B2 (en) | 2013-07-29 | 2014-07-29 | GaN transistors with polysilicon layers for creating additional components |
US14/959,710 Active 2034-09-05 US9837438B2 (en) | 2013-07-29 | 2015-12-04 | GaN transistors with polysilicon layers used for creating additional components |
US15/655,508 Active 2034-09-28 US10312260B2 (en) | 2013-07-29 | 2017-07-20 | GaN transistors with polysilicon layers used for creating additional components |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/959,710 Active 2034-09-05 US9837438B2 (en) | 2013-07-29 | 2015-12-04 | GaN transistors with polysilicon layers used for creating additional components |
US15/655,508 Active 2034-09-28 US10312260B2 (en) | 2013-07-29 | 2017-07-20 | GaN transistors with polysilicon layers used for creating additional components |
Country Status (7)
Country | Link |
---|---|
US (3) | US9214461B2 (en) |
JP (1) | JP6483116B2 (en) |
KR (1) | KR102210449B1 (en) |
CN (1) | CN105684134B (en) |
DE (2) | DE112014003481B4 (en) |
TW (1) | TWI566328B (en) |
WO (1) | WO2015017410A1 (en) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160079403A1 (en) * | 2014-09-12 | 2016-03-17 | Kabushiki Kaisha Toshiba | Field effect transistor |
US20170047378A1 (en) * | 2015-04-27 | 2017-02-16 | International Business Machines Corporation | Hybrid high electron mobility transistor and active matrix structure |
CN106486543A (en) * | 2015-08-29 | 2017-03-08 | 台湾积体电路制造股份有限公司 | Semiconductor device and its manufacture method |
CN106601792A (en) * | 2015-10-15 | 2017-04-26 | 北京大学 | Gallium nitride transistor of high electron mobility and preparation method of transistor |
WO2018063278A1 (en) * | 2016-09-30 | 2018-04-05 | Intel Corporation | Transistors with vertically opposed source and drain metal interconnect layers |
WO2018096537A1 (en) * | 2016-11-24 | 2018-05-31 | Visic Technologies Ltd. | Transistor cell |
US10170580B2 (en) | 2017-05-23 | 2019-01-01 | Industrial Technology Research Institute | Structure of GaN-based transistor and method of fabricating the same |
US20200357736A1 (en) * | 2018-01-19 | 2020-11-12 | Rohm Co., Ltd. | Semiconductor device and method for producing same |
US10964788B1 (en) * | 2019-11-27 | 2021-03-30 | Vanguard International Semiconductor Corporation | Semiconductor device and operating method thereof |
US11127846B2 (en) * | 2019-07-12 | 2021-09-21 | Vanguard International Semiconductor Corporation | High electron mobility transistor devices and methods for forming the same |
US11444090B2 (en) | 2020-04-20 | 2022-09-13 | Semiconductor Components Industries, Llc | Semiconductor device having a programming element |
US20230124962A1 (en) * | 2021-10-17 | 2023-04-20 | Globalfoundries U.S. Inc. | High electron mobility transistor devices having a silicided polysilicon layer |
CN116130431A (en) * | 2023-04-12 | 2023-05-16 | 通威微电子有限公司 | Semiconductor device and manufacturing method thereof |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI566328B (en) * | 2013-07-29 | 2017-01-11 | 高效電源轉換公司 | Gan transistors with polysilicon layers for creating additional components |
US10110232B2 (en) | 2015-06-30 | 2018-10-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiplexer and latch system |
US9543402B1 (en) * | 2015-08-04 | 2017-01-10 | Power Integrations, Inc. | Integrated high performance lateral schottky diode |
US10204791B1 (en) * | 2017-09-22 | 2019-02-12 | Power Integrations, Inc. | Contact plug for high-voltage devices |
US10950598B2 (en) * | 2018-01-19 | 2021-03-16 | Macom Technology Solutions Holdings, Inc. | Heterolithic microwave integrated circuits including gallium-nitride devices formed on highly doped semiconductor |
JP2020061414A (en) * | 2018-10-05 | 2020-04-16 | ローム株式会社 | Nitride semiconductor device and manufacturing method of nitride semiconductor device |
US11538804B2 (en) * | 2019-01-09 | 2022-12-27 | Intel Corporation | Stacked integration of III-N transistors and thin-film transistors |
TWI692868B (en) * | 2019-04-16 | 2020-05-01 | 世界先進積體電路股份有限公司 | Semiconductor structure |
TWI726316B (en) * | 2019-05-08 | 2021-05-01 | 世界先進積體電路股份有限公司 | High electron mobility transistor devices and methods for forming the same |
US10886394B1 (en) | 2019-06-19 | 2021-01-05 | Vanguard International Semiconductor Corporation | Semiconductor structure |
CN113035943A (en) * | 2019-12-25 | 2021-06-25 | 华润微电子(重庆)有限公司 | HEMT device with field plate structure and preparation method thereof |
CN112789731A (en) | 2020-12-25 | 2021-05-11 | 英诺赛科(苏州)科技有限公司 | Semiconductor device and method for manufacturing the same |
Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6075258A (en) * | 1997-06-11 | 2000-06-13 | Advanced Micro Devices, Inc. | Elevated transistor fabrication technique |
US6600173B2 (en) * | 2000-08-30 | 2003-07-29 | Cornell Research Foundation, Inc. | Low temperature semiconductor layering and three-dimensional electronic circuits using the layering |
US20040185622A1 (en) * | 1999-04-22 | 2004-09-23 | Advanced Analogic Technologies, Inc. | Self-aligned trench transistor using etched contact |
US20080029816A1 (en) * | 2006-05-15 | 2008-02-07 | Stmicroelectronics S. R. L. | Process for integrating on an inert substrate a device comprising at least a passive element and an active element and corresponding integrated device |
US7417268B2 (en) * | 2005-07-21 | 2008-08-26 | Stmicroelectronics S.A. | Image sensor |
US20090267233A1 (en) * | 1996-11-04 | 2009-10-29 | Sang-Yun Lee | Bonded semiconductor structure and method of making the same |
US7723207B2 (en) * | 2004-08-16 | 2010-05-25 | International Business Machines Corporation | Three dimensional integrated circuit and method of design |
US20110027968A1 (en) * | 2007-08-24 | 2011-02-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US20110193166A1 (en) * | 2010-02-05 | 2011-08-11 | International Business Machines Corporation | Structure and method for reducing floating body effect of soi mosfets |
US20110233617A1 (en) * | 2009-10-12 | 2011-09-29 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US20110298021A1 (en) * | 2009-02-24 | 2011-12-08 | Nec Corporation | Semiconductor device and method for manufacturing the same |
US8541819B1 (en) * | 2010-12-09 | 2013-09-24 | Monolithic 3D Inc. | Semiconductor device and structure |
US8581309B2 (en) * | 2007-09-21 | 2013-11-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US8779479B2 (en) * | 2009-11-13 | 2014-07-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US8896046B2 (en) * | 2010-11-05 | 2014-11-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US8901559B2 (en) * | 2009-12-11 | 2014-12-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having inverter circuit with terminal electrically connected to transistor that includes oxide semiconductor material |
Family Cites Families (97)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0612799B2 (en) * | 1986-03-03 | 1994-02-16 | 三菱電機株式会社 | Stacked semiconductor device and manufacturing method thereof |
JPH07109873B2 (en) * | 1988-07-05 | 1995-11-22 | 株式会社東芝 | Semiconductor memory device |
US5006913A (en) * | 1988-11-05 | 1991-04-09 | Mitsubishi Denki Kabushiki Kaisha | Stacked type semiconductor device |
JPH0456163A (en) * | 1990-06-21 | 1992-02-24 | Fujitsu Ltd | Semiconductor device and its manufacture |
US5041884A (en) * | 1990-10-11 | 1991-08-20 | Mitsubishi Denki Kabushiki Kaisha | Multilayer semiconductor integrated circuit |
US5844303A (en) * | 1991-02-19 | 1998-12-01 | Fujitsu Limited | Semiconductor device having improved electronic isolation |
US5266511A (en) * | 1991-10-02 | 1993-11-30 | Fujitsu Limited | Process for manufacturing three dimensional IC's |
JP2576983Y2 (en) * | 1992-03-31 | 1998-07-23 | 関西日本電気株式会社 | Power MOSFET with built-in gate protection diode |
JP3637069B2 (en) * | 1993-03-12 | 2005-04-06 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
JPH07176688A (en) * | 1993-12-20 | 1995-07-14 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
JPH08264790A (en) * | 1995-03-22 | 1996-10-11 | Toshiba Corp | Thin film field-effect transistor and liquid crystal display device |
US5675185A (en) * | 1995-09-29 | 1997-10-07 | International Business Machines Corporation | Semiconductor structure incorporating thin film transistors with undoped cap oxide layers |
JPH09153624A (en) * | 1995-11-30 | 1997-06-10 | Sony Corp | Semiconductor device |
US5990507A (en) * | 1996-07-09 | 1999-11-23 | Kabushiki Kaisha Toshiba | Semiconductor device having ferroelectric capacitor structures |
US5950082A (en) * | 1996-09-30 | 1999-09-07 | Advanced Micro Devices, Inc. | Transistor formation for multilevel transistors |
US5770482A (en) * | 1996-10-08 | 1998-06-23 | Advanced Micro Devices, Inc. | Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto |
US5872029A (en) * | 1996-11-07 | 1999-02-16 | Advanced Micro Devices, Inc. | Method for forming an ultra high density inverter using a stacked transistor arrangement |
US5923067A (en) * | 1997-04-04 | 1999-07-13 | International Business Machines Corporation | 3-D CMOS-on-SOI ESD structure and method |
US5880991A (en) * | 1997-04-14 | 1999-03-09 | International Business Machines Corporation | Structure for low cost mixed memory integration, new NVRAM structure, and process for forming the mixed memory and NVRAM structure |
US5889302A (en) * | 1997-04-21 | 1999-03-30 | Advanced Micro Devices, Inc. | Multilayer floating gate field effect transistor structure for use in integrated circuit devices |
US5818069A (en) * | 1997-06-20 | 1998-10-06 | Advanced Micro Devices, Inc. | Ultra high density series-connected transistors formed on separate elevational levels |
US5888872A (en) * | 1997-06-20 | 1999-03-30 | Advanced Micro Devices, Inc. | Method for forming source drain junction areas self-aligned between a sidewall spacer and an etched lateral sidewall |
US5949092A (en) * | 1997-08-01 | 1999-09-07 | Advanced Micro Devices, Inc. | Ultra-high-density pass gate using dual stacked transistors having a gate structure with planarized upper surface in relation to interlayer insulator |
US6271542B1 (en) * | 1997-12-08 | 2001-08-07 | International Business Machines Corporation | Merged logic and memory combining thin film and bulk Si transistors |
US6030860A (en) * | 1997-12-19 | 2000-02-29 | Advanced Micro Devices, Inc. | Elevated substrate formation and local interconnect integrated fabrication |
JP3483484B2 (en) | 1998-12-28 | 2004-01-06 | 富士通ディスプレイテクノロジーズ株式会社 | Semiconductor device, image display device, method of manufacturing semiconductor device, and method of manufacturing image display device |
US6429484B1 (en) * | 2000-08-07 | 2002-08-06 | Advanced Micro Devices, Inc. | Multiple active layer structure and a method of making such a structure |
US6887753B2 (en) * | 2001-02-28 | 2005-05-03 | Micron Technology, Inc. | Methods of forming semiconductor circuitry, and semiconductor circuit constructions |
JP3551947B2 (en) * | 2001-08-29 | 2004-08-11 | サンケン電気株式会社 | Semiconductor device and manufacturing method thereof |
US20040018711A1 (en) * | 2002-07-08 | 2004-01-29 | Madurawe Raminda U. | Methods for fabricating three dimensional integrated circuits |
US6882010B2 (en) * | 2002-10-03 | 2005-04-19 | Micron Technology, Inc. | High performance three-dimensional TFT-based CMOS inverters, and computer systems utilizing such novel CMOS inverters |
US6998683B2 (en) * | 2002-10-03 | 2006-02-14 | Micron Technology, Inc. | TFT-based common gate CMOS inverters, and computer systems utilizing novel CMOS inverters |
US7589380B2 (en) * | 2002-12-18 | 2009-09-15 | Noble Peak Vision Corp. | Method for forming integrated circuit utilizing dual semiconductors |
JP2005101141A (en) * | 2003-09-24 | 2005-04-14 | Renesas Technology Corp | Semiconductor integrated circuit device and its manufacturing method |
KR100746220B1 (en) * | 2004-01-12 | 2007-08-03 | 삼성전자주식회사 | Semiconductor integrated circuits employing stacked node contact structures and stacked thin film transistors and methods of fabricating the same |
US7112815B2 (en) * | 2004-02-25 | 2006-09-26 | Micron Technology, Inc. | Multi-layer memory arrays |
KR100519801B1 (en) * | 2004-04-26 | 2005-10-10 | 삼성전자주식회사 | Semiconductor devices having a nod contact plug surrounded by a stress buffer spacer and methods of fabricating the same |
US7417266B1 (en) | 2004-06-10 | 2008-08-26 | Qspeed Semiconductor Inc. | MOSFET having a JFET embedded as a body diode |
JP4907070B2 (en) * | 2004-09-10 | 2012-03-28 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
US7566974B2 (en) * | 2004-09-29 | 2009-07-28 | Sandisk 3D, Llc | Doped polysilicon via connecting polysilicon layers |
KR100665848B1 (en) * | 2005-03-21 | 2007-01-09 | 삼성전자주식회사 | Semiconductor device having stacked decoupling capacitors |
US20070007621A1 (en) * | 2005-03-30 | 2007-01-11 | Yamaha Corporation | Fuse breakdown method adapted to semiconductor device |
KR100663360B1 (en) * | 2005-04-20 | 2007-01-02 | 삼성전자주식회사 | Semiconductor devices having thin film transistor and fabrication methods thereof |
US7420226B2 (en) * | 2005-06-17 | 2008-09-02 | Northrop Grumman Corporation | Method for integrating silicon CMOS and AlGaN/GaN wideband amplifiers on engineered substrates |
JP5237535B2 (en) * | 2005-07-28 | 2013-07-17 | パナソニック株式会社 | Semiconductor device |
US7432565B2 (en) * | 2005-09-27 | 2008-10-07 | Freescale Semiconductor, Inc. | III-V compound semiconductor heterostructure MOSFET device |
EP1961120A4 (en) * | 2005-12-07 | 2008-12-31 | Dsm Solutions Inc | Method of producing and operating a low power junction field effect transistor |
KR101214901B1 (en) * | 2006-02-09 | 2012-12-26 | 삼성전자주식회사 | Multi-level semiconductor deivce |
US7285477B1 (en) | 2006-05-16 | 2007-10-23 | International Business Machines Corporation | Dual wired integrated circuit chips |
US7595232B2 (en) * | 2006-09-07 | 2009-09-29 | International Business Machines Corporation | CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors |
WO2008036256A1 (en) * | 2006-09-18 | 2008-03-27 | Amberwave Systems Corporation | Aspect ratio trapping for mixed signal applications |
JP5415001B2 (en) * | 2007-02-22 | 2014-02-12 | 株式会社半導体エネルギー研究所 | Semiconductor device |
US8049253B2 (en) * | 2007-07-11 | 2011-11-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
WO2009073866A1 (en) * | 2007-12-07 | 2009-06-11 | The Government Of The United States Of America, As Represented By The Secretary Of The Navy | Gate after diamond transistor |
JP2009158528A (en) * | 2007-12-25 | 2009-07-16 | Sharp Corp | Semiconductor device |
US8084783B2 (en) * | 2008-11-10 | 2011-12-27 | International Rectifier Corporation | GaN-based device cascoded with an integrated FET/Schottky diode device |
KR101486426B1 (en) * | 2009-01-30 | 2015-01-26 | 삼성전자주식회사 | Stacked loadless random access memory device |
DE112010001589T5 (en) * | 2009-04-08 | 2012-06-28 | Efficient Power Conversion Corporation | Compensated GATE MISFET and process for its production |
TWI514567B (en) * | 2009-04-08 | 2015-12-21 | Efficient Power Conversion Corp | Back diffusion suppression structures |
US8362482B2 (en) * | 2009-04-14 | 2013-01-29 | Monolithic 3D Inc. | Semiconductor device and structure |
US7994550B2 (en) * | 2009-05-22 | 2011-08-09 | Raytheon Company | Semiconductor structures having both elemental and compound semiconductor devices on a common substrate |
US7915645B2 (en) * | 2009-05-28 | 2011-03-29 | International Rectifier Corporation | Monolithic vertically integrated composite group III-V and group IV semiconductor device and method for fabricating same |
US8564020B2 (en) * | 2009-07-27 | 2013-10-22 | The Hong Kong University Of Science And Technology | Transistors and rectifiers utilizing hybrid electrodes and methods of fabricating the same |
US8242510B2 (en) * | 2010-01-28 | 2012-08-14 | Intersil Americas Inc. | Monolithic integration of gallium nitride and silicon devices and circuits, structure and method |
US9608119B2 (en) * | 2010-03-02 | 2017-03-28 | Micron Technology, Inc. | Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures |
US20110248283A1 (en) * | 2010-04-07 | 2011-10-13 | Jianjun Cao | Via structure of a semiconductor device and method for fabricating the same |
US8487593B2 (en) * | 2010-04-22 | 2013-07-16 | Intersil Americas Inc. | System and method for detection and compensation of aggressive output filters for switched mode power supplies |
US8492773B2 (en) | 2010-04-23 | 2013-07-23 | Intersil Americas Inc. | Power devices with integrated protection devices: structures and methods |
US8389348B2 (en) * | 2010-09-14 | 2013-03-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanism of forming SiC crystalline on Si substrates to allow integration of GaN and Si electronics |
JPWO2012086104A1 (en) | 2010-12-22 | 2014-05-22 | パナソニック株式会社 | Semiconductor device |
US8748871B2 (en) * | 2011-01-19 | 2014-06-10 | International Business Machines Corporation | Graphene devices and semiconductor field effect transistors in 3D hybrid integrated circuits |
DE112012000612T5 (en) * | 2011-01-31 | 2013-10-24 | Efficient Power Conversion Corp. | Ion-implanted and self-aligned gate structure for GaN transistors |
US9111795B2 (en) * | 2011-04-29 | 2015-08-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device with capacitor connected to memory element through oxide semiconductor film |
US8994181B2 (en) | 2011-08-18 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bond pad structure to reduce bond pad corrosion |
WO2013032906A1 (en) * | 2011-08-29 | 2013-03-07 | Efficient Power Conversion Corporation | Parallel connection methods for high performance transistors |
JP5678866B2 (en) * | 2011-10-31 | 2015-03-04 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
US8723226B2 (en) | 2011-11-22 | 2014-05-13 | Texas Instruments Incorporated | Manufacturable enhancement-mode group III-N HEMT with a reverse polarization cap |
US8916909B2 (en) * | 2012-03-06 | 2014-12-23 | Infineon Technologies Austria Ag | Semiconductor device and method for fabricating a semiconductor device |
US9006024B2 (en) * | 2012-04-25 | 2015-04-14 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US8587033B1 (en) * | 2012-06-04 | 2013-11-19 | Infineon Technologies Austria Ag | Monolithically integrated HEMT and current protection device |
US9337123B2 (en) * | 2012-07-11 | 2016-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal structure for integrated circuit package |
US9219445B2 (en) * | 2012-12-28 | 2015-12-22 | Peregrine Semiconductor Corporation | Optimization methods for amplifier with variable supply power |
EP2787641B1 (en) * | 2013-04-05 | 2018-08-29 | Nexperia B.V. | Cascoded semiconductor devices |
US9035318B2 (en) * | 2013-05-03 | 2015-05-19 | Texas Instruments Incorporated | Avalanche energy handling capable III-nitride transistors |
US9356045B2 (en) * | 2013-06-10 | 2016-05-31 | Raytheon Company | Semiconductor structure having column III-V isolation regions |
US9553183B2 (en) * | 2013-06-19 | 2017-01-24 | Infineon Technologies Austria Ag | Gate stack for normally-off compound semiconductor transistor |
TWI566328B (en) * | 2013-07-29 | 2017-01-11 | 高效電源轉換公司 | Gan transistors with polysilicon layers for creating additional components |
US8947154B1 (en) * | 2013-10-03 | 2015-02-03 | Avogy, Inc. | Method and system for operating gallium nitride electronics |
US20150340483A1 (en) * | 2014-05-21 | 2015-11-26 | International Rectifier Corporation | Group III-V Device Including a Shield Plate |
US20150371987A1 (en) * | 2014-06-23 | 2015-12-24 | International Rectifier Corporation | Group III-V HEMT Having a Diode Controlled Substrate |
WO2016007088A1 (en) * | 2014-07-08 | 2016-01-14 | Massachusetts Institute Of Technology | Method of manufacturing a substrate |
US9087689B1 (en) * | 2014-07-11 | 2015-07-21 | Inoso, Llc | Method of forming a stacked low temperature transistor and related devices |
CN105470313B (en) * | 2014-08-12 | 2018-11-02 | 北京纳米能源与系统研究所 | Backgate field-effect transistor based on contact electrification |
US9385224B2 (en) * | 2014-08-13 | 2016-07-05 | Northrop Grumman Systems Corporation | Method of forming an integrated multichannel device and single channel device structure |
WO2016028967A1 (en) * | 2014-08-20 | 2016-02-25 | Navitas Semiconductor, Inc. | Power transistor with distributed gate |
US9571093B2 (en) * | 2014-09-16 | 2017-02-14 | Navitas Semiconductor, Inc. | Half bridge driver circuits |
US9667245B2 (en) * | 2014-10-10 | 2017-05-30 | Efficient Power Conversion Corporation | High voltage zero QRR bootstrap supply |
-
2014
- 2014-07-28 TW TW103125695A patent/TWI566328B/en active
- 2014-07-29 DE DE112014003481.9T patent/DE112014003481B4/en active Active
- 2014-07-29 CN CN201480042752.2A patent/CN105684134B/en active Active
- 2014-07-29 KR KR1020167005235A patent/KR102210449B1/en active IP Right Grant
- 2014-07-29 US US14/445,988 patent/US9214461B2/en active Active
- 2014-07-29 WO PCT/US2014/048616 patent/WO2015017410A1/en active Application Filing
- 2014-07-29 JP JP2016531818A patent/JP6483116B2/en active Active
- 2014-07-29 DE DE112014007341.5T patent/DE112014007341B4/en active Active
-
2015
- 2015-12-04 US US14/959,710 patent/US9837438B2/en active Active
-
2017
- 2017-07-20 US US15/655,508 patent/US10312260B2/en active Active
Patent Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090267233A1 (en) * | 1996-11-04 | 2009-10-29 | Sang-Yun Lee | Bonded semiconductor structure and method of making the same |
US6075258A (en) * | 1997-06-11 | 2000-06-13 | Advanced Micro Devices, Inc. | Elevated transistor fabrication technique |
US20040185622A1 (en) * | 1999-04-22 | 2004-09-23 | Advanced Analogic Technologies, Inc. | Self-aligned trench transistor using etched contact |
US6600173B2 (en) * | 2000-08-30 | 2003-07-29 | Cornell Research Foundation, Inc. | Low temperature semiconductor layering and three-dimensional electronic circuits using the layering |
US7723207B2 (en) * | 2004-08-16 | 2010-05-25 | International Business Machines Corporation | Three dimensional integrated circuit and method of design |
US7417268B2 (en) * | 2005-07-21 | 2008-08-26 | Stmicroelectronics S.A. | Image sensor |
US20080029816A1 (en) * | 2006-05-15 | 2008-02-07 | Stmicroelectronics S. R. L. | Process for integrating on an inert substrate a device comprising at least a passive element and an active element and corresponding integrated device |
US20110027968A1 (en) * | 2007-08-24 | 2011-02-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US8581309B2 (en) * | 2007-09-21 | 2013-11-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US20110298021A1 (en) * | 2009-02-24 | 2011-12-08 | Nec Corporation | Semiconductor device and method for manufacturing the same |
US20110233617A1 (en) * | 2009-10-12 | 2011-09-29 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US8779479B2 (en) * | 2009-11-13 | 2014-07-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US8901559B2 (en) * | 2009-12-11 | 2014-12-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having inverter circuit with terminal electrically connected to transistor that includes oxide semiconductor material |
US20110193166A1 (en) * | 2010-02-05 | 2011-08-11 | International Business Machines Corporation | Structure and method for reducing floating body effect of soi mosfets |
US8896046B2 (en) * | 2010-11-05 | 2014-11-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US8541819B1 (en) * | 2010-12-09 | 2013-09-24 | Monolithic 3D Inc. | Semiconductor device and structure |
Cited By (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160079403A1 (en) * | 2014-09-12 | 2016-03-17 | Kabushiki Kaisha Toshiba | Field effect transistor |
US10115773B2 (en) | 2015-04-27 | 2018-10-30 | International Business Machines Corporation | Hybrid high electron mobility transistor and active matrix structure |
US20170047378A1 (en) * | 2015-04-27 | 2017-02-16 | International Business Machines Corporation | Hybrid high electron mobility transistor and active matrix structure |
US10790336B2 (en) | 2015-04-27 | 2020-09-29 | International Business Machines Corporation | Hybrid high electron mobility transistor and active matrix structure |
US10256276B2 (en) * | 2015-04-27 | 2019-04-09 | International Business Machines Corporation | Hybrid high electron mobility transistor and active matrix structure |
US10686054B2 (en) | 2015-08-29 | 2020-06-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device |
CN106486543A (en) * | 2015-08-29 | 2017-03-08 | 台湾积体电路制造股份有限公司 | Semiconductor device and its manufacture method |
US11901433B2 (en) | 2015-08-29 | 2024-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device |
US11374107B2 (en) | 2015-08-29 | 2022-06-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device |
CN106601792A (en) * | 2015-10-15 | 2017-04-26 | 北京大学 | Gallium nitride transistor of high electron mobility and preparation method of transistor |
TWI784966B (en) * | 2016-09-30 | 2022-12-01 | 美商英特爾股份有限公司 | Transistors with vertically opposed source and drain metal interconnect layers |
WO2018063278A1 (en) * | 2016-09-30 | 2018-04-05 | Intel Corporation | Transistors with vertically opposed source and drain metal interconnect layers |
US10658475B2 (en) | 2016-09-30 | 2020-05-19 | Intel Corporation | Transistors with vertically opposed source and drain metal interconnect layers |
CN110168936A (en) * | 2016-11-24 | 2019-08-23 | 威电科技有限公司 | Transistor unit |
US10930737B2 (en) | 2016-11-24 | 2021-02-23 | Visic Technologies Ltd. | Transistor cell |
WO2018096537A1 (en) * | 2016-11-24 | 2018-05-31 | Visic Technologies Ltd. | Transistor cell |
JP2020501352A (en) * | 2016-11-24 | 2020-01-16 | ヴィジック テクノロジーズ リミテッド | Transistor cell |
US10170580B2 (en) | 2017-05-23 | 2019-01-01 | Industrial Technology Research Institute | Structure of GaN-based transistor and method of fabricating the same |
US20200357736A1 (en) * | 2018-01-19 | 2020-11-12 | Rohm Co., Ltd. | Semiconductor device and method for producing same |
US11694954B2 (en) * | 2018-01-19 | 2023-07-04 | Rohm Co., Ltd. | Semiconductor device and method for producing same |
US11127846B2 (en) * | 2019-07-12 | 2021-09-21 | Vanguard International Semiconductor Corporation | High electron mobility transistor devices and methods for forming the same |
US10964788B1 (en) * | 2019-11-27 | 2021-03-30 | Vanguard International Semiconductor Corporation | Semiconductor device and operating method thereof |
US11444090B2 (en) | 2020-04-20 | 2022-09-13 | Semiconductor Components Industries, Llc | Semiconductor device having a programming element |
US20230124962A1 (en) * | 2021-10-17 | 2023-04-20 | Globalfoundries U.S. Inc. | High electron mobility transistor devices having a silicided polysilicon layer |
US11923446B2 (en) * | 2021-10-17 | 2024-03-05 | Globalfoundries U.S. Inc. | High electron mobility transistor devices having a silicided polysilicon layer |
CN116130431A (en) * | 2023-04-12 | 2023-05-16 | 通威微电子有限公司 | Semiconductor device and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
WO2015017410A1 (en) | 2015-02-05 |
US10312260B2 (en) | 2019-06-04 |
CN105684134A (en) | 2016-06-15 |
DE112014003481T5 (en) | 2016-04-14 |
KR102210449B1 (en) | 2021-02-02 |
JP2016529710A (en) | 2016-09-23 |
US20170330898A1 (en) | 2017-11-16 |
DE112014007341B4 (en) | 2024-03-14 |
US20160086980A1 (en) | 2016-03-24 |
TWI566328B (en) | 2017-01-11 |
JP6483116B2 (en) | 2019-03-13 |
DE112014003481B4 (en) | 2020-10-22 |
KR20160038011A (en) | 2016-04-06 |
US9214461B2 (en) | 2015-12-15 |
TW201519363A (en) | 2015-05-16 |
US9837438B2 (en) | 2017-12-05 |
CN105684134B (en) | 2019-01-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10312260B2 (en) | GaN transistors with polysilicon layers used for creating additional components | |
US10446542B1 (en) | GaN structures | |
US8884335B2 (en) | Semiconductor including lateral HEMT | |
US10522532B2 (en) | Through via extending through a group III-V layer | |
US11024703B2 (en) | Semiconductor device and a method for fabricating the same | |
US20180026099A1 (en) | Semiconductor device and method of manufacturing the semiconductor device | |
US9397168B2 (en) | Method to define the active region of a transistor employing a group III-V semiconductor material | |
US9171911B2 (en) | Isolation structure in gallium nitride devices and integrated circuits | |
US20220359295A1 (en) | Semiconductor structure and method for manufacturing thereof | |
US9412863B2 (en) | Enhanced breakdown voltages for high voltage MOSFETS | |
US20170221821A1 (en) | Semiconductor device and a method for fabricating the same | |
JP2017059691A (en) | Semiconductor device and semiconductor device manufacturing method | |
KR102193085B1 (en) | Method to fabricate self-aligned isolation in gallium nitride devices and integrated circuits | |
JP2005197495A (en) | Electrostatic protection element and its fabrication process, and semiconductor device and its fabrication process | |
CN113078098A (en) | Semiconductor structure and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: EFFICIENT POWER CONVERSION CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIDOW, ALEXANDER;BEACH, ROBERT;NAKATA, ALANA;AND OTHERS;SIGNING DATES FROM 20140722 TO 20140728;REEL/FRAME:034933/0030 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YR, SMALL ENTITY (ORIGINAL EVENT CODE: M2551); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YR, SMALL ENTITY (ORIGINAL EVENT CODE: M2552); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY Year of fee payment: 8 |