JP5237535B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a field effect transistor using a nitride semiconductor provided with a protective diode.

The group III-V nitride semiconductor, general formula _{B w Al x Ga y In z} N ( where, w + x + y + z = 1;. 0 ≦ w, x, y, a z ≦ 1) is represented by aluminum A compound semiconductor made of a compound of (Al), boron (B), gallium (Ga) or indium (In) and nitrogen (N).

  Nitride semiconductors have advantages such as a large band gap and a high breakdown voltage, a high electron saturation speed and a high electron mobility, and a high electron concentration at the heterojunction. Research and development is progressing for the purpose of application to high-frequency, low-noise amplification elements.

  In particular, a heterojunction structure in which III-V nitride semiconductor layers having different band gaps with different composition ratios of group III-V elements are stacked, or a quantum well structure or a superlattice structure in which a plurality of these are stacked are included in the device. Since the degree of modulation of the electron concentration can be controlled, it is used as the basic structure of the element.

  One of semiconductor devices using a heterojunction structure is a heterojunction field effect transistor (HFET). The HFET is an element that operates at high speed, and is expected to be applied to high output elements, power switching elements, high frequency power devices, high frequency low noise amplifiers, and the like.

  The semiconductor layer is required to be miniaturized, and HFETs used for such applications are no exception. However, HFETs using nitride semiconductors are limited in terms of gate surge withstand voltage, and there is a limit to miniaturization of gates. Further, in the case of a power switching element or the like, it is required to further improve surge resistance.

In order to improve the surge resistance of an element in a conventional semiconductor device, it is known to form a protective element separately from the element (see, for example, Patent Document 1). In addition, a protection circuit is formed as an external circuit.
JP 60-10653 A

  However, the conventional semiconductor device has a problem that the entire circuit or the element area increases because a protection circuit is formed outside or a protection element is separately formed in order to protect the gate from a surge voltage. doing. In addition, when the protective element is separately formed, there is a problem that a process of forming a diffusion layer to be the protective element is required, and the manufacturing process becomes complicated.

  The present invention solves the above-mentioned conventional problems, protects the gate of an HFET using a nitride semiconductor from a surge voltage without forming a protective circuit outside, and without complicating the manufacturing process. The object is to realize a high HFET.

  In order to achieve the above object, according to the present invention, a semiconductor device includes a protective diode formed in the same nitride semiconductor layer as a field effect transistor and using a two-dimensional electron gas.

  Specifically, a semiconductor device according to the present invention includes a plurality of nitride semiconductor layers formed on a substrate, an element forming layer having a heterojunction interface, and a source electrode and a drain formed on the element forming layer. Field effect transistor having electrode and gate electrode, p-type nitride semiconductor layer selectively formed on element formation layer, and p-type nitride semiconductor layer formed on element formation layer at a distance from each other And a diode having a pn junction in which a two-dimensional electron gas generated by a heterojunction interface is an n-type region and a p-type nitride semiconductor layer is a p-type region. A current path is configured to be electrically connected to the electrode and to release an excessive current generated in the gate electrode.

  According to the semiconductor device of the present invention, there is provided a diode having a pn junction in which a two-dimensional electron gas generated by a heterojunction interface is an n-type region and a p-type nitride semiconductor layer is a p-type region. Since a current path is formed that is electrically connected to the electrode and releases an excessive current generated in the gate electrode, the gate electrode can be protected from the excessive current. Therefore, it is possible to miniaturize the gate electrode and to form an HFET with extremely high surge resistance. Also, the area occupied by the protection diode is very small. Therefore, an increase in the area occupied by the semiconductor device due to the provision of the protection circuit can be suppressed. Furthermore, since the diode can be formed by forming the third nitride semiconductor layer and the ohmic electrode on the element formation layer, there is almost no increase in the process due to the provision of the protective circuit.

  In the semiconductor device of the present invention, the diode may be electrically connected between the gate electrode and the source electrode, or may be electrically connected between the gate electrode and the drain electrode. And may be electrically connected to ground.

  The semiconductor device of the present invention further includes an element isolation region formed on the substrate and separating the element formation layer into a plurality of element formation regions, and the field effect transistor and the diode are formed in different element formation regions. It is preferable.

  In the semiconductor device of the present invention, it is preferable that a plurality of diodes are formed, and at least two of the plurality of diodes are electrically connected to each other in series. By adopting such a configuration, surge resistance can be further improved.

  The semiconductor device of the present invention further includes an element isolation region that is formed on the substrate and isolates the element formation layer into a plurality of element formation regions, and the field effect transistor and each diode are formed in different element formation regions. It is preferable.

  In the semiconductor device of the present invention, two of the plurality of diodes constitute a diode pair whose anodes are electrically connected to each other, and the diode pair constitutes an anode electrically connected to each other The p-type nitride semiconductor layer is preferably composed of two ohmic electrodes formed on both sides of the p-type nitride semiconductor layer. With such a configuration, the gate electrode can be protected regardless of whether the surge is positive or negative. Further, since the anode is common, the area occupied by the p-type nitride semiconductor layer is also reduced. Therefore, the increase in size accompanying the formation of the diode can be further reduced. Further, the manufacturing process can be simplified.

  The semiconductor device of the present invention further includes an element isolation region that is formed on the substrate and isolates the element formation layer into a plurality of element formation regions, and the two diodes constituting the diode pair are formed in one element formation region. It is preferable that By adopting such a configuration, the area occupied by the diode can be reduced as compared with the case where each diode is formed independently.

  In this case, a plurality of diode pairs are preferably formed. By adopting such a configuration, surge resistance can be further improved.

  In the semiconductor device of the present invention, the substrate has conductivity, the first via plug that electrically connects the source electrode and the substrate, and the opposite side of the diode connected to the gate electrode of the plurality of diodes. It is preferable to further include a second via plug that electrically connects the ohmic electrode of the diode connected to the terminal of the second via plug. Further, the substrate has conductivity, and is connected to a first via plug that electrically connects the drain electrode and the substrate, and a terminal opposite to the diode connected to the gate electrode of the plurality of diodes. And a second via plug that electrically connects the ohmic electrode of the diode. With such a configuration, the terminal diode and the source electrode or the drain electrode are electrically connected by the substrate, so that the formation of the wiring is facilitated. Moreover, it becomes easy to release an excessive current by grounding the substrate.

  According to the present invention, it is possible to protect the gate of an HFET using a nitride semiconductor from a surge voltage without forming a protection circuit outside and without complicating the manufacturing process, thereby realizing an HFET with high surge resistance.

(First embodiment)
A semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. 1A and 1B show a semiconductor device according to the first embodiment. FIG. 1A shows an equivalent circuit, and FIG. 1B shows a cross-sectional configuration. As shown in FIG. 1, the semiconductor device according to the present embodiment includes a heterojunction field effect transistor (HFET) and a protection diode connected between the gate and the source of the HFET.

As shown in FIG. 1B, on a substrate 11 made of sapphire, a first semiconductor layer 12 made of GaN and a second semiconductor layer 13 made of i-Al _0.26 Ga _0.74 N are formed. The element formation layers 10 that are sequentially stacked are formed. On the first region 10A of the element formation layer 10, a source electrode 14 and a drain electrode 15 which are ohmic electrodes are formed with a space therebetween, and a gate electrode 16 is formed between them, and the HFET 1 is formed. ing.

On the second region 10B separated from the first region 10A of the element formation layer 10 by the element isolation region 20, an ohmic contact with the third semiconductor layer 17 made of p-type Al _0.26 Ga _0.74 N is formed. The electrode 18 is formed at an interval. As described above, when the p-type third semiconductor layer 17 is formed on the element formation layer 10 having the heterojunction interface, the two-dimensional electron gas (2DEG) generated at the heterojunction interface is set as the n-type region, A pn junction is formed using the third semiconductor layer 17 as a p-type region. Therefore, by forming the ohmic electrode 18 on the element forming layer 10, the first pn junction diode 2 having the third semiconductor layer 17 as an anode and the ohmic electrode 18 as a cathode is formed.

  In the present embodiment, the second pn junction diode 3 having the same configuration as the first pn junction diode 2 is formed in the third region 10C separated from the second region 10B by the further element isolation region 20. .

  The third semiconductor layer 17 that is the anode of the first pn junction diode 2 and the gate electrode 16 of the HFET 1 are electrically connected by a wiring 30. In addition, the ohmic electrode 18 that is the cathode of the first pn junction diode 2 and the third semiconductor layer 17 that is the anode of the second pn junction diode 3 are electrically connected by the wiring 31, and the second pn junction is formed. The ohmic electrode 18 that is the cathode of the diode 3 and the source electrode 14 of the HFET 1 are electrically connected by a wiring 32. The third semiconductor layer 17 may be connected to the wiring 30 and the wiring 31 by forming an electrode (not shown) made of platinum or the like on the third semiconductor layer 17 and through the formed electrode.

  As a result, the first pn junction diode 2 and the second pn junction diode 3 are connected in series between the gate and source of the HFET 1 shown in FIG. 1A, and the excessive current applied to the gate electrode 16 is released. Current path is formed.

  Thus, since the first pn junction diode 2 and the second pn junction diode 3 connected between the gate and the source function as a protection circuit, the surge resistance of the HFET 1 can be improved. Further, the first pn junction diode 2 and the second pn junction diode 3 and the HFET 1 are formed on the same substrate 11, and the size increase due to the diodes is slight. Further, in the present embodiment, the first pn junction diode 2 and the second pn junction diode 3 are formed in a region separated from the HFET 1 by the element isolation region 20 on the element formation layer 10. The third semiconductor layer 17 and the ohmic electrode 18 are formed. Therefore, it is only necessary to add a step of forming a p-type semiconductor layer compared with a normal HFET formation step, and a protective element can be formed with almost no increase in the number of steps.

  By providing a protection circuit having a pn junction diode using 2DEG formed in this way as a protection element, in a general HFET having a gate length of 1 μm, the surge resistance of the HFET, which was conventionally about 300 V, is reduced to about 1 kV. Was able to improve.

  In this embodiment, the diode is connected between the gate and the source. However, a configuration in which the diode is provided between the gate and the drain or between the gate and the ground is also possible depending on the circuit configuration and the protection target. is there. Moreover, it is also possible to combine these. In the present embodiment, an example in which two diodes are connected in series has been described. However, one diode may be used, or three or more diodes may be used depending on the required surge withstand voltage characteristics. A plurality of diodes may be connected in parallel.

The p-type third semiconductor layer 17 may be formed as follows. For example, after the element formation layer 10 is grown on the substrate 11, Al _0.26 Ga _0.74 N doped p-type is subsequently grown. Subsequently, after forming a resist mask that covers a region where the third semiconductor layer 17 is to be formed, the third semiconductor layer 17 may be formed by dry etching using a chlorine-based etchant.

In addition, after the element formation layer 10 is grown, a silicon oxide (SiO ₂ ) film covering a region other than the region where the third semiconductor layer 17 is formed is formed, and then Al _0.26 Ga doped in p-type. _0.74 N may be regrown. When the third semiconductor layer 17 is formed by regrowth, there is an advantage that damage due to etching does not occur.

The material, film thickness, and impurity concentration of the third semiconductor layer 17 may be determined according to the target surge resistance of the HFET. For example, when the general gate length is 1 μm, the surge breakdown voltage is 1 kV. The first pn junction diode 2 and the second pn junction diode 3 are formed using Al _0.26 Ga _0.74 N having a thickness of 150 nm and an impurity concentration of 3 × 10 ¹⁸ cm ^−3. do it.

(One modification of the first embodiment)
A modification of the first embodiment of the present invention will be described below with reference to the drawings. 2A and 2B show a semiconductor device according to a modification of the first embodiment, where FIG. 2A shows an equivalent circuit and FIG. 2B shows a cross-sectional configuration. In FIG. 2, the same components as those of FIG.

  As shown in FIG. 2, in the semiconductor device of this modification, the protection diode is connected between the gate and the drain. The drain electrode 15 of the HFET 1 and the third semiconductor layer 17 that is the anode of the first pn junction diode 2 are connected by a wiring 33. The ohmic electrode 18 that is the cathode of the first pn junction diode 2 and the third semiconductor layer 17 that is the anode of the second pn junction diode 3 are connected by a wiring 34. The ohmic electrode 18 that is the cathode of the second pn junction diode 3 and the gate electrode 16 of the HFET 1 are connected by a wiring 35.

  By connecting the protective diode between the drain and the gate in this way, the HFET can be protected when an excessive current flows on the drain side.

  In the present embodiment, an example in which two diodes are connected in series has been described. However, one diode may be used, or three or more diodes may be used depending on the required surge withstand voltage characteristics. Moreover, you may connect a diode in parallel.

(Second Embodiment)
The second embodiment of the present invention will be described below with reference to the drawings. 3A and 3B show a semiconductor device according to the second embodiment. FIG. 3A shows an equivalent circuit and FIG. 3B shows a cross-sectional configuration. In FIG. 3, the same components as those in FIG.

  As shown in FIG. 3, the semiconductor device according to this embodiment includes an HFET 1 and a diode pair 4 including two diodes that are connected between the gate and the source of the HFET 1 and share an anode.

As shown in FIG. 3B, the ohmic electrode 18 and the ohmic electrode 19 are spaced apart from the first region 10A where the HFET 1 is formed on the element forming layer 10 by the element isolating region 20 and the second region 10B. A third semiconductor layer 17 made of p-type Al _0.26 Ga _0.74 N is formed between the ohmic electrode 18 and the ohmic electrode 19.

  A depletion layer spreads in a region below the third semiconductor layer 17 in the element formation layer 10. Accordingly, the first pn junction diode 2 having the ohmic electrode 18 as a cathode and the third semiconductor layer 17 as an anode, and the second pn junction having the ohmic electrode 19 as a cathode and the third semiconductor layer 17 as an anode. The diode 3 is formed, and it is not necessary to provide an element isolation region for separating the first pn junction diode 2 and the second pn junction diode 3.

  The ohmic electrode 18 of the first pn junction diode 2 is electrically connected to the gate electrode 16 of the HFET 1 by the wiring 30, and the ohmic electrode 19 of the second pn junction diode 3 is electrically connected to the source electrode 14 by the wiring 32. Has been. Therefore, two pn junction diodes are connected in series in opposite directions between the gate and source of the HFET 1.

  Thus, by connecting two diodes between the gate and the source in the opposite directions in series, the gate can be protected in the case of any positive or negative surge.

  In addition, since it is possible to reduce the number of element isolation regions that normally have to be formed in order to form two diodes by one, the area of the element can be further reduced.

  FIG. 4 shows an example of the layout of the semiconductor device of this embodiment. A first element formation region 51 and a second element formation region 52 that are separated from each other by the element isolation region 20 are formed on the substrate 11. The HFET 1 is formed in the first element formation region 51, and the diode pair 4 including the first pn junction diode 2 and the second pn junction diode 3 is formed in the second element formation region 52. Further, a wiring 36 connecting the drain electrode 15 of the HFET 1 and the power supply line, a wiring 30 connecting the gate electrode 16 and the ohmic electrode 18 which is the cathode of the first pn junction diode 2, and the source electrode 14 and the second pn. A wiring 32 that connects the ohmic electrode 19 that is the cathode of the junction diode 3 is formed. The wiring 30, the wiring 32, and the wiring 36 are actually formed by a wiring layer embedded in an interlayer insulating film that covers the element, and a plug that connects the wiring layer and each electrode.

  FIG. 5 shows an example in which the first pn junction diode 2 is formed in the second element formation region 52 and the second pn junction diode 3 is formed in the third element formation region 53. Compared with the case of forming as a diode pair, the area occupied by the element isolation region 20 and the third semiconductor layer 17 is increased. Further, in order to connect the anode of the first pn junction diode 2 and the anode of the second pn junction diode 3, it is necessary to form the anode connection wiring 37. Further, in order to connect the anode connection wiring 37 to the third semiconductor layer 17, it is necessary to form an anode electrode 38 made of platinum or the like on the third semiconductor layer 17.

  Thus, by forming the first pn junction diode 2 and the second pn junction diode 3 as the diode pair 4 as in the semiconductor device of this embodiment, there is one element formation region for forming the diode. In addition, since the number of wirings can be reduced, the occupied area of the semiconductor element can be reduced by about 20%. Further, it is not necessary to form an electrode on the third semiconductor layer 17, and the process can be simplified.

  In the present embodiment, only one diode pair sharing the anode is connected between the gate and the source, but two or more diode pairs may be connected. Further, a diode pair and a diode that does not form a pair may be combined and connected.

(One Modification of Second Embodiment)
A modification of the second embodiment of the present invention will be described below with reference to the drawings. FIG. 6 shows a cross-sectional configuration of a semiconductor device according to a modification of the second embodiment. In FIG. 6, the same components as those of FIG.

  The equivalent circuit of the semiconductor device of this embodiment is the same as that of the semiconductor device of the second embodiment, and two diodes as protective elements are connected back-to-back between the gate and source of the HFET. . As shown in FIG. 6, the semiconductor device of this embodiment is formed on a conductive substrate 41, and a via plug 42 and a second pn junction that electrically connect the source electrode 14 of the HFET and the substrate 41. A via plug 43 that electrically connects the ohmic electrode 19 of the diode 3 and the substrate 41 is formed. As a result, the wiring 32 that electrically connects the ohmic electrode 19 of the second pn junction diode 3 and the source electrode 14 of the HFET 1 becomes unnecessary.

  A silicon substrate may be used as the conductive substrate 41, and a substrate made of silicon carbide or the like may be used. The via plug 42 and the via plug 43 may be formed of a general material, for example, by embedding a material in which titanium and gold are stacked.

  In this modification, an example in which a via plug is provided in the semiconductor device of the second embodiment has been described. However, the configuration of this modification can also be applied to the semiconductor device of the first embodiment.

  In each embodiment and modification, a nitride semiconductor having the same aluminum composition ratio as that of the second semiconductor layer 13 is used for the third semiconductor layer 17. However, the third semiconductor layer 17 may be p-type, A nitride semiconductor having a mixed crystal ratio different from that of the second semiconductor layer 13 may be used.

The composition of the first semiconductor layer 12 and the second semiconductor layer 13 may be any composition as long as a two-dimensional electron gas is generated at the interface between the first semiconductor layer 12 and the second semiconductor layer 13. Two types with different band gaps selected from nitride semiconductors represented by the formula B _w Al _x Ga _y In _z N (where w + x + y + z = 1; 0 ≦ w, x, y, z ≦ 1) The nitride semiconductor can be used.

  Each electrode may be formed of a general material. For example, the source electrode and the drain electrode may be formed of a material in which titanium and aluminum are laminated, a material in which titanium, platinum and gold are laminated, or the like. The gate electrode and the p-type ohmic electrode may be formed of, for example, palladium, palladium silicon, nickel, a material in which nickel and gold are laminated, a material in which palladium, platinum and gold are laminated, or the like.

  The semiconductor device of the present invention can protect a gate of an HFET using a nitride semiconductor from a surge voltage without forming a protective circuit outside and without complicating the manufacturing process, and can realize an HFET having high surge resistance. In particular, the present invention is useful as a field effect transistor using a nitride semiconductor having a protective diode.

(A) And (b) shows the semiconductor device which concerns on the 1st Embodiment of this invention, (a) is a circuit diagram, (b) is sectional drawing. (A) And (b) shows the semiconductor device which concerns on the modification of the 1st Embodiment of this invention, (a) is a circuit diagram, (b) is sectional drawing. (A) And (b) shows the semiconductor device which concerns on the 2nd Embodiment of this invention, (a) is a circuit diagram, (b) is sectional drawing. It is a top view which shows the layout of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a top view which shows the layout of the semiconductor device in case the diode pair is not formed. It is sectional drawing which shows the semiconductor device which concerns on the modification of the 2nd Embodiment of this invention.

Explanation of symbols

1 HFET
2 First pn junction diode 3 Second pn junction diode 4 Diode pair 10 Element formation layer 10A First region 10B Second region 10C Third region 11 Substrate 12 First semiconductor layer 13 Second semiconductor layer 14 Source electrode 15 Drain electrode 16 Gate electrode 17 Third semiconductor layer 18 Ohmic electrode 19 Ohmic electrode 20 Element isolation region 30 Wiring 31 Wiring 32 Wiring 33 Wiring 34 Wiring 35 Wiring 36 Wiring 37 Anode connecting wiring 38 Anode electrode 41 Substrate 42 Via plug 43 Via plug 51 First element formation region 52 Second element formation region 53 Third element formation region

Claims (17)

An element forming layer comprising a plurality of nitride semiconductor layers formed on a substrate and having a heterojunction interface;
A field effect transistor having a source electrode, a drain electrode and a gate electrode formed on the element formation layer;
A p-type nitride semiconductor layer selectively formed on the element formation layer and an ohmic electrode formed on the element formation layer at a distance from the p-type nitride semiconductor layer; A diode having a two-dimensional electron gas generated by the heterojunction interface as an n-type region and the p-type nitride semiconductor layer as a p-type region;
An element isolation region formed on the substrate and separating the element formation layer into a plurality of element formation regions;
The field effect transistor and the diode are formed in different element formation regions,
The diode is electrically connected to the gate electrode;
The semiconductor device according to claim 2, wherein the two-dimensional electron gas constitutes a current path for releasing an excessive current generated in the gate electrode.   The semiconductor device according to claim 1, wherein the diode is electrically connected between the gate electrode and the source electrode.   The semiconductor device according to claim 1, wherein the diode is electrically connected between the gate electrode and the drain electrode.   The semiconductor device according to claim 1, wherein the diode is electrically connected between the gate electrode and ground. A plurality of the diodes are formed,
5. The semiconductor device according to claim 1, wherein at least two of the plurality of diodes are electrically connected to each other in series. 6. Two diodes of the plurality of diodes constitute a diode pair in which anodes are electrically connected to each other;
The diode pair includes the p-type nitride semiconductor layer constituting the anode electrically connected to each other, and the two ohmic electrodes formed on both sides of the p-type nitride semiconductor layer The semiconductor device according to claim 5, comprising:   The semiconductor device according to claim 6, wherein the two diodes constituting the diode pair are formed in one of the element formation regions.   The semiconductor device according to claim 6, wherein a plurality of the diode pairs are formed. The substrate has electrical conductivity;
A first via plug that electrically connects the source electrode and the substrate;
And a second via plug that electrically connects the ohmic electrode of the diode connected to the opposite end of the diode connected to the gate electrode of the plurality of diodes. The semiconductor device according to any one of claims 1 to 8. The substrate has electrical conductivity;
A first via plug that electrically connects the drain electrode and the substrate;
And a second via plug that electrically connects the ohmic electrode of the diode connected to the opposite end of the diode connected to the gate electrode of the plurality of diodes. The semiconductor device according to any one of claims 1 to 8. An element forming layer comprising a plurality of nitride semiconductor layers formed on a substrate and having a heterojunction interface;
An element isolation region formed on the substrate and separating the element formation layer into at least a first element formation region and a second element formation region;
A field effect transistor having a source electrode, a drain electrode and a gate electrode formed on the first element formation region;
A p-type nitride semiconductor layer formed on the second element formation region;
An ohmic electrode formed on the second element formation region and spaced apart from the p-type nitride semiconductor layer;
The gate electrode is electrically connected to a two-dimensional electron gas generated at the heterojunction interface of the second element formation region;
The p-type nitride semiconductor layer and the ohmic electrode are electrically connected via the two-dimensional electron gas ,
The two-dimensional electron gas, a semiconductor device which is characterized that you configure a current path for releasing an excessive current generated in the gate electrode.   The semiconductor device according to claim 11, wherein the gate electrode is electrically connected to the source electrode through the ohmic electrode.   The semiconductor device according to claim 11, wherein the gate electrode is electrically connected to the drain electrode through the ohmic electrode.   The semiconductor device according to claim 11, wherein the gate electrode is electrically connected to ground through the ohmic electrode.   The semiconductor device according to claim 11, wherein the gate electrode is electrically connected to the two-dimensional electron gas through the p-type nitride semiconductor layer.   The semiconductor device according to claim 11, wherein the gate electrode is electrically connected to the two-dimensional electron gas through the ohmic electrode. 17. The semiconductor device according to claim 1, wherein the layer in contact with the p-type nitride semiconductor layer in the element formation layer is a layer that is not doped with an impurity.

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