US20140306284A1 - Semiconductor Device and Method for Producing the Same - Google Patents

Semiconductor Device and Method for Producing the Same Download PDF

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US20140306284A1
US20140306284A1 US13/861,823 US201313861823A US2014306284A1 US 20140306284 A1 US20140306284 A1 US 20140306284A1 US 201313861823 A US201313861823 A US 201313861823A US 2014306284 A1 US2014306284 A1 US 2014306284A1
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region
trench
channel region
gate electrode
transistor
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US13/861,823
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Anton Mauder
Franz Hirler
Hans-Joachim Schulze
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Priority to US13/861,823 priority Critical patent/US20140306284A1/en
Assigned to INFINEON TECHNOLOGIES AUSTRIA AG reassignment INFINEON TECHNOLOGIES AUSTRIA AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SCHULZE, HANS-JOACHIM, MAUDER, ANTON, HIRLER, FRANZ
Priority to DE102014104975.6A priority patent/DE102014104975B4/de
Priority to CN201410144330.8A priority patent/CN104103690B/zh
Publication of US20140306284A1 publication Critical patent/US20140306284A1/en
Priority to US15/003,441 priority patent/US20160155821A1/en
Abandoned legal-status Critical Current

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Definitions

  • This specification refers to embodiments of methods for forming a semiconductor device. Furthermore, this specification refers to embodiments of semiconductor devices with a special channel doping, in particular a field effect semiconductor device having a special channel doping.
  • MOS devices are often arranged in cells in a substrate and have to fulfill a number of properties. However, these properties may influence each other and sometimes require individual measures that may contradict each other. This is particularly relevant for properties such as threshold voltage, channel resistance, short circuit current, short channel effects, and resistance to latch-up.
  • Embodiments of the invention include a trench gate MOS transistor, comprising a semiconductor substrate with a trench including a gate electrode, a source region, and a body contact region adjacent to a channel region.
  • the dopant concentration in the channel region varies in a lateral direction and has at least one minimal value in a direction from the gate electrode to the body contact region, which is distanced from the gate electrode. In some embodiments, the dopant concentration decreases in a lateral direction from the gate electrode to the body contact region.
  • An example method comprises: providing a substrate, etching a trench for a gate electrode, providing a body contact region, providing a channel region located between the trench and the body contact region, applying a doping to implant a dopant into walls of the trench, and diffusing the dopant from the trench walls into the channel region in order to produce a laterally varying doping concentration in the channel region.
  • a doping profile of the channel region in a vertical direction is determined by the position and depth of the trench for the gate electrode, resulting in a self adjustment of the channel region with respect to the gate electrode.
  • FIG. 1 schematically illustrates a vertical cross-section of a vertical semiconductor device according to one or more embodiments.
  • FIG. 2 schematically illustrates a vertical cross-section of a vertical semiconductor device according to one or more embodiments.
  • FIG. 3 schematically illustrates vertical cross-sections of vertical semiconductor devices according to one or more embodiments.
  • FIG. 4 schematically illustrates a vertical cross-section of a vertical semiconductor device according to one or more embodiments.
  • FIG. 5 schematically illustrates a method according to embodiments.
  • horizontal intends to describe an orientation substantially parallel to a first or main horizontal surface of a semiconductor substrate or body. This can be, for instance, the surface of a wafer or a die.
  • vertical as used in this specification is intended to describe an orientation which is substantially arranged perpendicular to the first surface, i.e., parallel to a normal direction with respect to the first surface of the semiconductor substrate or body.
  • an n-doped material or region is referred to as having a first conductivity type, while a p-doped material or region is referred to as having a second conductivity type.
  • the semiconductor devices can be formed with opposite doping relations so that the first conductivity type can be p-doped and the second conductivity type can be n-doped.
  • some Figures illustrate relative doping concentrations by indicating “ ⁇ ” or “+” next to the doping type.
  • “n ⁇ ” means a doping concentration that is less than the doping concentration of an “n”-doping region while an “n + ”-doping region has a larger doping concentration than the “n”-doping region.
  • indicating the relative doping concentration does not mean that doping regions of the same relative doping concentration have to have the same absolute doping concentration unless otherwise stated.
  • two different n + regions can have different absolute doping concentrations. The same applies, for example, to an n + and a p + region.
  • field effect is intended to describe the electric-field mediated formation of a conductive “channel” of a first conductivity type and/or control of conductivity and/or shape of the channel in a semiconductor region of a second conductivity type, typically a body region of the second conductivity type. Due to the field-effect, a unipolar current path through the channel region is formed and/or controlled between a source region or emitter region of the first conductivity type and a drift region of the first conductivity type. The drift region may be in contact with a drain region or a collector region respectively.
  • the drain region or the collector region is in ohmic contact with a drain or collector electrode.
  • the source region or emitter region is in ohmic contact with a source or emitter electrode. Without applying an external voltage between the gate electrode and the source or emitter electrode, the ohmic current path between the source or emitter electrode and the drain or collector electrode through the semiconductor device is broken or at least high-ohmic in normally-off field effect devices.
  • HEMTs High Electron Mobility Transistors
  • depletion MOSFETs Metal Oxide Field Effect Transistors
  • normally-on JFETs normally-on JFETs
  • field-effect structure is intended to describe a structure formed in a semiconductor substrate or semiconductor device having a gate electrode for forming and or shaping a conductive channel in the channel region.
  • the gate electrode is at least insulated from the channel region by a dielectric region or dielectric layer.
  • field plate and “field electrode” are intended to describe an electrode that is arranged next to a semiconductor region, typically a drift region, insulated from the semiconductor region, and configured to expand a depleted portion in the semiconductor region by applying an appropriate voltage, typically a negative voltage relative to the semiconductor region for an n-type drift region.
  • a semiconductor region comprises substantially no free charge carriers.
  • insulated field plates are arranged close to pn-junctions formed, e.g., between a drift region and a body region. Accordingly, the blocking voltage of the pn-junction and the semiconductor device, respectively, may be increased.
  • the dielectric layer or region that insulates the field plate from the drift region is in the following also referred to a field dielectric layer or field dielectric region.
  • the gate electrode and the field plate may be on same electrical potential or on different electrical potential.
  • the field plate may be on source or emitter potential. Furthermore, a portion of the gate electrode may be operated as field electrode.
  • dielectric materials for forming a dielectric region or dielectric layer between the gate electrode or a field plate and the drift region include, without being limited thereto, SiO 2 , Si 3 N 4 , SiO x N y , Al 2 O 3 , ZrO 2 , Ta 2 O 5 , TiO 2 and HfO 2 , as well as mixtures and / or layers of these materials.
  • Embodiments described herein generally relate to trench transistors, wherein a doping of a channel region is produced by employing a plasma doping (PLAD), preferably through a wall of the trench.
  • PAD plasma doping
  • the transistor may, in some embodiments, optionally employ a field plate.
  • FIG. 1 illustrates an embodiment of a semiconductor device 100 in a section of a vertical cross-section.
  • semiconductor device 100 is a power semiconductor device.
  • the shown section typically corresponds to one of a plurality of unit cells in an active area of power semiconductor device 100 .
  • the semiconductor device 100 includes a semiconductor body 40 having a first or main horizontal surface 15 and a second or back surface 16 arranged opposite to the first surface 15 .
  • the normal direction e n of the first surface 15 is substantially parallel to, i.e. defines, the vertical dimension, and the direction e L defines a horizontal or lateral dimension.
  • a monocrystalline semiconductor region or layer is typically a monocrystalline Si-region or Si-layer. It should however be understood that the semiconductor body 40 can be made of any semiconductor material suitable for manufacturing a semiconductor device.
  • Such materials include, without being limited thereto, elementary semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa) or indium gallium arsenide phosphide (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name a few.
  • elementary semiconductor materials such as silicon (Si) or germanium (Ge)
  • group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe
  • heterojunction semiconductor materials include, without being limited thereto, aluminum gallium nitride (AlGaN) and gallium nitride (GaN) or silicon-silicon carbide (Si x C 1 ⁇ x ) and SiGe heterojunction semiconductor material.
  • AlGaN aluminum gallium nitride
  • GaN gallium nitride
  • Si x C 1 ⁇ x silicon-silicon carbide
  • SiGe heterojunction semiconductor material mainly Si, SiC and GaN materials are currently used. If the semiconductor body comprises a wide band gap material such as SiC or GaN, which has a high breakdown voltage and high critical avalanche field strength, respectively, the doping of the respective semiconductor regions can be chosen higher, which reduces the on-resistance R on .
  • a semiconductor body may also include polycrystalline semiconductor regions.
  • a trench gate electrode or a field electrode arranged in an insulated trench may be formed by highly doped n-type of p-type polycrystalline semiconductor regions such as poly-Silicon.
  • the term “exposing a semiconductor body” as used in this specification is intended to describe exposing a monocrystalline semiconductor region of the semiconductor body and/or exposing a polycrystalline semiconductor region arranged in the semiconductor body.
  • semiconductor body 40 includes an n-type first semiconductor region 1 , a p-type second semiconductor region, in the following also called body contact region 2 , which is arranged between first semiconductor region 1 and the main horizontal surface 15 .
  • the first semiconductor region 1 and the p-type body contact region 2 form a pn-junction.
  • An n + -type source region 4 which extends to main surface 15 , forms an additional pn-junction with the p-type body contact region 2 .
  • a channel region 5 is located, in a vertical direction, between n + -type source region 4 and the n-type first semiconductor region 1 . In a horizontal direction, channel region 5 is located between a trench gate 12 and the body contact region 2 .
  • the first semiconductor region 1 , the p-type second semiconductor region, also called body contact region 2 , the source region 4 , and the channel region 5 may be shaped as bars which extend out of the drawing plane.
  • the regions 2 , 4 , 5 may also be ring-shaped, or have the shape of a square with rounded corners when viewed from a top of the device 100 .
  • the structure shown in FIG. 1 and also the following figures corresponds to a respective simply connected semiconductor region.
  • the dopant concentration of the channel region 5 is produced independently from the dopant concentration in the body contact region 2 during manufacturing of the device 100 . This is typically achieved by producing the dopant concentration in the channel region 5 by a different process than the doping of the body contact region 2 .
  • the doping of the channel region 5 is achieved by applying a plasma doping (PLAD). It is typically applied after the trench 20 for the gate electrode 12 has been produced, and after a gate oxide 14 has been applied to the walls of the trench 20 . This is typically carried out before applying the material for gate electrode 12 , which material typically includes polycrystalline silicon.
  • ions are implanted into the gate oxide 14 walls in trench 20 . This is carried out by exposing the semiconductor body 40 with the trench 20 to a plasma of Ar, Kr, Xe, Ne or another noble gas or an inert gas. In a subsequent heating step, part of the ions implanted into the walls of the gate oxide 14 diffuse from the gate oxide 14 in the direction of the channel region 5 , which is p-doped in this process.
  • the parameters of the PLAD process and the subsequent heating step are chosen such that the resulting dopant concentration of the channel region 5 varies in a lateral direction e L , i.e., parallel to semiconductor surface 15 in FIG. 1 .
  • the dopant concentration decreases in the direction e L from the gate oxide 14 towards the body contact region 2 .
  • a channel with a self-adjusted depth with respect to the gate electrode 12 , respectively to gate oxide 14 is achieved.
  • the doping profile of the channel region 5 in a vertical direction is determined by the position and depth of the trench 20 for the gate electrode, resulting in a self adjustment of the channel region 5 with respect to the gate electrode.
  • the resulting dopant concentration in the channel region 5 varies in a lateral direction e L and has at least one minimal value in a direction from the gate electrode 12 to the body contact region 2 .
  • the position of the minimum value is distanced from the gate oxide 14 .
  • the minimum value of the dopant concentration is typically smaller than 70%, more typically smaller than 50%, even more typically smaller than 20% of the maximum value of the dopant concentration in the channel region 5 .
  • the concentration of the dopant decreases towards the body contact region 2 in the direction e L , it is typically chosen to be high enough in order to achieve an ohmic connection of the channel region 5 to the body contact region 2 .
  • the maximum dopant concentration in the channel region 5 may not be located directly at the border region to the gate oxide 14 , but may instead be slightly distanced from it. Hence, in a direction e L from the gate oxide 14 to the body contact region 2 , the dopant concentration in the channel region 5 first increases, and then decreases when proceeding further towards the body contact region 2 in direction e L . However, the position of this local maximum is typically distanced by no more than 10% or no more than 20% of the distance d from the gate oxide 14 , wherein d is the distance between gate oxide 14 and the body contact region 2 . Hence, typically the maximum of the dopant concentration in the channel region 5 is located adjacent the gate electrode 12 and gate oxide 14 .
  • the position of the minimum value of the dopant concentration in the channel region 5 is distanced from the gate oxide 14 by more than 70% of the distance d between gate oxide 14 and channel region 5 , even more typically by more than 90% of distance d.
  • a semiconductor device 100 typically comprises a field plate 10 .
  • the field plate 10 and the body contact region 2 reach further into the first semiconductor region 1 in a vertical direction e n than the channel region 5 .
  • the field plate extends more than 20% deeper, more typically more than 30% deeper into the semiconductor first region 1 than the channel region 5 .
  • the body contact region 2 is typically doped more strongly than the channel region 5 .
  • the transistor blocks there is no buildup of a space-charge region of any considerable width in the p-doped channel region 5 . Effects that are caused by a dynamic reduction of the channel length, such as in case of short circuit and respective short circuit currents, are thus strongly reduced.
  • a further advantageous effect of the structure 100 according to embodiments is that the distance between the channel region 5 and the more highly doped body contact region 2 may be designed to be smaller than in a structure with an identical dopant concentration in body contact region 2 and channel region 5 .
  • the device 100 according to embodiments has an improved robustness against the latchup effect.
  • There are certain operation modes when the maximum blocking voltage of the device 100 is exceeded e. g., when turning off an inductive load without providing a free wheeling circuit, and a load current is sustained by generation of pairs of electrons and holes in regions of high electric fields.
  • the highest electric fields and thus the highest generation rates may occur, e.
  • the laterally varying dopant concentration in channel region 5 is produced differently to the manufacturing method described above.
  • a body contact region 2 is first produced, wherein the p-dopant concentration is higher than the concentration which would be necessary for achieving a desired threshold voltage.
  • a compensating n-doping is applied via PLAD through the walls of trench 20 to channel region 5 , i.e., through the gate oxide 14 .
  • the introduction of the doping of the channel region 5 via the walls of the trench 20 allows a realisation of the channel in a self-adjusted manner with respect to the trench gate 12 .
  • the gate oxide 14 in trench 20 thereby serves as a mask for the PLAD process, prior to the application of the gate 12 .
  • a vertical distance oxide 19 may be placed in a vertical direction above the gate oxide 14 and the field plate 10 .
  • the parts of the gate trench that are only covered by thin layers like, for example, the gate oxide 14 do not shield the doping of the channel region 5 .
  • the end of the channel region is therefore adjusted to the lower end of the later gate electrode 12 , minimizing geometrical overlap and thus stray capacitances.
  • a conductive path for carriers from the channel into the drift region 1 is ensured.
  • the unwanted doping of semiconductor material below the gate trench 20 is ensured by the field plate 10 and the field electrode 17 .
  • the highly doped body contact region 2 is typically realized via a masked implantation, for example, by using ions of varying energy levels during implantation.
  • a second trench 3 for the body contact region 2 may be etched. Subsequently, the second trench is filled by adding to the walls of this trench, in various non-limiting examples, one or more of the following: polycrystalline silicon, boron silica glass (BSG), which may then be treated and activated by ion implantation or plasma doping (PLAD).
  • BSG boron silica glass
  • the bottom of the trench 20 may optionally be covered by an auxiliary layer 18 (delimited upwards by dashed line), essentially leaving open the trench sidewall to prevent the doping of the channel region 5 reaching deeper into the semiconductor device 100 in a vertical direction e n .
  • This auxiliary layer 18 may consist of a polymer, such as a photo-resist, for example, and may be removed during the later process steps. In some embodiments, it may consist of a dielectric material, such as SiO 2 , which may be only partially removed or may even remain at the bottom of the gate trench.
  • the doping of channel region 5 may also be achieved using tilted-ion implantation, in case in twin mode or quad mode, i. e. using implantation under different angles.
  • the doping of the channel region 5 may take place before finalizing the gate oxide 14 .
  • a thin scatter layer e. g., a scatter oxide, is covering the sidewall of the trench 20 when the doping of the channel region 5 is done.
  • the gate oxide may be generated by thermal oxidation and/or deposition process.
  • the channel region 5 may be doped with a second conductivity type leading, e. g., to an enhancement MOSFET.
  • the channel region 5 may be doped with a first conductivity type leading, e. g., to a depletion MOSFET.
  • a first metallization 8 is arranged on parts of main horizontal surface 15 .
  • a second metallization 9 is arranged on back surface 16 .
  • the back surface 16 delimits a strongly doped contact zone 13 on the back side of the semiconductor body 40 .
  • Semiconductor device 100 includes a trench gate electrode 12 structure arranged in a deep trench 20 . Accordingly, semiconductor device 100 may be operated as a vertical field effect semiconductor device which switches and/or controls a load current between the two metallizations 8 , 9 .
  • Semiconductor device 100 may form a MOSFET.
  • drift region 1 is in ohmic connection with the second metallization 9 forming a drain electrode via an n + -type drain contact region 13 .
  • first metallization 8 forms a source electrode 8 that is in ohmic connection with source region 4 and with p + -type body contact region 2 .
  • the doping concentrations of source region 4 and body contact region 2 are typically higher than the doping concentration of first semiconductor region 1 forming drift region 1 .
  • the terms “in ohmic contact”, “in electric contact”, “in contact”, “in ohmic connection”, and “electrically connected” are intended to describe that there is an ohmic electric connection or ohmic current path between two regions, portion or parts of a semiconductor devices, in particular a connection of low-ohmic resistance, even if no voltages are applied to the semiconductor device.
  • Semiconductor device 100 may also form an IGBT.
  • a p + -type contact zone 13 of the semiconductor forms a collector region 13 , which is arranged between drift region 1 and the second metallization 9 , forming a collector electrode 9 .
  • first metallization 8 forms an emitter electrode 8 which is in ohmic connection with a p + -type body contact region 2 .
  • Contact zone 13 may also include n-type and p-type portions so that semiconductor device 100 may be operated as an IGBT with integrated free-wheeling diode.
  • the deep trench 20 extends from the main horizontal surface 15 , past the source region 4 , the channel region 5 , and partially into the first semiconductor region 1 .
  • the deep trench 20 extends vertically below the pn-junction formed between the drift region 1 and the body contact region 2 .
  • the deep trench 20 is insulated from semiconductor body 40 by a thin dielectric layer 14 and includes a respective conductive region 12 .
  • the thin dielectric layer 14 is in the following also referred to as gate oxide 14 or gate oxide layer 14 .
  • conductive region 12 forms a gate electrode 12 which is electrically connected to a gate metallization (not shown) and terminal Ga.
  • Lower portions of conductive region 12 may in embodiments also form a field electrode 10 as shown in FIG. 1 .
  • the thin dielectric layer 14 is typically thickened in the respective lower trench portion, carrying the field electrode 10 , to form a thicker field oxide.
  • the trench 20 is formed in an etching process and filled with a polycrystalline semiconductor material. This also facilitates manufacturing of semiconductor device 100 .
  • semiconductor device 100 may be operated as a MOSFET or an IGBT.
  • the gate electrode 12 in FIG. 1 is located over a field electrode 10 surrounded by a field dielectric. But this is only an example.
  • the width d g of the trench 20 in a lateral direction e L at the gate electrode may be the same or may be wider than the width d f of the trench 20 in a lateral direction e L at the field plate.
  • the field electrode 12 and the field dielectric may be omitted so that also the lower part of the gate dielectric 14 at the bottom of the trench 20 is in direct contact with the drift region 1 .
  • FIG. 2 an embodiment based on the device of FIG. 1 is shown. Additionally, the dopant concentration of the body contact region 2 is also varied, in addition to the variation of the doping of the channel region 5 already described above. However, the dopant concentration of the body contact region is varied in a vertical direction e n , such that an additional body contact region 6 exists with a lower dopant concentration than the body contact region 2 .
  • the effect is that in the border region of zone 6 towards first semiconductor region 1 respectively drift region 1 , the concentration of acceptors is lower, and the field stop is not fully depleted of mobile carriers or holes provided by the doping of zone 6 in the state of static blocking—for this case, the dashed line in FIG. 2 marks the end of the space charge region. Only at higher current densities, the space-charge region extends deeper into the body contact region 2 , which increases the blocking voltage and leads to a stabilization of the characteristics in avalanche operation.
  • FIG. 3 shows a semiconductor device 100 according to embodiments.
  • the channel region 5 should end in the vertical direction e n before the end of the gate electrode 12 is reached.
  • the drift zone 1 is adjacent to the gate dielectric 14 .
  • deviations in the process e. g., diffusion or scattering during the doping process, may lead to the insertion of dopants from the channel region 5 to the drift zone 1 , reducing the conductivity of the drift zone 1 close to the channel end.
  • One additional topic is a very high current density of the electron current at the end of the inversion channel. This high current density has to spread to a more homogeneous current density towards the way to the contact zone 13 .
  • a high conductivity of the drift zone 1 close to the end of the inversion channel helps to disproportionately reduce the onstate resistance of the semiconductor device 100 .
  • an n-doped channel connection zone 7 is provided at the end region of channel region 5 towards the trench 20 , in the lower vertical section of channel region 5 .
  • the zone 7 may be applied with a higher n-doping.
  • the zone 7 is produced after back-etching the field oxide layer 17 , so that it may reach deeper into the device 100 than the gate electrode 12 . Without the channel connection zone 7 , the resulting inversion channel in the channel region 5 might show a reduced conductivity at the end of channel region 5 .
  • FIG. 4 a further device 100 according to embodiments is shown.
  • the body contact region 2 is implanted via a deep reaching contact hole 3 , and subsequently annealed, respectively only lightly diffused.
  • This embodiment may also be combined with the channel connection zone 7 shown in FIG. 3 .
  • a method 300 for forming a vertical semiconductor comprises providing a substrate in a block 301 , etching a trench for a gate electrode in a block 302 , providing a body contact region in a block 303 , providing a channel region located between the trench and the body contact region in a block 304 , applying a doping to implant a dopant into walls of the trench in a block 305 , and diffusing the dopant from the trench walls into the channel region in order to produce a laterally varying doping concentration in the channel region in a block 306 .
  • the doping is a plasma doping.

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