US20140159050A1 - Field effect transistor and method of fabricating the same - Google Patents

Field effect transistor and method of fabricating the same Download PDF

Info

Publication number
US20140159050A1
US20140159050A1 US13/935,096 US201313935096A US2014159050A1 US 20140159050 A1 US20140159050 A1 US 20140159050A1 US 201313935096 A US201313935096 A US 201313935096A US 2014159050 A1 US2014159050 A1 US 2014159050A1
Authority
US
United States
Prior art keywords
layer
electrode
insulating layer
opening
planarization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/935,096
Inventor
Hyung Sup Yoon
Byoung-Gue Min
Jong-won Lim
Hokyun Ahn
Seong-ll Kim
Sang-Heung Lee
Dong Min Kang
Chull Won JU
Jae Kyoung Mun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Electronics and Telecommunications Research Institute ETRI
Original Assignee
Electronics and Telecommunications Research Institute ETRI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Electronics and Telecommunications Research Institute ETRI filed Critical Electronics and Telecommunications Research Institute ETRI
Assigned to ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE reassignment ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MUN, JAE KYOUNG, AHN, HOKYUN, JU, CHULL WON, KANG, DONG MIN, KIM, SEONG-IL, LEE, SANG-HEUNG, LIM, JONG-WON, MIN, BYOUNG-GUE, YOON, HYUNG SUP
Publication of US20140159050A1 publication Critical patent/US20140159050A1/en
Priority to US14/633,984 priority Critical patent/US9634112B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28264Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • H01L29/404Multiple field plate structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • H01L21/28593Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T asymmetrical sectional shape

Definitions

  • Example embodiments of the inventive concept relate to a field effect transistor and a method of fabricating the same, and in particular, to a high-voltage field effect transistor and a method of fabricating the same.
  • a high electron mobility transistor one of compound semiconductor devices, is configured to include one or more layers having very different lattice constants from other layers and thereby its channel layer can have a modified property. Such a lattice mismatch is used to produce a stress improving electron mobility of the channel layer, in the HEMT devices.
  • the HEMT can have improved characteristics of power and noise, due to the increase of charge density and high electron mobility in the channel layer, and thus, it can be operated at a higher frequency. Since the HEMT is superior to silicon-based devices in terms of electron mobility, it is widely used for microwave and millimeter-wave applications.
  • Gallium nitride one of nitride semiconductors, is a direct transition semiconductor with a high electron speed of about 2 ⁇ 10 7 cm/s and a high breakdown electric field of about 3 ⁇ 10 6 V/cm, and thus, there is an increasing interest in the use of GaN as a new material for high frequency devices.
  • the nitride semiconductors makes it possible to realize as a heterojunction structure, such as AlGaN/GaN, and can be selectively doped, and thus, the use of nitride semiconductor makes it possible to realize a high speed device.
  • the nitride semiconductor can improve significantly a trade-off relationship between a cutoff frequency (ft) and a breakdown voltage (V BV ), which is one of technical issues of conventional field effect transistors. Accordingly, the use of the nitride semiconductor makes it possible to realize electronic devices with high voltage and high frequency property.
  • nitride-semiconductor-based FET By using the nitride-semiconductor-based FET, it is possible to simplify or remove a peripheral circuit, such as a power distribution/synthesis circuit and a direct current (DC) converting circuit, and thereby to realize a high power amplifier module with high power efficiency.
  • a peripheral circuit such as a power distribution/synthesis circuit and a direct current (DC) converting circuit
  • a T-, Y-, or mushroom-shaped gate electrode having an increased sectional area is used for a high speed semiconductor device.
  • the T-, Y-, or mushroom-shaped gate electrode is generally formed using an E-beam lithography or photolithography process.
  • Example embodiments of the inventive concept provide a field effect transistor including a ⁇ -shaped gate electrode capable of improving characteristics of stability, parasitic capacitance, parasitic resistance, and cut-off frequency of the transistor.
  • a field effect transistor may include a capping layer disposed on a substrate, a source ohmic electrode and a drain ohmic electrode disposed, spaced apart from each other, on the capping layer, a first insulating layer and a second insulating layer sequentially stacked on the capping layer to cover the source and drain ohmic electrodes, a ⁇ -shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode through the second insulating layer, the first insulating layer and the capping layer, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer provided on the second insulating layer to cover the ⁇ -shaped gate electrode, and a first electrode provided on the first planarization layer and connected to the source ohmic electrode or the drain ohmic electrode through the first planarization layer, the second insulating
  • the capping layer defines an undercut region formed adjacent to the leg portion of the ⁇ -shaped gate electrode.
  • the capping layer may include undoped gallium nitride.
  • the leg portion of the ⁇ -shaped gate electrode has a section shaped like a letter ‘Y’.
  • the substrate may include a silicon carbide substrate, an aluminum nitride buffer layer, an undoped gallium nitride channel layer, an undoped aluminum gallium nitride spacer layer, and an undoped aluminum gallium nitride Schottky layer that may be sequentially stacked.
  • the first insulating layer may include alumina
  • the second insulating layer may include silicon nitride
  • the first planarization layer may include benzocyclobutene.
  • the field effect transistor may further include at least one second planarization layer provided on the first planarization layer to cover the first electrode, and a second electrode provided on the second planarization layer and connected to the first electrode through the second planarization layer.
  • the field effect transistor may further include a protection layer provided on the second planarization layer to cover the second electrode.
  • a method of fabricating a field effect transistor may include forming a capping layer on a substrate, forming a source ohmic electrode and a drain ohmic electrode on the capping layer to be spaced apart from each other, sequentially forming a first insulating layer and a second insulating layer on the capping layer to cover the source and drain electrodes, forming a photoresist layer with a first opening exposing a portion of the second insulating layer between the source and drain ohmic electrodes, partially etching the second and first insulating layers using the photoresist layer as an etch mask to define a second opening, removing the photoresist layer, partially etching the capping layer using the first and second insulating layers defining the second opening as an etch mask to form a third opening partially exposing the substrate, forming a ⁇ -shaped gate electrode with a leg portion connected to the substrate through the third opening and a head portion covering a top surface of the second
  • the capping layer may be formed of undoped gallium nitride.
  • the first insulating layer may be formed of alumina and the second insulating layer may be formed of silicon nitride.
  • the defining of the second opening may include partially etching the second and first insulating layers using the photoresist layer as an etch mask to form a preliminary second opening having substantially the same width as that of the first opening, and selectively etching the second insulating layer to define a Y-shaped second opening.
  • the defining of the third opening may include etching a portion of the capping layer using the first and second insulating layers with the second opening as an etch mask, and the capping layer may be formed to define an undercut region, whose width may be greater than that of the first opening.
  • the leg portion of the ⁇ -shaped gate electrode may be formed spaced apart from the capping layer, and thereby the third opening may be not filled with the leg portion.
  • the substrate may be a stack of a silicon carbide substrate, an aluminum nitride buffer layer, an undoped gallium nitride channel layer, an undoped aluminum gallium nitride spacer layer, and an undoped aluminum gallium nitride Schottky layer that may be sequentially stacked.
  • the first planarization layer may be formed of benzocyclobutene.
  • the forming of the ⁇ -shaped gate electrode may include forming a photoresist mold layer on the second insulating layer to define a fourth opening, whose width may be greater than those of the first to third openings, forming conductive layers in the third and fourth openings and on the photoresist mold layer, and removing the photoresist mold layer and the conductive layer on the photoresist mold layer.
  • the method may further include forming at least one second planarization layer on the first planarization layer to cover the first electrode, and forming a second electrode on the second planarization layer, the second electrode being connected to the first electrode through the second planarization layer.
  • the method may further include forming a protection layer on the second planarization layer to cover the second electrode.
  • FIG. 1 is a sectional view illustrating a field effect transistor according to example embodiments of the inventive concept.
  • FIGS. 2A through 2G are sectional views illustrating a method of fabricating a field effect transistor, according to example embodiments of the inventive concept.
  • Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.
  • Example embodiments of the inventive concepts may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those of ordinary skill in the art.
  • the thicknesses of layers and regions are exaggerated for clarity.
  • Like reference numerals in the drawings denote like elements, and thus their description will be omitted.
  • first”, “second”, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.
  • spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • Example embodiments of the inventive concepts are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments of the inventive concepts should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region.
  • a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • FIG. 1 is a sectional view illustrating a field effect transistor according to example embodiments of the inventive concept.
  • a field effect transistor may include a substrate, a capping layer 15 , source and drain ohmic electrodes 16 , first and second insulating layers 17 and 18 , a ⁇ -shaped gate electrode 23 , first, second, and third planarization layers 25 , 27 and 29 , first, second, and third electrodes 26 , 28 , and 30 , and a protection layer 31 .
  • the substrate may include a silicon carbide (SiC) substrate 10 , an aluminum nitride (AlN) buffer layer 11 , an undoped gallium nitride (GaN) channel layer 12 , an undoped aluminum gallium nitride (AlGaN) spacer layer 13 , and an undoped aluminum gallium nitride Schottky layer 14 , which may be sequentially stacked.
  • SiC silicon carbide
  • AlN aluminum nitride
  • GaN undoped gallium nitride
  • AlGaN undoped aluminum gallium nitride
  • the capping layer 15 may be provided on the Schottky layer 14 of the substrate.
  • the capping layer 15 may include undoped gallium nitride.
  • the source and drain ohmic electrodes 16 may be provided spaced apart from each other on the capping layer 15 .
  • the source and drain ohmic electrodes 16 may include a conductive material.
  • the source and drain ohmic electrodes 16 may include an alloy, which may be formed by performing a rapid thermal annealing process to a stack of titanium/aluminum/nickel/gold or of titanium/aluminum/nickel/palladium/gold.
  • the first insulating layer 17 and the second insulating layer 18 may be sequentially stacked on the capping layer 15 to cover the source and drain ohmic electrodes 16 .
  • the first insulating layer 17 may include alumina (Al 2 O 3 ), and the second insulating layer 18 may include silicon nitride (SiN).
  • the ⁇ -shaped gate electrode 23 may include a leg portion, which penetrates the second insulating layer 18 , the first insulating layer 17 , and the capping layer 15 and is connected to a portion of the substrate between the source and drain ohmic electrodes 16 , and a head portion extending to cover partially a top surface of the second insulating layer 18 .
  • the ⁇ -shaped gate electrode 23 may include a heat-resisting metal.
  • the ⁇ -shaped gate electrode 23 may be a multi-layered structure of nickel/gold or platinum/nickel/tungsten nitride/gold.
  • the head portion of the ⁇ -shaped gate electrode 23 may extend horizontally from the leg portion in an asymmetric manner.
  • a length of the head portion extending toward the drain ohmic electrode 16 may be greater than that toward the source ohmic electrode 16 .
  • the leg portion of the ⁇ -shaped gate electrode 23 may be shaped like a letter ‘Y’.
  • the capping layer 15 may be formed to define an undercut region 22 adjacent to the leg portion of ⁇ -shaped gate electrode 23 .
  • the first planarization layer 25 may be provided on the second insulating layer 18 to cover the ⁇ -shaped gate electrode 23 .
  • the first planarization layer 25 may include a low-k dielectric material, e.g., BenzoCycloButene (BCB).
  • BCB BenzoCycloButene
  • the first electrode 26 may be connected to the source ohmic electrode 16 or the drain ohmic electrode 16 through the first planarization layer 25 , the second insulating layer 18 , and the first insulating layer 17 .
  • the first electrode 26 may include a portion covering a top surface of the first planarization layer 25 .
  • the first electrode 26 may include a conductive material.
  • the second planarization layer 27 may be provided on the first planarization layer 25 to cover the first electrode 26 .
  • the second electrode 28 may be connected to the first electrode 26 through the second planarization layer 27 .
  • the second electrode 28 may include a portion covering a top surface of the second planarization layer 27 .
  • a third planarization layer 29 may be provided on the second planarization layer 27 to cover the second electrode 28 .
  • the third electrode 30 may be connected to the first electrode 26 through the third planarization layer 29 and the second planarization layer 27 .
  • the third electrode 30 may include a portion covering a top surface of the third planarization layer 29 .
  • Each of the second and third planarization layers 27 and 29 may include a low-k dielectric material, for example, BCB.
  • Each of the second and third electrodes 28 and 30 may include a conductive material.
  • the protection layer 31 may be provided on the third planarization layer 29 to cover the third electrode 30 .
  • the protection layer 31 may include silicon nitride.
  • the field effect transistor may include the ⁇ -shaped gate electrode that may be formed by using an double-layered structure of insulating layers having different etch rates from each other, and thus, it is possible to improve stability of the ⁇ -shaped gate electrode and maintain a small width of the leg portion of the ⁇ -shaped gate electrode. Further, since the field effect transistor includes an insulating layer provided between the head portion of the ⁇ -shaped gate electrode and the substrate, it is possible to improve a drain output property and reduce parasitic capacitance between the ⁇ -shaped gate electrode and the source ohmic electrode and between the ⁇ -shaped gate electrode and the drain ohmic electrode.
  • the ⁇ -shaped gate electrode of the field effect transistor has a reduced length, it is possible to improve a cutoff frequency property and a high frequency property. As a result, it is possible to provide a field effect transistor with improved stability, reduced parasitic capacitance, and high frequency property.
  • FIGS. 2A through 2G are sectional views illustrating a method of fabricating a field effect transistor, according to example embodiments of the inventive concept.
  • a capping layer 15 may be formed on a substrate.
  • the substrate may include a silicon carbide substrate 10 , an aluminum nitride buffer layer 11 , an undoped gallium nitride channel layer 12 , an undoped aluminum gallium nitride spacer layer 13 , and an undoped aluminum gallium nitride Schottky layer 14 , which may be sequentially stacked.
  • the capping layer 15 may be formed of undoped gallium nitride.
  • a source ohmic electrode 16 and a drain ohmic electrode 16 may be formed on the capping layer 15 to be spaced apart from each other.
  • the source and drain ohmic electrodes 16 may be formed of a conductive material.
  • the source and drain ohmic electrodes 16 may be formed of an alloy, which may be formed by performing a rapid thermal annealing process to a stack of titanium/aluminum/nickel/gold or of titanium/aluminum/nickel/palladium/gold. The rapid thermal annealing process may be performed at a temperature of about 850° C.
  • a first insulating layer 17 may be formed on the capping layer 15 to cover the source and drain ohmic electrodes 16 .
  • the first insulating layer 17 may be formed of alumina.
  • the first insulating layer 17 may be formed using an atomic layer deposition (ALD) to have a thickness of about 500 ⁇ .
  • ALD atomic layer deposition
  • a second insulating layer 18 may be formed on the first insulating layer 17 .
  • the second insulating layer 18 may be formed of silicon nitride.
  • the second insulating layer 18 may be formed at a low temperature of about 100° C. using a plasma enhanced chemical vapor deposition (PECVD) and be formed to a thickness of about 2,000 ⁇ .
  • PECVD plasma enhanced chemical vapor deposition
  • a photoresist layer 19 may be formed on the second insulating layer 18 to have a first opening 19 b exposing the second insulating layer 18 between the source and drain ohmic electrodes 16 .
  • the photoresist layer 19 may include PolyMethyl MethAcrylate (PMMA).
  • a preliminary second opening may be formed in first and second insulating layers 17 and 18 to have substantially the same width as that of the first opening 19 b .
  • the formation of the preliminary second opening may include a step of partially etching the second and first insulating layers 18 and 17 using the photoresist layer 19 as an etch mask.
  • the partial etching of the second and first insulating layers 18 and 17 may be performed using an anisotropic dry etching process.
  • the second insulating layer 18 may be selectively etched to define a ‘Y’-shaped second opening 20 in the first and second insulating layers 17 and 18 .
  • the formation of the second opening 20 may be performed using an isotropic plasma etching process, in which sulphur hexafluoride (SF 6 ) gas is used.
  • SF 6 sulphur hexafluoride
  • the photoresist layer 19 may be removed, after the formation of the second opening 20 in the first and second insulating layers 17 and 18 .
  • an etching process may be performed using the first and second insulating layers 17 and 18 with the second opening 20 as an etch mask to remove a portion of the capping layer 15 , and thus, a third opening may be formed to expose a portion of the substrate.
  • the third opening may be formed through the capping layer 15 , the first insulating layer 17 , and the second insulating layer 18 . Further, the third opening may be formed to have an undercut region 22 defined by the capping layer 15 . In example embodiments, the undercut region 22 may be formed to have a width greater than that of the first opening 19 b .
  • the formation of the undercut region 22 may include a step of etching a portion of the capping layer 15 exposed by the second opening 20 using a dry etching process, in which an inductively coupled plasma (ICP) technology is applied.
  • ICP inductively coupled plasma
  • the selective dry etching of the capping layer 15 may be performed using gas containing BCl 3 and/or Cl 2 .
  • a photoresist mold layer 21 may be formed on the second insulating layer 18 to have a fourth opening, whose width is greater than those of the first opening 19 b , the second opening 20 , and the third opening.
  • the fourth opening may be formed to have asymmetric widths with respect to the third opening. For example, in the fourth opening, a region toward the drain ohmic electrode 16 may be wider than other region toward the source ohmic electrode 16 .
  • Conductive layers 21 m and 23 may be formed in the third opening and fourth openings and on the photoresist mold layer 21 .
  • the conductive layers 21 m and 23 may be formed of a heat-resisting metal.
  • the conductive layers 21 m and 23 may be formed of nickel/gold or platinum/nickel/tungsten nitride/gold.
  • the conductive layers 21 m and 23 may be formed using an electron beam vacuum deposition process and thus cover the whole top surface of the resulting structure.
  • the conductive layer 21 m on the photoresist mold layer 21 may be removed by a lift-off process for removing the photoresist mold layer 21 .
  • the conductive layer 21 m and the photoresist mold layer 21 may be simultaneously removed by the same lift-off process.
  • the ⁇ -shaped gate electrode 23 may include a leg portion, which penetrates the second insulating layer 18 , the first insulating layer 17 , and the capping layer 15 and is connected to a portion of the substrate between the source and drain ohmic electrodes 16 , and a head portion extending to cover partially a top surface of the second insulating layer 18 .
  • the head portion may be a portion of the ⁇ -shaped gate electrode 23 extending horizontally and asymmetrically from the leg portion, and a length of the head portion extending toward the drain ohmic electrode 16 may be greater than that toward the source ohmic electrode 16 . This is because the fourth opening has an asymmetric structure with respect to the third opening, as described above.
  • the leg portion of the ⁇ -shaped gate electrode 23 may be shaped like a letter ‘Y’. This is because the second opening 20 is shaped like the letter ‘Y’.
  • the capping layer 15 may be formed to define the undercut region 22 that is provided adjacent to the leg portion of the ⁇ -shaped gate electrode 23 . This is because if the conductive layers 21 m and 23 are formed using the electron beam vacuum deposition process, the undercut region 22 may not be deposited with the conductive layer, owing to the second opening that is located thereon and has a smaller width than the undercut region 22 .
  • the conductive layer 21 m on the photoresist mold layer 21 may be removed by a lift-off process for removing the photoresist mold layer 21 .
  • a first planarization layer 25 may be formed on the second insulating layer 18 to cover the ⁇ -shaped gate electrode 23 .
  • the first planarization layer 25 may be formed of a low-k dielectric material, e.g., benzocyclobutene.
  • a first electrode 26 may be formed on the first planarization layer 25 .
  • the first electrode 26 may be connected to the source ohmic electrode 16 or the drain ohmic electrode 16 through the first planarization layer 25 , the second insulating layer 18 , and the first insulating layer 17 .
  • the first electrode 26 may be formed of a conductive material.
  • a second planarization layer 27 may be formed on the first planarization layer 25 to cover the first electrode 26 . Thereafter, a second electrode 28 may be formed on the second planarization layer 27 . The second electrode 28 may be connected to the first electrode 26 through the second planarization layer 27 . A third planarization layer 29 may be formed on the second planarization layer 27 to cover the second electrode 28 . A third electrode 30 may be formed on the third planarization layer 29 . The third electrode 30 may be connected to the first electrode 26 through the third planarization layer 29 and the second planarization layer 27 . Each of the second and third planarization layers 27 and 29 may be formed of a low-k dielectric material, e.g., benzocyclobutene. Each of the second and third electrodes 28 and 30 may be formed of a conductive material.
  • a protection layer 31 may be formed on the third planarization layer 29 to cover the third electrode 30 .
  • the protection layer 31 may be formed of silicon nitride.
  • the ⁇ -shaped gate electrode of the field effect transistor may be formed by using an double-layered structure of insulating layers having different etch rates from each other, and thus, it is possible to improve stability of the ⁇ -shaped gate electrode and maintain a small width of the leg portion of the ⁇ -shaped gate electrode. Further, since the field effect transistor includes an insulating layer provided between the head portion of the ⁇ -shaped gate electrode and the substrate, it is possible to improve a drain output property and reduce parasitic capacitance between the ⁇ -shaped gate electrode and the source ohmic electrode and between the ⁇ -shaped gate electrode and the drain ohmic electrode.
  • the ⁇ -shaped gate electrode of the field effect transistor has a reduced length, it is possible to improve a cutoff frequency property and a high frequency property. As a result, it is possible to provide a method of fabricating a field effect transistor with improved stability, reduced parasitic capacitance, and high frequency property.

Abstract

A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a Γ-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the Γ-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2012-0144126, filed on Dec. 12, 2012, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.
  • BACKGROUND OF THE INVENTION
  • Example embodiments of the inventive concept relate to a field effect transistor and a method of fabricating the same, and in particular, to a high-voltage field effect transistor and a method of fabricating the same.
  • A high electron mobility transistor (HEMT), one of compound semiconductor devices, is configured to include one or more layers having very different lattice constants from other layers and thereby its channel layer can have a modified property. Such a lattice mismatch is used to produce a stress improving electron mobility of the channel layer, in the HEMT devices.
  • There is a difficulty in growing a substrate for the HEMT. For all that, the HEMT can have improved characteristics of power and noise, due to the increase of charge density and high electron mobility in the channel layer, and thus, it can be operated at a higher frequency. Since the HEMT is superior to silicon-based devices in terms of electron mobility, it is widely used for microwave and millimeter-wave applications.
  • Gallium nitride (GaN), one of nitride semiconductors, is a direct transition semiconductor with a high electron speed of about 2×107 cm/s and a high breakdown electric field of about 3×106 V/cm, and thus, there is an increasing interest in the use of GaN as a new material for high frequency devices. The nitride semiconductors makes it possible to realize as a heterojunction structure, such as AlGaN/GaN, and can be selectively doped, and thus, the use of nitride semiconductor makes it possible to realize a high speed device. In addition, the nitride semiconductor can improve significantly a trade-off relationship between a cutoff frequency (ft) and a breakdown voltage (VBV), which is one of technical issues of conventional field effect transistors. Accordingly, the use of the nitride semiconductor makes it possible to realize electronic devices with high voltage and high frequency property.
  • By using the nitride-semiconductor-based FET, it is possible to simplify or remove a peripheral circuit, such as a power distribution/synthesis circuit and a direct current (DC) converting circuit, and thereby to realize a high power amplifier module with high power efficiency.
  • Additionally, to realize better modulating operations and reduced noise characteristics, a T-, Y-, or mushroom-shaped gate electrode having an increased sectional area is used for a high speed semiconductor device. The T-, Y-, or mushroom-shaped gate electrode is generally formed using an E-beam lithography or photolithography process.
  • SUMMARY
  • Example embodiments of the inventive concept provide a field effect transistor including a Γ-shaped gate electrode capable of improving characteristics of stability, parasitic capacitance, parasitic resistance, and cut-off frequency of the transistor.
  • Other example embodiments of the inventive concept provide a method of fabricating a field effect transistor with a Γ-shaped gate electrode that is formed to be able to improve characteristics of stability, parasitic capacitance, parasitic resistance, and cut-off frequency of the transistor.
  • According to example embodiments of the inventive concepts, a field effect transistor may include a capping layer disposed on a substrate, a source ohmic electrode and a drain ohmic electrode disposed, spaced apart from each other, on the capping layer, a first insulating layer and a second insulating layer sequentially stacked on the capping layer to cover the source and drain ohmic electrodes, a Γ-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode through the second insulating layer, the first insulating layer and the capping layer, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer provided on the second insulating layer to cover the Γ-shaped gate electrode, and a first electrode provided on the first planarization layer and connected to the source ohmic electrode or the drain ohmic electrode through the first planarization layer, the second insulating layer, and the first insulating layer.
  • In example embodiments, the capping layer defines an undercut region formed adjacent to the leg portion of the Γ-shaped gate electrode.
  • In example embodiments, the capping layer may include undoped gallium nitride.
  • In example embodiments, the leg portion of the Γ-shaped gate electrode has a section shaped like a letter ‘Y’.
  • In example embodiments, the substrate may include a silicon carbide substrate, an aluminum nitride buffer layer, an undoped gallium nitride channel layer, an undoped aluminum gallium nitride spacer layer, and an undoped aluminum gallium nitride Schottky layer that may be sequentially stacked.
  • In example embodiments, the first insulating layer may include alumina, and the second insulating layer may include silicon nitride.
  • In example embodiments, the first planarization layer may include benzocyclobutene.
  • In example embodiments, the field effect transistor may further include at least one second planarization layer provided on the first planarization layer to cover the first electrode, and a second electrode provided on the second planarization layer and connected to the first electrode through the second planarization layer.
  • In example embodiments, the field effect transistor may further include a protection layer provided on the second planarization layer to cover the second electrode.
  • According to example embodiments of the inventive concepts, a method of fabricating a field effect transistor may include forming a capping layer on a substrate, forming a source ohmic electrode and a drain ohmic electrode on the capping layer to be spaced apart from each other, sequentially forming a first insulating layer and a second insulating layer on the capping layer to cover the source and drain electrodes, forming a photoresist layer with a first opening exposing a portion of the second insulating layer between the source and drain ohmic electrodes, partially etching the second and first insulating layers using the photoresist layer as an etch mask to define a second opening, removing the photoresist layer, partially etching the capping layer using the first and second insulating layers defining the second opening as an etch mask to form a third opening partially exposing the substrate, forming a Γ-shaped gate electrode with a leg portion connected to the substrate through the third opening and a head portion covering a top surface of the second insulating layer, forming a first planarization layer on the second insulating layer to cover the Γ-shaped gate electrode, and forming a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode through the first planarization layer, the second insulating layer, and the first insulating layer.
  • In example embodiments, the capping layer may be formed of undoped gallium nitride.
  • In example embodiments, the first insulating layer may be formed of alumina and the second insulating layer may be formed of silicon nitride.
  • In example embodiments, the defining of the second opening may include partially etching the second and first insulating layers using the photoresist layer as an etch mask to form a preliminary second opening having substantially the same width as that of the first opening, and selectively etching the second insulating layer to define a Y-shaped second opening.
  • In example embodiments, the defining of the third opening may include etching a portion of the capping layer using the first and second insulating layers with the second opening as an etch mask, and the capping layer may be formed to define an undercut region, whose width may be greater than that of the first opening.
  • In example embodiments, the leg portion of the Γ-shaped gate electrode may be formed spaced apart from the capping layer, and thereby the third opening may be not filled with the leg portion.
  • In example embodiments, the substrate may be a stack of a silicon carbide substrate, an aluminum nitride buffer layer, an undoped gallium nitride channel layer, an undoped aluminum gallium nitride spacer layer, and an undoped aluminum gallium nitride Schottky layer that may be sequentially stacked.
  • In example embodiments, the first planarization layer may be formed of benzocyclobutene.
  • In example embodiments, the forming of the Γ-shaped gate electrode may include forming a photoresist mold layer on the second insulating layer to define a fourth opening, whose width may be greater than those of the first to third openings, forming conductive layers in the third and fourth openings and on the photoresist mold layer, and removing the photoresist mold layer and the conductive layer on the photoresist mold layer.
  • In example embodiments, the method may further include forming at least one second planarization layer on the first planarization layer to cover the first electrode, and forming a second electrode on the second planarization layer, the second electrode being connected to the first electrode through the second planarization layer.
  • In example embodiments, the method may further include forming a protection layer on the second planarization layer to cover the second electrode.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The accompanying drawings represent non-limiting, example embodiments as described herein.
  • FIG. 1 is a sectional view illustrating a field effect transistor according to example embodiments of the inventive concept.
  • FIGS. 2A through 2G are sectional views illustrating a method of fabricating a field effect transistor, according to example embodiments of the inventive concept.
  • It should be noted that these figures are intended to illustrate the general characteristics of methods, structure and/or materials utilized in certain example embodiments and to supplement the written description provided below. These drawings are not, however, to scale and may not precisely reflect the precise structural or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of values or properties encompassed by example embodiments. For example, the relative thicknesses and positioning of molecules, layers, regions and/or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numbers in the various drawings is intended to indicate the presence of a similar or identical element or feature.
  • DETAILED DESCRIPTION
  • Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown. Example embodiments of the inventive concepts may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those of ordinary skill in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements, and thus their description will be omitted.
  • It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Like numbers indicate like elements throughout. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items. Other words used to describe the relationship between elements or layers should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” “on” versus “directly on”).
  • It will be understood that, although the terms “first”, “second”, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.
  • Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes” and/or “including,” if used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
  • Example embodiments of the inventive concepts are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments of the inventive concepts should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments of the inventive concepts belong. It will be further understood that terms, such as those defined in commonly-used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
  • FIG. 1 is a sectional view illustrating a field effect transistor according to example embodiments of the inventive concept.
  • Referring to FIG. 1, a field effect transistor may include a substrate, a capping layer 15, source and drain ohmic electrodes 16, first and second insulating layers 17 and 18, a Γ-shaped gate electrode 23, first, second, and third planarization layers 25, 27 and 29, first, second, and third electrodes 26, 28, and 30, and a protection layer 31.
  • The substrate may include a silicon carbide (SiC) substrate 10, an aluminum nitride (AlN) buffer layer 11, an undoped gallium nitride (GaN) channel layer 12, an undoped aluminum gallium nitride (AlGaN) spacer layer 13, and an undoped aluminum gallium nitride Schottky layer 14, which may be sequentially stacked.
  • The capping layer 15 may be provided on the Schottky layer 14 of the substrate. The capping layer 15 may include undoped gallium nitride.
  • The source and drain ohmic electrodes 16 may be provided spaced apart from each other on the capping layer 15. The source and drain ohmic electrodes 16 may include a conductive material. For example, the source and drain ohmic electrodes 16 may include an alloy, which may be formed by performing a rapid thermal annealing process to a stack of titanium/aluminum/nickel/gold or of titanium/aluminum/nickel/palladium/gold.
  • The first insulating layer 17 and the second insulating layer 18 may be sequentially stacked on the capping layer 15 to cover the source and drain ohmic electrodes 16. The first insulating layer 17 may include alumina (Al2O3), and the second insulating layer 18 may include silicon nitride (SiN).
  • The Γ-shaped gate electrode 23 may include a leg portion, which penetrates the second insulating layer 18, the first insulating layer 17, and the capping layer 15 and is connected to a portion of the substrate between the source and drain ohmic electrodes 16, and a head portion extending to cover partially a top surface of the second insulating layer 18. The Γ-shaped gate electrode 23 may include a heat-resisting metal. The Γ-shaped gate electrode 23 may be a multi-layered structure of nickel/gold or platinum/nickel/tungsten nitride/gold. The head portion of the Γ-shaped gate electrode 23 may extend horizontally from the leg portion in an asymmetric manner. A length of the head portion extending toward the drain ohmic electrode 16 may be greater than that toward the source ohmic electrode 16. The leg portion of the Γ-shaped gate electrode 23 may be shaped like a letter ‘Y’. In example embodiments, the capping layer 15 may be formed to define an undercut region 22 adjacent to the leg portion of Γ-shaped gate electrode 23.
  • The first planarization layer 25 may be provided on the second insulating layer 18 to cover the Γ-shaped gate electrode 23. The first planarization layer 25 may include a low-k dielectric material, e.g., BenzoCycloButene (BCB).
  • The first electrode 26 may be connected to the source ohmic electrode 16 or the drain ohmic electrode 16 through the first planarization layer 25, the second insulating layer 18, and the first insulating layer 17. In example embodiments, the first electrode 26 may include a portion covering a top surface of the first planarization layer 25. The first electrode 26 may include a conductive material.
  • The second planarization layer 27 may be provided on the first planarization layer 25 to cover the first electrode 26. The second electrode 28 may be connected to the first electrode 26 through the second planarization layer 27. In example embodiments, the second electrode 28 may include a portion covering a top surface of the second planarization layer 27. A third planarization layer 29 may be provided on the second planarization layer 27 to cover the second electrode 28. The third electrode 30 may be connected to the first electrode 26 through the third planarization layer 29 and the second planarization layer 27. In example embodiments, the third electrode 30 may include a portion covering a top surface of the third planarization layer 29. Each of the second and third planarization layers 27 and 29 may include a low-k dielectric material, for example, BCB. Each of the second and third electrodes 28 and 30 may include a conductive material.
  • The protection layer 31 may be provided on the third planarization layer 29 to cover the third electrode 30. The protection layer 31 may include silicon nitride.
  • According to example embodiments of the inventive concept, the field effect transistor may include the Γ-shaped gate electrode that may be formed by using an double-layered structure of insulating layers having different etch rates from each other, and thus, it is possible to improve stability of the Γ-shaped gate electrode and maintain a small width of the leg portion of the Γ-shaped gate electrode. Further, since the field effect transistor includes an insulating layer provided between the head portion of the Γ-shaped gate electrode and the substrate, it is possible to improve a drain output property and reduce parasitic capacitance between the Γ-shaped gate electrode and the source ohmic electrode and between the Γ-shaped gate electrode and the drain ohmic electrode. Furthermore, since the Γ-shaped gate electrode of the field effect transistor has a reduced length, it is possible to improve a cutoff frequency property and a high frequency property. As a result, it is possible to provide a field effect transistor with improved stability, reduced parasitic capacitance, and high frequency property.
  • FIGS. 2A through 2G are sectional views illustrating a method of fabricating a field effect transistor, according to example embodiments of the inventive concept.
  • Referring to FIG. 2A, a capping layer 15 may be formed on a substrate. The substrate may include a silicon carbide substrate 10, an aluminum nitride buffer layer 11, an undoped gallium nitride channel layer 12, an undoped aluminum gallium nitride spacer layer 13, and an undoped aluminum gallium nitride Schottky layer 14, which may be sequentially stacked. The capping layer 15 may be formed of undoped gallium nitride.
  • A source ohmic electrode 16 and a drain ohmic electrode 16 may be formed on the capping layer 15 to be spaced apart from each other. The source and drain ohmic electrodes 16 may be formed of a conductive material. For example, the source and drain ohmic electrodes 16 may be formed of an alloy, which may be formed by performing a rapid thermal annealing process to a stack of titanium/aluminum/nickel/gold or of titanium/aluminum/nickel/palladium/gold. The rapid thermal annealing process may be performed at a temperature of about 850° C.
  • A first insulating layer 17 may be formed on the capping layer 15 to cover the source and drain ohmic electrodes 16. The first insulating layer 17 may be formed of alumina.
  • The first insulating layer 17 may be formed using an atomic layer deposition (ALD) to have a thickness of about 500 Å.
  • Referring to FIG. 2B, a second insulating layer 18 may be formed on the first insulating layer 17. The second insulating layer 18 may be formed of silicon nitride. In example embodiments, the second insulating layer 18 may be formed at a low temperature of about 100° C. using a plasma enhanced chemical vapor deposition (PECVD) and be formed to a thickness of about 2,000 Å.
  • Referring to FIG. 2C, a photoresist layer 19 may be formed on the second insulating layer 18 to have a first opening 19 b exposing the second insulating layer 18 between the source and drain ohmic electrodes 16. The photoresist layer 19 may include PolyMethyl MethAcrylate (PMMA).
  • A preliminary second opening may be formed in first and second insulating layers 17 and 18 to have substantially the same width as that of the first opening 19 b. The formation of the preliminary second opening may include a step of partially etching the second and first insulating layers 18 and 17 using the photoresist layer 19 as an etch mask. In example embodiments, the partial etching of the second and first insulating layers 18 and 17 may be performed using an anisotropic dry etching process.
  • Referring to FIG. 2D, the second insulating layer 18 may be selectively etched to define a ‘Y’-shaped second opening 20 in the first and second insulating layers 17 and 18. The formation of the second opening 20 may be performed using an isotropic plasma etching process, in which sulphur hexafluoride (SF6) gas is used.
  • The photoresist layer 19 may be removed, after the formation of the second opening 20 in the first and second insulating layers 17 and 18.
  • Referring to FIG. 2E, an etching process may be performed using the first and second insulating layers 17 and 18 with the second opening 20 as an etch mask to remove a portion of the capping layer 15, and thus, a third opening may be formed to expose a portion of the substrate. The third opening may be formed through the capping layer 15, the first insulating layer 17, and the second insulating layer 18. Further, the third opening may be formed to have an undercut region 22 defined by the capping layer 15. In example embodiments, the undercut region 22 may be formed to have a width greater than that of the first opening 19 b. The formation of the undercut region 22 may include a step of etching a portion of the capping layer 15 exposed by the second opening 20 using a dry etching process, in which an inductively coupled plasma (ICP) technology is applied. The selective dry etching of the capping layer 15 may be performed using gas containing BCl3 and/or Cl2.
  • A photoresist mold layer 21 may be formed on the second insulating layer 18 to have a fourth opening, whose width is greater than those of the first opening 19 b, the second opening 20, and the third opening. The fourth opening may be formed to have asymmetric widths with respect to the third opening. For example, in the fourth opening, a region toward the drain ohmic electrode 16 may be wider than other region toward the source ohmic electrode 16.
  • Conductive layers 21 m and 23 may be formed in the third opening and fourth openings and on the photoresist mold layer 21. The conductive layers 21 m and 23 may be formed of a heat-resisting metal. The conductive layers 21 m and 23 may be formed of nickel/gold or platinum/nickel/tungsten nitride/gold. In example embodiments, the conductive layers 21 m and 23 may be formed using an electron beam vacuum deposition process and thus cover the whole top surface of the resulting structure.
  • Except for the Γ-shaped gate electrode 23 provided in the third and fourth openings, the conductive layer 21 m on the photoresist mold layer 21 may be removed by a lift-off process for removing the photoresist mold layer 21. In other words, the conductive layer 21 m and the photoresist mold layer 21 may be simultaneously removed by the same lift-off process.
  • The Γ-shaped gate electrode 23 may include a leg portion, which penetrates the second insulating layer 18, the first insulating layer 17, and the capping layer 15 and is connected to a portion of the substrate between the source and drain ohmic electrodes 16, and a head portion extending to cover partially a top surface of the second insulating layer 18. The head portion may be a portion of the Γ-shaped gate electrode 23 extending horizontally and asymmetrically from the leg portion, and a length of the head portion extending toward the drain ohmic electrode 16 may be greater than that toward the source ohmic electrode 16. This is because the fourth opening has an asymmetric structure with respect to the third opening, as described above. The leg portion of the Γ-shaped gate electrode 23 may be shaped like a letter ‘Y’. This is because the second opening 20 is shaped like the letter ‘Y’.
  • The capping layer 15 may be formed to define the undercut region 22 that is provided adjacent to the leg portion of the Γ-shaped gate electrode 23. This is because if the conductive layers 21 m and 23 are formed using the electron beam vacuum deposition process, the undercut region 22 may not be deposited with the conductive layer, owing to the second opening that is located thereon and has a smaller width than the undercut region 22.
  • Referring to FIG. 2F, the conductive layer 21 m on the photoresist mold layer 21, except for the Γ-shaped gate electrode 23 provided in the third and fourth openings, may be removed by a lift-off process for removing the photoresist mold layer 21.
  • A first planarization layer 25 may be formed on the second insulating layer 18 to cover the Γ-shaped gate electrode 23. The first planarization layer 25 may be formed of a low-k dielectric material, e.g., benzocyclobutene.
  • A first electrode 26 may be formed on the first planarization layer 25. The first electrode 26 may be connected to the source ohmic electrode 16 or the drain ohmic electrode 16 through the first planarization layer 25, the second insulating layer 18, and the first insulating layer 17. The first electrode 26 may be formed of a conductive material.
  • Referring to FIG. 2G, a second planarization layer 27 may be formed on the first planarization layer 25 to cover the first electrode 26. Thereafter, a second electrode 28 may be formed on the second planarization layer 27. The second electrode 28 may be connected to the first electrode 26 through the second planarization layer 27. A third planarization layer 29 may be formed on the second planarization layer 27 to cover the second electrode 28. A third electrode 30 may be formed on the third planarization layer 29. The third electrode 30 may be connected to the first electrode 26 through the third planarization layer 29 and the second planarization layer 27. Each of the second and third planarization layers 27 and 29 may be formed of a low-k dielectric material, e.g., benzocyclobutene. Each of the second and third electrodes 28 and 30 may be formed of a conductive material.
  • A protection layer 31 may be formed on the third planarization layer 29 to cover the third electrode 30. The protection layer 31 may be formed of silicon nitride.
  • According to example embodiments of the inventive concept, the Γ-shaped gate electrode of the field effect transistor may be formed by using an double-layered structure of insulating layers having different etch rates from each other, and thus, it is possible to improve stability of the Γ-shaped gate electrode and maintain a small width of the leg portion of the Γ-shaped gate electrode. Further, since the field effect transistor includes an insulating layer provided between the head portion of the Γ-shaped gate electrode and the substrate, it is possible to improve a drain output property and reduce parasitic capacitance between the Γ-shaped gate electrode and the source ohmic electrode and between the Γ-shaped gate electrode and the drain ohmic electrode. Furthermore, since the Γ-shaped gate electrode of the field effect transistor has a reduced length, it is possible to improve a cutoff frequency property and a high frequency property. As a result, it is possible to provide a method of fabricating a field effect transistor with improved stability, reduced parasitic capacitance, and high frequency property.
  • While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the attached claims.

Claims (20)

What is claimed is:
1. A field effect transistor, comprising:
a capping layer disposed on a substrate;
a source ohmic electrode and a drain ohmic electrode disposed, spaced apart from each other, on the capping layer;
a first insulating layer and a second insulating layer sequentially stacked on the capping layer to cover the source and drain ohmic electrodes;
a Γ-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode through the second insulating layer, the first insulating layer and the capping layer, and the head portion extending from the leg portion to cover a top surface of the second insulating layer;
a first planarization layer provided on the second insulating layer to cover the Γ-shaped gate electrode; and
a first electrode provided on the first planarization layer and connected to the source ohmic electrode or the drain ohmic electrode through the first planarization layer, the second insulating layer, and the first insulating layer.
2. The field effect transistor of claim 1, wherein the capping layer defines an undercut region formed adjacent to the leg portion of the Γ-shaped gate electrode.
3. The field effect transistor of claim 1, wherein the capping layer comprises undoped gallium nitride.
4. The field effect transistor of claim 1, wherein the leg portion of the Γ-shaped gate electrode has a section shaped like a letter ‘Y’.
5. The field effect transistor of claim 1, wherein the substrate comprises a silicon carbide substrate, an aluminum nitride buffer layer, an undoped gallium nitride channel layer, an undoped aluminum gallium nitride spacer layer, and an undoped aluminum gallium nitride Schottky layer that are sequentially stacked.
6. The field effect transistor of claim 1, wherein the first insulating layer comprises alumina, and the second insulating layer comprises silicon nitride.
7. The field effect transistor of claim 1, wherein the first planarization layer comprises benzocyclobutene.
8. The field effect transistor of claim 1, further comprising:
at least one second planarization layer provided on the first planarization layer to cover the first electrode; and
a second electrode provided on the second planarization layer and connected to the first electrode through the second planarization layer.
9. The field effect transistor of claim 8, further comprising a protection layer provided on the second planarization layer to cover the second electrode.
10. A method of fabricating a field effect transistor, comprising:
forming a capping layer on a substrate;
forming a source ohmic electrode and a drain ohmic electrode on the capping layer to be spaced apart from each other;
sequentially forming a first insulating layer and a second insulating layer on the capping layer to cover the source and drain electrodes;
forming a photoresist layer with a first opening exposing a portion of the second insulating layer between the source and drain ohmic electrodes;
partially etching the second and first insulating layers using the photoresist layer as an etch mask to define a second opening;
removing the photoresist layer;
partially etching the capping layer using the first and second insulating layers defining the second opening as an etch mask to form a third opening partially exposing the substrate;
forming a Γ-shaped gate electrode with a leg portion connected to the substrate through the third opening and a head portion covering a top surface of the second insulating layer;
forming a first planarization layer on the second insulating layer to cover the Γ-shaped gate electrode; and
forming a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode through the first planarization layer, the second insulating layer, and the first insulating layer.
11. The method of claim 10, wherein the capping layer is formed of undoped gallium nitride.
12. The method of claim 10, wherein the first insulating layer is formed of alumina and the second insulating layer is formed of silicon nitride.
13. The method of claim 10, wherein the defining of the second opening comprises:
partially etching the second and first insulating layers using the photoresist layer as an etch mask to form a preliminary second opening having substantially the same width as that of the first opening; and
selectively etching the second insulating layer to define a Y-shaped second opening.
14. The method of claim 10, wherein the defining of the third opening comprises etching a portion of the capping layer using the first and second insulating layers with the second opening as an etch mask, and
the capping layer is formed to define an undercut region, whose width is greater than that of the first opening.
15. The method of claim 14, wherein the leg portion of the Γ-shaped gate electrode is formed spaced apart from the capping layer, and thereby the third opening is not filled with the leg portion.
16. The method of claim 10, wherein the substrate is a stack of a silicon carbide substrate, an aluminum nitride buffer layer, an undoped gallium nitride channel layer, an undoped aluminum gallium nitride spacer layer, and an undoped aluminum gallium nitride Schottky layer that are sequentially stacked.
17. The method of claim 10, wherein the first planarization layer is formed of benzocyclobutene.
18. The method of claim 10, wherein the forming of the Γ-shaped gate electrode comprises:
forming a photoresist mold layer on the second insulating layer to define a fourth opening, whose width is greater than those of the first to third openings;
forming conductive layers in the third and fourth openings and on the photoresist mold layer; and
removing the photoresist mold layer and the conductive layer on the photoresist mold layer.
19. The method of claim 10, further comprising:
forming at least one second planarization layer on the first planarization layer to cover the first electrode; and
forming a second electrode on the second planarization layer, the second electrode being connected to the first electrode through the second planarization layer.
20. The method of claim 19, further comprising, forming a protection layer on the second planarization layer to cover the second electrode.
US13/935,096 2012-12-12 2013-07-03 Field effect transistor and method of fabricating the same Abandoned US20140159050A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/633,984 US9634112B2 (en) 2012-12-12 2015-02-27 Field effect transistor and method of fabricating the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020120144126A KR101736277B1 (en) 2012-12-12 2012-12-12 Field Effect Transistor and Method of Fabricating the Same
KR10-2012-0144126 2012-12-12

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/633,984 Division US9634112B2 (en) 2012-12-12 2015-02-27 Field effect transistor and method of fabricating the same

Publications (1)

Publication Number Publication Date
US20140159050A1 true US20140159050A1 (en) 2014-06-12

Family

ID=50879983

Family Applications (2)

Application Number Title Priority Date Filing Date
US13/935,096 Abandoned US20140159050A1 (en) 2012-12-12 2013-07-03 Field effect transistor and method of fabricating the same
US14/633,984 Expired - Fee Related US9634112B2 (en) 2012-12-12 2015-02-27 Field effect transistor and method of fabricating the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US14/633,984 Expired - Fee Related US9634112B2 (en) 2012-12-12 2015-02-27 Field effect transistor and method of fabricating the same

Country Status (2)

Country Link
US (2) US20140159050A1 (en)
KR (1) KR101736277B1 (en)

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140291774A1 (en) * 2013-03-29 2014-10-02 Sumitomo Electric Device Innovations, Inc. Semiconductor device and method for manufacturing the same
US20140353673A1 (en) * 2013-05-30 2014-12-04 Transphorm Japan, Inc. Semiconductor apparatus
US20150263107A1 (en) * 2014-03-14 2015-09-17 Kabushiki Kaisha Toshiba Semiconductor device
US9306014B1 (en) * 2013-12-27 2016-04-05 Power Integrations, Inc. High-electron-mobility transistors
US9337332B2 (en) * 2012-04-25 2016-05-10 Hrl Laboratories, Llc III-Nitride insulating-gate transistors with passivation
JP2016119463A (en) * 2014-12-23 2016-06-30 パワー・インテグレーションズ・インコーポレーテッド High-electron-mobility transistor
US20160372557A1 (en) * 2015-06-18 2016-12-22 Delta Electronics, Inc. Semiconductor device
CN106328703A (en) * 2015-06-18 2017-01-11 台达电子工业股份有限公司 Semiconductor apparatus
US9559012B1 (en) 2013-09-30 2017-01-31 Hrl Laboratories, Llc Gallium nitride complementary transistors
US9812532B1 (en) 2015-08-28 2017-11-07 Hrl Laboratories, Llc III-nitride P-channel transistor
RU2668635C1 (en) * 2017-12-26 2018-10-02 Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский Томский государственный университет" (ТГУ, НИ ТГУ) Method for manufacturing a gallium nitride power field-effect transistor
US20190027593A1 (en) * 2017-07-20 2019-01-24 Delta Electronics, Inc. Enclosed gate runner for eliminating miller turn-on
US10276712B2 (en) 2014-05-29 2019-04-30 Hrl Laboratories, Llc III-nitride field-effect transistor with dual gates
CN109962101A (en) * 2019-04-23 2019-07-02 窦祥峰 A kind of structure of gallium nitride MISHEMT power device
CN110571144A (en) * 2019-07-25 2019-12-13 西安电子科技大学 manufacturing method of novel semiconductor grid
US10692984B2 (en) 2015-11-19 2020-06-23 Hrl Laboratories, Llc III-nitride field-effect transistor with dual gates
US10734508B2 (en) 2016-11-16 2020-08-04 Advantest Corporation Compound semiconductor device
US11114532B2 (en) * 2019-11-20 2021-09-07 Vanguard International Semiconductor Corporation Semiconductor structures and methods of forming the same
US20220190123A1 (en) * 2019-04-04 2022-06-16 Hrl Laboratories, Llc Miniature Field Plate T-Gate and Method of Fabricating the Same

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10002958B2 (en) * 2016-06-08 2018-06-19 The United States Of America, As Represented By The Secretary Of The Navy Diamond on III-nitride device
CN106206295B (en) * 2016-07-15 2019-04-09 中国科学院微电子研究所 GaN enhancement device preparation method and the GaN enhancement device of formation
CN111863950B (en) * 2020-07-28 2021-08-20 西安电子科技大学 Junction gate-drain power device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7064439B1 (en) * 1997-12-16 2006-06-20 Infineon Technologies Ag Integrated electrical circuit and method for fabricating it
JP2007242746A (en) * 2006-03-07 2007-09-20 Nippon Telegr & Teleph Corp <Ntt> Dual gate high-electron mobility transistor (hemt) structure semiconductor modulation element and method of manufacturing same
US20080087916A1 (en) * 2006-10-12 2008-04-17 Mitsubishi Electric Corporation Field-effect transistor and method of manufacturing the same
US20080277692A1 (en) * 2007-05-02 2008-11-13 Kabushiki Kaisha Toshiba Semiconductor device
US20100327322A1 (en) * 2009-06-25 2010-12-30 Kub Francis J Transistor with Enhanced Channel Charge Inducing Material Layer and Threshold Voltage Control
US20110057237A1 (en) * 2009-09-04 2011-03-10 Electronics And Telecommunications Research Institute Semiconductor devices and methods of forming thereof
US20110147762A1 (en) * 2003-03-03 2011-06-23 Sheppard Scott T Integrated Nitride and Silicon Carbide-Based Devices
US20110263102A1 (en) * 2008-07-31 2011-10-27 Sten Heikman Methods of Fabricating Normally-Off Semiconductor Devices

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6315475A (en) 1986-07-07 1988-01-22 Fujitsu Ltd Manufacture of field effect semiconductor device
JPS63193570A (en) 1987-02-06 1988-08-10 Sharp Corp Manufacture of semiconductor device
KR100307986B1 (en) * 1997-08-28 2002-05-09 가네꼬 히사시 Method of manufacturing semiconductor device
KR100262940B1 (en) * 1998-05-29 2000-09-01 이계철 Method for fabricating compound semiconductor device using lift-off of insulator

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7064439B1 (en) * 1997-12-16 2006-06-20 Infineon Technologies Ag Integrated electrical circuit and method for fabricating it
US20110147762A1 (en) * 2003-03-03 2011-06-23 Sheppard Scott T Integrated Nitride and Silicon Carbide-Based Devices
JP2007242746A (en) * 2006-03-07 2007-09-20 Nippon Telegr & Teleph Corp <Ntt> Dual gate high-electron mobility transistor (hemt) structure semiconductor modulation element and method of manufacturing same
US20080087916A1 (en) * 2006-10-12 2008-04-17 Mitsubishi Electric Corporation Field-effect transistor and method of manufacturing the same
US20080277692A1 (en) * 2007-05-02 2008-11-13 Kabushiki Kaisha Toshiba Semiconductor device
US20110263102A1 (en) * 2008-07-31 2011-10-27 Sten Heikman Methods of Fabricating Normally-Off Semiconductor Devices
US20100327322A1 (en) * 2009-06-25 2010-12-30 Kub Francis J Transistor with Enhanced Channel Charge Inducing Material Layer and Threshold Voltage Control
US20110057237A1 (en) * 2009-09-04 2011-03-10 Electronics And Telecommunications Research Institute Semiconductor devices and methods of forming thereof

Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9337332B2 (en) * 2012-04-25 2016-05-10 Hrl Laboratories, Llc III-Nitride insulating-gate transistors with passivation
US9484446B2 (en) 2013-03-29 2016-11-01 Sumitomo Electric Device Innovations, Inc. Semiconductor device and method for manufacturing the same
US9123792B2 (en) * 2013-03-29 2015-09-01 Sumitomo Electric Device Innovations, Inc. Semiconductor device and method for manufacturing the same
US20140291774A1 (en) * 2013-03-29 2014-10-02 Sumitomo Electric Device Innovations, Inc. Semiconductor device and method for manufacturing the same
US20140353673A1 (en) * 2013-05-30 2014-12-04 Transphorm Japan, Inc. Semiconductor apparatus
US9349805B2 (en) * 2013-05-30 2016-05-24 Transphorm Japan, Inc. III-n device with dual gates and field plate
US9559012B1 (en) 2013-09-30 2017-01-31 Hrl Laboratories, Llc Gallium nitride complementary transistors
US9306014B1 (en) * 2013-12-27 2016-04-05 Power Integrations, Inc. High-electron-mobility transistors
US9525055B2 (en) 2013-12-27 2016-12-20 Power Integrations. Inc. High-electron-mobility transistors
TWI692103B (en) * 2013-12-27 2020-04-21 美商電源整合公司 High electron-mobility transistor and semiconductor device
US20150263107A1 (en) * 2014-03-14 2015-09-17 Kabushiki Kaisha Toshiba Semiconductor device
US9318565B2 (en) * 2014-03-14 2016-04-19 Kabushiki Kaisha Toshiba Power semiconductor device with dual field plate arrangement and method of making
US10276712B2 (en) 2014-05-29 2019-04-30 Hrl Laboratories, Llc III-nitride field-effect transistor with dual gates
JP2016119463A (en) * 2014-12-23 2016-06-30 パワー・インテグレーションズ・インコーポレーテッド High-electron-mobility transistor
US9793390B2 (en) * 2015-06-18 2017-10-17 Delta Electronics, Inc. Low miller factor semiconductor device
US20160372557A1 (en) * 2015-06-18 2016-12-22 Delta Electronics, Inc. Semiconductor device
CN106328703A (en) * 2015-06-18 2017-01-11 台达电子工业股份有限公司 Semiconductor apparatus
US9812532B1 (en) 2015-08-28 2017-11-07 Hrl Laboratories, Llc III-nitride P-channel transistor
US10692984B2 (en) 2015-11-19 2020-06-23 Hrl Laboratories, Llc III-nitride field-effect transistor with dual gates
TWI719255B (en) * 2016-11-16 2021-02-21 日商愛德萬測試股份有限公司 Compound semiconductor device and manufacturing method thereof
US10734508B2 (en) 2016-11-16 2020-08-04 Advantest Corporation Compound semiconductor device
US10680090B2 (en) * 2017-07-20 2020-06-09 Delta Electronics, Inc. Enclosed gate runner for eliminating miller turn-on
CN109285830A (en) * 2017-07-20 2019-01-29 台达电子工业股份有限公司 Semiconductor structure
US20190027593A1 (en) * 2017-07-20 2019-01-24 Delta Electronics, Inc. Enclosed gate runner for eliminating miller turn-on
US11127845B2 (en) 2017-07-20 2021-09-21 Delta Electronics, Inc. Enclosed gate runner for eliminating miller turn-on
RU2668635C1 (en) * 2017-12-26 2018-10-02 Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский Томский государственный университет" (ТГУ, НИ ТГУ) Method for manufacturing a gallium nitride power field-effect transistor
US20220190123A1 (en) * 2019-04-04 2022-06-16 Hrl Laboratories, Llc Miniature Field Plate T-Gate and Method of Fabricating the Same
US11764271B2 (en) * 2019-04-04 2023-09-19 Hrl Laboratories, Llc Miniature field plate T-gate and method of fabricating the same
CN109962101A (en) * 2019-04-23 2019-07-02 窦祥峰 A kind of structure of gallium nitride MISHEMT power device
CN110571144A (en) * 2019-07-25 2019-12-13 西安电子科技大学 manufacturing method of novel semiconductor grid
US11114532B2 (en) * 2019-11-20 2021-09-07 Vanguard International Semiconductor Corporation Semiconductor structures and methods of forming the same

Also Published As

Publication number Publication date
US20150171188A1 (en) 2015-06-18
KR20140080574A (en) 2014-07-01
US9634112B2 (en) 2017-04-25
KR101736277B1 (en) 2017-05-17

Similar Documents

Publication Publication Date Title
US9634112B2 (en) Field effect transistor and method of fabricating the same
US11075271B2 (en) Stepped field plates with proximity to conduction channel and related fabrication methods
EP2763179B1 (en) High Electron Mobility Transistor (HEMT)
US8283699B2 (en) GaN based HEMTs with buried field plates
JP4077731B2 (en) Compound semiconductor device and manufacturing method thereof
US7592211B2 (en) Methods of fabricating transistors including supported gate electrodes
US8004022B2 (en) Field effect transistor
JP5866766B2 (en) Compound semiconductor device and manufacturing method thereof
WO2006080109A1 (en) Semiconductor device provided with mis structure and method for manufacturing the same
US20130099285A1 (en) High electron mobility transistor having reduced threshold voltage variation and method of manufacturing the same
US10679860B2 (en) Self-aligning source, drain and gate process for III-V nitride MISHEMTs
EP2747143A1 (en) GaN HEMTs and GaN diodes
WO2017000906A1 (en) Enhancement-mode double-channel high electron mobility transistor
JP6834546B2 (en) Semiconductor devices and their manufacturing methods
US10734498B1 (en) Method of making a dual-gate HEMT
US11594625B2 (en) III-N transistor structures with stepped cap layers
RU2671312C2 (en) High-frequency field transistor with the additional field electrode manufacturing method
US10985253B2 (en) Semiconductor devices with multiple channels and three-dimensional electrodes
US8901608B2 (en) Transistor and method of fabricating the same
US8558242B2 (en) Vertical GaN-based metal insulator semiconductor FET
CN114078965A (en) High electron mobility transistor and manufacturing method thereof
US20110062448A1 (en) Field effect semiconductor devices and methods of manufacturing field effect semiconductor devices
JP2010245240A (en) Heterojunction field-effect semiconductor device and method of manufacturing the same
US8952422B2 (en) Transistor and method of fabricating the same
JP5768340B2 (en) Compound semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTIT

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YOON, HYUNG SUP;MIN, BYOUNG-GUE;LIM, JONG-WON;AND OTHERS;SIGNING DATES FROM 20130514 TO 20130520;REEL/FRAME:030738/0223

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION