US20140048888A1 - Strained Structure of a Semiconductor Device - Google Patents

Strained Structure of a Semiconductor Device Download PDF

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Publication number
US20140048888A1
US20140048888A1 US13/588,860 US201213588860A US2014048888A1 US 20140048888 A1 US20140048888 A1 US 20140048888A1 US 201213588860 A US201213588860 A US 201213588860A US 2014048888 A1 US2014048888 A1 US 2014048888A1
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Prior art keywords
silicide
region
strained
semiconductor device
substrate
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US13/588,860
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English (en)
Inventor
Chung-Hsien Chen
Ting-Chu Ko
Chih-Hao Chang
Chih-Sheng Chang
Shou-Zen Chang
Clement Hsingjen Wann
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to US13/588,860 priority Critical patent/US20140048888A1/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHANG, CHIH-HAO, CHANG, CHIH-SHENG, CHANG, SHOU-ZEN, CHEN, CHUNG-HSIEN, KO, TING-CHU, WANN, CLEMENT HSINGJEN
Priority to KR1020120153341A priority patent/KR101573108B1/ko
Priority to TW102126603A priority patent/TWI524396B/zh
Priority to US14/166,585 priority patent/US9236253B2/en
Publication of US20140048888A1 publication Critical patent/US20140048888A1/en
Abandoned legal-status Critical Current

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Definitions

  • the disclosure relates to integrated circuit fabrication, and more particularly to a semiconductor device with a strained structure.
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • a high-k gate dielectric layer and metal gate electrode layer are incorporated into the gate stack of the MOSFET to improve device performance with the decreased feature sizes.
  • strained structures in source and drain (S/D) recess cavities of the MOSFET utilizing selectively grown silicon germanium (SiGe) may be used to enhance carrier mobility.
  • CMOS complementary metal-oxide-semiconductor
  • FET field-effect transistor
  • FIG. 1 is a flowchart illustrating a method of fabricating a strained structure of a semiconductor device according to various aspects of the present disclosure
  • FIGS. 2-12 show schematic cross-sectional views of a semiconductor device comprising a strained structure at various stages of fabrication according to various aspects of the present disclosure.
  • first and second features are formed in direct contact
  • additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
  • Various features may be arbitrarily drawn in different scales for simplicity and clarity.
  • present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
  • the method 100 begins with step 102 in which a substrate comprising a major surface is provided.
  • the method 100 continues with step 104 in which a cavity is formed below the major surface.
  • the method 100 continues with step 106 in which a strained material is epi-grown in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate.
  • the method 100 continues with step 108 in which a first metal layer is formed over the strained material.
  • the method 100 continues with step 110 in which the first metal layer and the strained material are heated to form a first silicide region.
  • the method 100 continues with step 112 in which an interlayer dielectric (ILD) layer is formed over the first silicide region and extending over the substrate.
  • the method 100 continues with step 114 in which an opening is formed in the ILD layer, wherein the opening is on the first silicide region (i.e. the opening at least partially exposes the first silicide region).
  • the method 100 continues with step 116 in which a second metal layer is formed on the first silicide region in the opening.
  • the method 100 continues with step 118 in which the second metal layer and the strained material are heated to form a second silicide region lower than the first silicide region.
  • the discussion that follows illustrates embodiments of semiconductor devices that can be fabricated according to the method 100 of FIG. 1 .
  • FIGS. 2-12 show schematic cross-sectional views of a semiconductor device 200 comprising a strained structure 250 (see FIG. 12 ) at various stages of fabrication according to various aspects of the present disclosure.
  • the term semiconductor device 200 refers to a planar field effect transistor (FET).
  • the term semiconductor device 200 refers to a fin field effect transistor (FinFET).
  • the FinFET refers to any fin-based, multi-gate transistor.
  • Other transistor structures and analogous structures are within the contemplated scope of this disclosure.
  • the semiconductor device 200 may be included in a microprocessor, memory cell, and/or other integrated circuit (IC). It is noted that the method of FIG. 1 does not produce a completed semiconductor device 200 .
  • Completed semiconductor device 200 may be fabricated using complementary metal-oxide-semiconductor (CMOS) technology processing. Accordingly, it is understood that additional processes may be provided before, during, and after the method 100 of FIG. 1 , and that some other processes may only be briefly described herein. Also, FIGS. 2 through 12 are simplified for a better understanding of the concepts of the present disclosure. For example, although only the semiconductor device 200 is depicted in FIGS. 2-12 , it is understood the IC may comprise a number of other devices comprising resistors, capacitors, inductors, fuses, etc.
  • CMOS complementary metal-oxide-semiconductor
  • the substrate 202 may comprise a silicon substrate.
  • the substrate 202 may alternatively comprise silicon germanium, gallium arsenic, or other suitable semiconductor materials.
  • the substrate 202 may further comprise other features such as various doped regions, a buried layer, and/or an epitaxy layer.
  • the substrate 202 may be a semiconductor on insulator such as silicon on insulator (SOI).
  • SOI silicon on insulator
  • the semiconductor substrate 202 may comprise a doped epi layer, a gradient semiconductor layer, and/or may further include a semiconductor layer overlying another semiconductor layer of a different type such as a silicon layer on a silicon germanium layer.
  • a compound semiconductor substrate may comprise a multilayer silicon structure or a silicon substrate may include a multilayer compound semiconductor structure.
  • the substrate 202 comprises a major surface 202 s.
  • the semiconductor substrate 202 comprises a P-active region 204 p and an N-active region 204 n separated by an isolation region 206 .
  • the active regions 204 p , 204 n may include various doping configurations depending on design requirements.
  • the P-active region 204 p is doped with n-type dopants, such as phosphorus or arsenic;
  • the N-active region 204 n is doped with p-type dopants, such as boron or BF 2 .
  • the P-active region 204 p may be usable for forming a p-type Field Effect Transistor (pFET) 200 p
  • the N-active region 204 n may be usable for forming an n-type Field Effect Transistor (nFET) 200 n
  • the semiconductor device 200 comprises both the pFET 200 p and the nFET 200 n.
  • Isolation regions 206 may be formed on the substrate 202 to isolate the various active regions 204 p , 204 n from each other.
  • the isolation regions 206 may utilize isolation technology, such as local oxidation of silicon (LOCOS) or shallow trench isolation (STI), to define and electrically isolate the various active regions 204 p , 204 n .
  • the isolation regions 206 comprise an STI.
  • the isolation regions 206 may comprise materials such as silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-k dielectric material, and/or combinations thereof.
  • the isolation regions 206 and in the present embodiment, the STI, may be formed by any suitable process.
  • the formation of the STI may include patterning the semiconductor substrate 202 by a photolithography process, etching a trench in the substrate 202 (for example, by using a dry etching, wet etching, and/or plasma etching process), and filling the trench (for example, by using a chemical vapor deposition process) with a dielectric material.
  • the filled trench may have a multi-layer structure such as a thermal oxide liner layer filled with silicon nitride or silicon oxide.
  • the gate dielectric layer 212 and gate electrode layer 214 are sequentially deposited over the substrate 202 .
  • the gate dielectric layer 212 may include silicon oxide, silicon nitride, silicon oxy-nitride, or high-k dielectric.
  • High-k dielectrics comprise metal oxides. Examples of metal oxides used for high-k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and mixtures thereof.
  • the gate dielectric layer 212 is a high-k dielectric layer with a thickness in the range of about 10 to 30 angstroms.
  • the gate dielectric layer 212 may be formed using a suitable process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation, UV-ozone oxidation, or combinations thereof.
  • the gate dielectric layer 212 may further comprise an interfacial layer (not shown) to reduce damage between the gate dielectric layer 212 and the substrate 202 .
  • the interfacial layer may comprise silicon oxide.
  • the gate electrode layer 214 may comprise a single layer or multilayer structure. In the present embodiment, the gate electrode layer 214 may comprise poly-silicon. Further, the gate electrode layer 214 may be doped poly-silicon with uniform or non-uniform doping. In some embodiments, the gate electrode layer 214 may include an N-work-function metal for the N-gate stack 210 n .
  • the N-work-function metal comprises Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr. In some embodiments, the gate electrode layer 214 may include a P-work-function metal for the P-gate stack 210 p .
  • the P-work-function metal comprises TiN, WN, TaN, and Ru.
  • the gate electrode layer 214 comprises a thickness in the range of about 30 nm to about 60 nm.
  • the gate electrode layer 214 may be formed using a suitable process such as ALD, CVD, PVD, plating, or combinations thereof.
  • a layer of photoresist (not shown) is formed over the gate electrode layer 214 by a suitable process, such as spin-on coating, and patterned to form a patterned photoresist feature by a proper lithography patterning method.
  • a width of the patterned photoresist feature is in the range of about 5 to 45 nm.
  • the patterned photoresist feature can then be transferred using a dry etching process to the underlying layers (i.e., the gate electrode layer 214 and the gate dielectric layer 212 ) to form the P-gate stack 210 p and the N-gate stacks 210 n .
  • the photoresist layer may be stripped thereafter.
  • a hard mask layer 216 is formed over the gate electrode layer 214 ; a patterned photoresist layer (not shown) is formed on the hard mask layer 216 ; and the pattern of the photoresist layer is transferred to the hard mask layer 216 and then transferred to the gate electrode layer 214 and the gate dielectric layer 212 to form the P-gate stack 210 p and the N-gate stack 210 n .
  • the hard mask layer 216 comprises silicon oxide.
  • the hard mask layer 216 may comprise silicon nitride, silicon oxynitride, and/or other suitable dielectric materials, and may be formed using a method such as CVD or PVD.
  • the hard mask layer 216 has a thickness in the range from about 100 to 800 angstroms. The photoresist layer may be stripped thereafter.
  • the semiconductor device 200 further comprises a pair of sidewall spacers 218 p on two sides of the P-gate stack 210 p and a pair of sidewall spacers 218 n on two sides of the N-gate stack 210 n .
  • the sidewall spacers 218 p , 218 n are formed by first forming a dielectric layer formed over the P-gate stack 210 p , the N-gate stacks 210 n , and the substrate 202 and covering sidewalls of the P-gate stack 210 p and sidewalls of the N-gate stack 210 n .
  • the dielectric layer may include silicon oxide, silicon nitride, silicon oxy-nitride, or other suitable material.
  • the dielectric layer may comprise a single layer or multilayer structure.
  • the dielectric layer may be formed by CVD, PVD, ALD, or other suitable technique.
  • the dielectric layer has a thickness ranging from about 5 to 15 nm. Then, an anisotropic etching is performed on the dielectric layer to form the pair of sidewall spacers 218 p on two sides of the P-gate stack 210 p and the pair of sidewall spacers 218 n on two sides of the N-gate stack 210 n.
  • the process steps up to this point have provided the substrate 202 having the P-gate stack 210 p over channel portion of the P-active region 204 p and the N-gate stack 210 n over channel portion of the N-active region 204 n .
  • portions of the N-active region (other than where the N-gate stack 210 n and the pair of sidewall spacers 218 n are formed thereover) are recessed to form N-source and drain (S/D) cavities in the N-active region 204 n .
  • S/D N-source and drain
  • an N-strained material is epi-grown in the N-S/D cavities to form N-S/D regions to strain or stress the channel region of the nFET 200 n to enhance carrier mobility of the nFET 200 n .
  • portions of the P-active region 204 p are recessed to form P-source and drain (S/D) cavities in the P-active region 204 p .
  • P-source and drain (S/D) cavities are recessed to form P-source and drain (S/D) cavities in the P-active region 204 p .
  • a P-strained material is epi-grown in the P-SD cavities to form P-S/D regions to strain or stress the channel region of the pFET 200 p to enhance carrier mobility of the pFET 200 p .
  • the strained material i.e., the N-strained material or P-strained material
  • the processing discussed below with reference to FIGS. 3-12 may fabricate a strained structure in the S/D regions of the semiconductor device, thereby delivering a given amount of strain into channel region of the semiconductor device. Problems associated with insufficient on-current of a semiconductor device may be avoided, thereby enhancing the device performance.
  • the structure in FIG. 3 is produced by recessing portions of the N-active region 204 n (other than where the N-gate stack 210 n and the pair of sidewall spacers 218 n are formed thereover) to form N-source and drain (S/D) cavities 208 n in the N-active region 204 n (step 104 in FIG. 1 ).
  • S/D N-source and drain cavities 208 n in the N-active region 204 n (step 104 in FIG. 1 ).
  • Each of the N-S/D cavities 208 n is below the major surface 202 s and adjacent to one side of the N-gate stack 210 n.
  • a dummy dielectric layer comprising a material such as silicon oxide is formed over the substrate 202 by a CVD process, and patterned to form a dummy dielectric feature 220 p by proper lithography and etch methods.
  • the dummy dielectric feature 220 p covers the P-active region 204 p and exposes portions of the N-active region 204 n (other than where the N-gate stack 210 n and the pair of sidewall spacers 218 n are formed thereover).
  • a biased etching process is performed to recess the major surface 208 s of the substrate 202 that are unprotected or exposed to form the N-S/D cavities 208 n in the N-active region 204 n .
  • the etching process may be performed using a chemical selected from NF 3 , CF 4 , and SF 6 as an etching gas.
  • the etching process may be performed using a solution comprising NH 4 OH and H 2 O 2 .
  • the structure in FIG. 4 is produced by epi-growing an N-strained material 222 n in the N-S/D cavities 208 n , wherein a lattice constant of the N-strained material 222 n is different from a lattice constant of the substrate 202 .
  • a top surface 222 a of the N-strained material 222 n is coplanar with the major surface 202 s , although it may be higher or lower than the major surface 202 s .
  • the N-strained material 222 n comprises SiCP or SiP.
  • a pre-cleaning process may be performed to clean the N-S/D cavities 208 n with HF or other suitable solution.
  • the N-strained material 222 n such as SiCP is selectively grown by an LPCVD process to fill the N-SD cavities 208 n .
  • the LPCVD process is performed at a temperature of about 400 to 800° C. and under a pressure of about 1 to 15 Torr, using SiH 4 , CH 4 , and H 2 as reaction gases. Then the dummy dielectric feature 220 p is removed using HF solution.
  • portions of the P-active region 204 p are recessed to form P-source and drain (S/D) cavities 208 p in the P-active region 204 p .
  • S/D cavities 208 p is below the major surface 202 s and adjacent to one side of the P-gate stack 210 p .
  • a dummy dielectric layer such as silicon oxide is formed over the substrate 202 by a CVD process, and patterned to form a dummy dielectric feature 220 n by proper lithography and etch methods.
  • the dummy dielectric feature 220 n covers the N-active region 204 n and exposes portions of the P-active region 204 p (other than where the P-gate stack 210 p and the pair of sidewall spacers 218 p are formed thereover).
  • a biased etching process is performed to recess the major surface 202 s of the substrate 202 that are unprotected or exposed to form the P-S/D cavities 208 p .
  • the etching process may be performed using a chemical selected from NF 3 , CF 4 , and SF 6 as an etching gas.
  • the etching process may be performed using a solution comprising NH 4 OH and/or H 2 O 2 .
  • the structure in FIG. 6 is produced by epi-growing a P-strained material 222 p in the P-S/D cavities 208 p , wherein a lattice constant of the P-strained material 222 p is different from a lattice constant of the substrate 202 .
  • a top surface 222 b of the P-strained material 222 p is higher than the major surface 202 s .
  • the P-strained material 222 p comprises SiGe or SiGeB.
  • a pre-cleaning process may be performed to clean the P-S/D cavities 208 p with HF or other suitable solution.
  • the P-strained material 222 p such as silicon germanium (SiGe) is selectively grown by an LPCVD process to fill the P-S/D cavities 208 p .
  • the LPCVD process is performed at a temperature of about 660 to 700° C. and under a pressure of about 13 to 50 Torr, using SiH 2 Cl 2 , HCl, GeH 4 , B 2 H 6 , and H 2 as reaction gases. Then the dummy dielectric feature 220 n is removed using HF solution.
  • a first metal layer 224 is formed over the strained materials 222 to a thickness of between about 15 and 60 angstroms.
  • the first metal layer 224 comprises titanium, cobalt, nickel, platinum, erbium, or palladium.
  • the first metal layer 224 may be formed by CVD, PVD, plating, ALD, or other suitable technique.
  • the structure depicted in FIG. 8 is produced by heating the first metal layer 224 and the strained materials 222 to form first silicide regions 226 (step 110 in FIG. 1 ).
  • the first metal layer 224 in contact with the strained materials 222 is then transformed into the first silicide regions 226 by a thermal process, such as a rapid thermal anneal (RTA) process.
  • RTA rapid thermal anneal
  • the first silicide regions 226 comprise first N-silicide regions 226 n and first P-silicide regions 226 p .
  • the first silicide regions 226 comprise titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, palladium silicide, and combinations thereof.
  • a first RTA process is applied to heat the substrate 202 at a temperature of about 230° C. to 260° C.
  • the first metal layer 224 in contact with the strained materials 222 will form a high-resistance silicide.
  • the remaining un-reacted first metal layer 224 is removed using, for example, a solution comprising NH 4 OH, H 2 O 2 , and deionized water.
  • a second RTA process is applied to heat the substrate 202 at a temperature of about 650° C. to 750° C., thereby forming the first silicide regions 226 .
  • the structure in FIG. 9 is produced by forming an interlayer dielectric (ILD) layer 228 over the first silicide regions 226 and extending over the substrate 202 .
  • the ILD layer 228 may comprise a dielectric material.
  • the dielectric material may comprise silicon oxide, silicon nitride, silicon oxynitride, or a low-k material. It is understood that the ILD layer 228 may comprise one or more dielectric materials and/or one or more dielectric layers.
  • the ILD layer 228 may be deposited over the first silicide region 226 to a suitable thickness by CVD, high density plasma (HDP) CVD, sub-atmospheric CVD (SACVD), spin-on, sputtering, or other suitable methods.
  • the ILD layer 228 has a thickness of about 3000 to 4500 ⁇ . Then, the ILD layer 228 is planarized using a chemical mechanical polishing (CMP) process until a top surface of the hard mask (i.e., the sidewall spacer) 218 is exposed or reached.
  • CMP chemical mechanical polishing
  • CMOS processing steps applied to the semiconductor device 200 of FIG. 9 comprise forming openings 230 in the ILD layer 228 , wherein the openings 230 are on the first silicide regions 226 (step 114 in FIG. 1 ).
  • the openings 230 may be formed by any suitable process.
  • the formation of the openings 230 may comprise patterning the ILD layer 228 by a conventional photolithography process, and etching the exposed ILD layer 228 (for example, by using a dry etching, wet etching, and/or plasma etching process) to remove portions of the ILD layer 228 over portions of the first silicide regions 226 to expose top portions of the first silicide regions 226 .
  • a second metal layer 234 is formed on the first silicide regions 226 in the openings 230 to a thickness of between about 15 and 60 angstroms.
  • the second metal layer 234 comprises titanium, cobalt, nickel, platinum, erbium, and palladium.
  • the second metal layer 234 may be formed by CVD, PVD, plating, ALD, or other suitable technique.
  • second metal layer 234 is shown as over-filling openings 230 , it is not necessary that second metal layer 234 over-fill the trench or even completely fill the trench, because excess portions of second metal layer 234 are subsequently removed, as described more fully below.
  • the structure depicted in FIG. 12 is produced by heating the second metal layer 234 and the strained materials 222 to form second silicide regions 236 lower than the first silicide regions 226 (step 118 in FIG. 1 ).
  • the second metal layer 234 will penetrate through the first silicide regions 226 to meet the remaining strained material 222 , and then will be transformed into the second silicide regions 236 by a thermal process, such as a rapid thermal anneal (RTA) process.
  • RTA rapid thermal anneal
  • the second silicide regions 236 comprise second N-silicide regions 236 n and second P-silicide regions 236 p .
  • the second silicide regions 236 comprise titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, and palladium silicide.
  • a third RTA process is applied to heat the substrate 202 at a temperature of about 230° C. to 260° C.
  • the second metal layer 234 meeting the strained material 222 will form a high-resistance silicide.
  • the remaining un-reacted second metal layer 234 is removed using, for example, a solution comprising NH 4 OH, H 2 O 2 , and deionized water.
  • a fourth RTA process is applied to heat the substrate 202 at a temperature of about 650° C. to 750° C., thereby forming the second silicide regions 236 .
  • the second N-silicide regions 236 n are on the remaining N-strained material 222 n (referred to as N-strained regions 238 n hereafter), while the second P-silicide regions 236 p are on the remaining P-strained material 222 p (referred to as P-strained regions 238 p hereafter).
  • the P-strained region 238 p has a first top surface 238 q higher than the major surface 202 s . In some embodiments, a distance H 1 between the first top surface 238 q and the major surface 202 s is in the range of about 5 to 15 nm.
  • the N-strained region 238 n has a second top surface 238 m lower than the major surface 202 s . In some embodiments, a distance H 2 between the second top surface 238 m and the major surface 202 s is in the range of about 10 to 25 nm.
  • the N-silicide regions 240 n are on the N-strained region 238 n . Further, the N-silicide regions 240 n are used to strain or stress the channel region of the nFET 200 n to enhance carrier mobility of the nFET 200 n.
  • the first P-silicide regions 226 p and the second P-silicide regions 236 p are combined and referred to as P-silicide regions 240 p .
  • a volume of the P-silicide regions 240 p is a summation of a volume of the first P-silicide regions 226 p and a volume of the second P-silicide regions 236 p , which is greater than each of the volume of the first P-silicide regions 226 p and the volume of the second P-silicide regions 236 p .
  • a maximum thickness t 1 of the P-silicide region 240 p is in the range of about 10 to 25 nm.
  • the P-silicide regions 240 p (with similar stress as the N-silicide regions 240 n ) will degrade carrier mobility of the pFET 200 p if the P-silicide regions 240 p strain or stress the channel region of the pFET 200 p .
  • the P-silicide regions 240 p are on the P-strained regions 238 p .
  • the P-silicide regions 240 p is used to strain or stress the P-gate stack 210 p to enhance work-function of the P-gate stack 210 p .
  • the P-silicide regions 240 p are adjacent to the P-gate stack 210 p , but far from the channel region of the pFET 200 p.
  • the P-silicide regions 240 p and P-strained regions 238 p are combined and referred to as a P-strained structure 250 p .
  • the N-silicide regions 240 n and N-strained regions 238 n are combined and referred to as an N-strained structure 250 n .
  • the P-strained structure 250 p and N-strained structure 250 n are combined and referred to as a strained structure 250 .
  • Applicant's method may fabricate large-volume N-silicide regions 240 n in the S/D regions of the nFET 200 n of the semiconductor device 200 , thereby delivering a given amount of strain into channel region of the semiconductor device 200 . Further, Applicant's method may fabricate large-volume P-silicide regions 240 p in the S/D regions of the pFET 200 p of the semiconductor device 200 , thereby delivering a given amount of strain into P-gate stack 210 p of the semiconductor device 200 . Problems associated with insufficient on-current of the semiconductor device 200 may be avoided, thereby enhancing the device performance.
  • the semiconductor device 200 may undergo further CMOS processes to form various features such as contacts/vias, interconnect metal layers, dielectric layers, passivation layers, etc.
  • a semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and a P-silicide region on the P-strained region; and an n-type Field Effect Transistor (nFET) comprising: an N-gate stack over the major surface, an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and a N-silicide region on the N-strained region.
  • pFET p-type Field Effect Transist
  • a method for fabricating a semiconductor device comprises providing a substrate comprising a major surface; forming a cavity below the major surface; epi-growing a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; forming a first metal layer over the strained material; heating the first metal layer and the strained material to form a first silicide region; forming an interlayer dielectric (ILD) layer over the first silicide region and extending over the substrate; forming an opening in the ILD layer, wherein the opening is on the first silicide region; forming a second metal layer on the first silicide region in the opening; and heating the second metal layer and the strained material to form a second silicide region lower than the first silicide region.
  • ILD interlayer dielectric
US13/588,860 2012-08-17 2012-08-17 Strained Structure of a Semiconductor Device Abandoned US20140048888A1 (en)

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US20140147978A1 (en) 2014-05-29
KR101573108B1 (ko) 2015-11-30
KR20140023200A (ko) 2014-02-26
TWI524396B (zh) 2016-03-01

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