US20130312901A1 - Printed circuit board and manufacturing method thereof - Google Patents
Printed circuit board and manufacturing method thereof Download PDFInfo
- Publication number
- US20130312901A1 US20130312901A1 US13/953,650 US201313953650A US2013312901A1 US 20130312901 A1 US20130312901 A1 US 20130312901A1 US 201313953650 A US201313953650 A US 201313953650A US 2013312901 A1 US2013312901 A1 US 2013312901A1
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- United States
- Prior art keywords
- primer resin
- resin layer
- insulating layer
- via hole
- carrier
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/428—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
- H05K3/4658—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern characterized by laminating a prefabricated metal foil pattern, e.g. by transfer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
- H05K2203/054—Continuous temporary metal layer over resist, e.g. for selective electroplating
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0571—Dual purpose resist, e.g. etch resist used as solder resist, solder resist used as plating resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0574—Stacked resist layers used for different processes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
Definitions
- the present invention relates to a printed circuit board and a manufacturing method thereof.
- circuit patterns are formed on the surface of an insulating layer.
- a technique of burying circuit patterns in the insulating layer has been introduced. According to the technique, a carrier is prepared, and a circuit pattern is formed over the carrier. And then, the circuit pattern is transferred to an insulating resin.
- a metal barrier is interposed between the carrier and the circuit pattern, there is a limit to simplification of manufacturing processes because the metal barrier has to be etched while the circuit pattern is transferred to the insulating resin.
- a portion of the metal barrier has to be opened, before the hole is processed. In that case, an interlayer accuracy may be deteriorated due to the process of opening a portion of the metal barrier.
- An aspect of the present invention provides a method of manufacturing a printed circuit board, which can include: preparing a carrier including a primer resin layer formed thereon; forming a circuit pattern on the primer resin layer; stacking the carrier onto an insulating layer such that the circuit pattern is buried in the insulating layer; removing the carrier; forming a via hole in the insulating layer on which the primer resin layer is stacked; and forming a conductive via in the via hole.
- the conductive via can be formed by forming a plating layer in the via hole and on the primer resin layer and removing a portion of the plating layer formed over the primer resin layer.
- the carrier can be made of metal, and the via hole can be a blind via hole (BVH).
- BVH blind via hole
- the via hole can be formed by performing a laser processing from a direction of the primer resin layer.
- the printed circuit board can include: an insulating layer including circuit patterns buried in both sides of the insulating layer; a via electrically connecting the both sides of the insulating layer; a primer resin layer stacked over one side of the insulating layer; and a solder-resist layer covering the primer resin layer.
- the via hole can be a blind via hole (BVH).
- BVH blind via hole
- FIG. 1 is a flowchart illustrating a method of manufacturing a printed circuit board according to an embodiment of the invention.
- FIGS. 2 to 14 illustrate processes for a method of manufacturing a printed circuit board according to an embodiment of the invention.
- FIG. 15 illustrates a process that two carriers are compressed on upper and lower sides of the insulating layer, respectively.
- FIG. 1 is a flowchart illustrating a method of manufacturing a printed circuit board according to an embodiment of the invention
- FIGS. 2 to 14 illustrate processes for a method of manufacturing a printed circuit board according to an embodiment of the invention. Illustrated in FIGS. 2 to 14 are a supporting member 10 , a carrier 20 , a primer resin layer 30 , a metal foil 40 , a plating resist 42 , circuit patterns 44 , 62 , an insulating layer 50 , a via hole 52 , plated metal 56 , a conductive via 58 and an inner substrate 60 .
- a carrier 20 including a primer resin layer 30 is prepared (S 110 ), and a circuit pattern 44 is formed on the primer resin layer 30 (S 120 ).
- a structure includes, in the successive order of, carriers 20 , primer resin layers 30 and metal foils 40 on both sides of a supporting member 10 .
- the supporting member 10 may be made of, for example, a thermoplastic material whose adhesion can be reduced when the supporting member 10 is heated.
- the carriers 20 stacked on both sides of the supporting member 10 are to be separated from the supporting member 10 later.
- the metal foil 40 may be made of copper or other conductive metal.
- a patterned plating resist 42 is formed over the metal foil 40 , and a circuit pattern 44 is formed by an electro-plating process.
- the metal foil 40 formed over the primer resin layer 30 can serve as a seed layer, the electro-plating process for forming the circuit pattern 44 can be carried out.
- the plating resist 42 is removed, and a circuit pattern 44 is formed on the metal foil 40 such that the circuit pattern 44 has a protruding shape.
- the carriers 20 stacked on the supporting member 10 are separated from the supporting member 10 .
- a surface-treatment process may be carried out on the circuit pattern 44 such that enough adhesion between the circuit pattern 44 and the insulating layer 50 can be ensured.
- the surface-treatment process is carried out by flash etching etc., a roughness may be formed on the surface of the circuit pattern 44 and the adhesion between the circuit pattern 44 and the insulating layer 50 can be increased.
- the exposed portions of the metal foil 40 on the primer resin layer 30 may be removed.
- the carrier 20 is stacked onto an insulating layer 50 and the circuit pattern 44 is buried in the insulating layer 50 (S 130 ). Since the primer resin layer 30 and circuit pattern 44 are formed on the surface of the carrier 20 , the circuit pattern 44 can be buried in the insulating layer 50 when the carrier 20 is stacked on the insulating layer 50 .
- the insulating layer 50 may be in B-stage, that is, semi-hardened. In that case, the circuit pattern 44 may be buried in the insulating layer 50 easily. And then, the solid bonding strength between the circuit pattern 44 and the insulating layer 50 may be obtained when the insulating layer 50 is hardened.
- an inner substrate 62 may be stacked on the lower surface of the insulating layer 50 .
- a circuit pattern 62 may be formed on the surface of the inner substrate 62 , and buried in the insulating layer 50 by stacking each other.
- two carriers 20 separated from the supporting member 10 may be compressed on upper and lower sides of the insulating layer 50 , respectively, as shown in FIG. 15 .
- circuit patterns 44 may be buried in both sides of the insulating layer 50 at the same time in one process.
- the carrier 20 is removed (S 140 ).
- the carrier 20 may be removed by a wet-etching process with etchant. In that case, since the upper surface of the circuit pattern 44 buried in the insulating layer 50 is covered by the primer resin layer 30 , the circuit pattern 44 may not be damaged by the etchant used for removing the carrier 20 .
- a via hole 52 is processed (S 150 ).
- a laser may be used for processing the via hole 52 .
- the via hole 52 may be processed directly without processing a window.
- a depth of the via bole 52 may be controlled easily.
- a seed layer 54 is formed on the primer resin layer 30 and inner wall of the via hole 52 .
- an electroless plating process may be carried out.
- plated metal 52 is filled in the via hole 52 by an electro-plating process, as shown in FIG. 11 .
- the plated metal 52 filled in the via hole 52 can serve as a conductive via 58 for interlayer connection.
- the plated metal 52 may be copper (Cu) or whatever is suitable for transmitting electric signals.
- a portion of the plated metal 52 formed over the primer resin layer 30 is removed.
- a wet-etching process with an etchant may be carried out.
- the primer resin layer 30 formed on the surface of the insulating layer 50 can serve as an etch-stop barrier.
- solder resist layer 70 is formed by dispensing solder resist ink while the primer resin layer 30 remains.
- a printed circuit board manufactured by the processes set forth above is illustrated in FIG. 14 .
- a printed circuit board according to this embodiment includes: an insulating layer 50 , circuit patterns buried in both sides of the insulating layer 50 ; a conductive via 58 electrically connecting the both sides of the insulating layer 50 ; a primer resin layer 30 stacked over one side of the insulating layer 50 ; and a solder-resist layer covering the primer resin layer 30 .
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
A printed circuit board and a manufacturing method of the same are disclosed. The method includes: preparing a carrier including a primer resin layer formed thereon; forming a circuit pattern on the primer resin layer; stacking the carrier onto an insulating layer such that the circuit pattern is buried in the insulating layer; removing the carrier; forming a via hole in the insulating layer on which the primer resin layer is stacked; and forming a conductive via in the via hole. The conductive via is formed by forming a plating layer in the via hole and on the primer resin layer and removing a portion of the plating layer formed over the primer resin layer.
Description
- This application claims the benefit of Korean Patent Application No. 10-2009-0099217, filed with the Korean Intellectual Property Office on Oct. 19, 2009, the disclosure of which is incorporated herein by reference in its entirety.
- 1. Technical Field
- The present invention relates to a printed circuit board and a manufacturing method thereof.
- 2. Description of the Related Art
- With the recent trend for a high density multi-functional package board having an electro-device, there has been an increasing demand for high density circuit patterns that are formed on a substrate.
- According to the related art, circuit patterns are formed on the surface of an insulating layer. However, since the structure is not suitable for high density circuit patterns, a technique of burying circuit patterns in the insulating layer has been introduced. According to the technique, a carrier is prepared, and a circuit pattern is formed over the carrier. And then, the circuit pattern is transferred to an insulating resin.
- Here, since a metal barrier is interposed between the carrier and the circuit pattern, there is a limit to simplification of manufacturing processes because the metal barrier has to be etched while the circuit pattern is transferred to the insulating resin. In addition, when a hole is processed in the insulating resin in order to form a via for interlayer connection, a portion of the metal barrier has to be opened, before the hole is processed. In that case, an interlayer accuracy may be deteriorated due to the process of opening a portion of the metal barrier.
- An aspect of the present invention provides a method of manufacturing a printed circuit board, which can include: preparing a carrier including a primer resin layer formed thereon; forming a circuit pattern on the primer resin layer; stacking the carrier onto an insulating layer such that the circuit pattern is buried in the insulating layer; removing the carrier; forming a via hole in the insulating layer on which the primer resin layer is stacked; and forming a conductive via in the via hole. The conductive via can be formed by forming a plating layer in the via hole and on the primer resin layer and removing a portion of the plating layer formed over the primer resin layer.
- The carrier can be made of metal, and the via hole can be a blind via hole (BVH).
- The via hole can be formed by performing a laser processing from a direction of the primer resin layer.
- Another aspect of the present invention provides a printed circuit board. The printed circuit board can include: an insulating layer including circuit patterns buried in both sides of the insulating layer; a via electrically connecting the both sides of the insulating layer; a primer resin layer stacked over one side of the insulating layer; and a solder-resist layer covering the primer resin layer.
- The via hole can be a blind via hole (BVH).
-
FIG. 1 is a flowchart illustrating a method of manufacturing a printed circuit board according to an embodiment of the invention. -
FIGS. 2 to 14 illustrate processes for a method of manufacturing a printed circuit board according to an embodiment of the invention. -
FIG. 15 illustrates a process that two carriers are compressed on upper and lower sides of the insulating layer, respectively. - As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to particular modes of practice, and it is to be appreciated that all changes, equivalents, and substitutes that do not depart from the spirit and technical scope of the present invention are encompassed in the present invention. In the description of the present invention, certain detailed description of related art is omitted when it is deemed that it may unnecessarily obscure the essence of the invention.
- A printed circuit board and a manufacturing method thereof according to certain embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. Those components that are the same or are in correspondence are rendered the same reference numeral regardless of the figure number, and redundant descriptions are omitted.
-
FIG. 1 is a flowchart illustrating a method of manufacturing a printed circuit board according to an embodiment of the invention, andFIGS. 2 to 14 illustrate processes for a method of manufacturing a printed circuit board according to an embodiment of the invention. Illustrated inFIGS. 2 to 14 are a supportingmember 10, acarrier 20, aprimer resin layer 30, ametal foil 40, aplating resist 42,circuit patterns insulating layer 50, avia hole 52, platedmetal 56, a conductive via 58 and aninner substrate 60. - First, a
carrier 20 including aprimer resin layer 30 is prepared (S110), and acircuit pattern 44 is formed on the primer resin layer 30 (S120). For that, as shown inFIG. 2 , a structure includes, in the successive order of,carriers 20,primer resin layers 30 andmetal foils 40 on both sides of a supportingmember 10. Here, the supportingmember 10 may be made of, for example, a thermoplastic material whose adhesion can be reduced when the supportingmember 10 is heated. Thecarriers 20 stacked on both sides of the supportingmember 10 are to be separated from the supportingmember 10 later. Themetal foil 40 may be made of copper or other conductive metal. - Next, as shown in
FIG. 3 , a patternedplating resist 42 is formed over themetal foil 40, and acircuit pattern 44 is formed by an electro-plating process. Here, since themetal foil 40 formed over theprimer resin layer 30 can serve as a seed layer, the electro-plating process for forming thecircuit pattern 44 can be carried out. Then theplating resist 42 is removed, and acircuit pattern 44 is formed on themetal foil 40 such that thecircuit pattern 44 has a protruding shape. - Next, as shown in
FIG. 5 , thecarriers 20 stacked on the supportingmember 10 are separated from the supportingmember 10. Before that, a surface-treatment process may be carried out on thecircuit pattern 44 such that enough adhesion between thecircuit pattern 44 and theinsulating layer 50 can be ensured. When the surface-treatment process is carried out by flash etching etc., a roughness may be formed on the surface of thecircuit pattern 44 and the adhesion between thecircuit pattern 44 and theinsulating layer 50 can be increased. During this process, the exposed portions of themetal foil 40 on theprimer resin layer 30 may be removed. - Then, as shown in
FIGS. 6 and 7 , thecarrier 20 is stacked onto aninsulating layer 50 and thecircuit pattern 44 is buried in the insulating layer 50 (S130). Since theprimer resin layer 30 andcircuit pattern 44 are formed on the surface of thecarrier 20, thecircuit pattern 44 can be buried in theinsulating layer 50 when thecarrier 20 is stacked on theinsulating layer 50. Here, theinsulating layer 50 may be in B-stage, that is, semi-hardened. In that case, thecircuit pattern 44 may be buried in theinsulating layer 50 easily. And then, the solid bonding strength between thecircuit pattern 44 and theinsulating layer 50 may be obtained when theinsulating layer 50 is hardened. - Meanwhile, as shown in
FIG. 6 , aninner substrate 62 may be stacked on the lower surface of theinsulating layer 50. Acircuit pattern 62 may be formed on the surface of theinner substrate 62, and buried in theinsulating layer 50 by stacking each other. - When a 2-layers substrate is needed, two
carriers 20 separated from the supportingmember 10 may be compressed on upper and lower sides of theinsulating layer 50, respectively, as shown inFIG. 15 . In that case,circuit patterns 44 may be buried in both sides of theinsulating layer 50 at the same time in one process. - Next, as shown in
FIG. 8 , thecarrier 20 is removed (S140). When thecarrier 20 is made of metal, thecarrier 20 may be removed by a wet-etching process with etchant. In that case, since the upper surface of thecircuit pattern 44 buried in theinsulating layer 50 is covered by theprimer resin layer 30, thecircuit pattern 44 may not be damaged by the etchant used for removing thecarrier 20. - Next, as shown in
FIG. 9 , avia hole 52 is processed (S150). A laser may be used for processing thevia hole 52. In this embodiment, since thecircuit pattern 44 is covered by theprimer resin layer 30, thevia hole 52 may be processed directly without processing a window. Also, when a lower side of thevia hole 52 is covered by acircuit pattern 62 formed on theinner substrate 60, that is, thevia hole 52 is a blind via hole (BVH), a depth of thevia bole 52 may be controlled easily. - Next, a via 85 for interlayer connection is formed in the via hole 52 (S160). A brief description is set forth below.
- First, as shown in
FIG. 10 , aseed layer 54 is formed on theprimer resin layer 30 and inner wall of the viahole 52. For that, an electroless plating process may be carried out. - Then, plated
metal 52 is filled in the viahole 52 by an electro-plating process, as shown inFIG. 11 . The platedmetal 52 filled in the viahole 52 can serve as a conductive via 58 for interlayer connection. The platedmetal 52 may be copper (Cu) or whatever is suitable for transmitting electric signals. - Next, as shown in
FIG. 12 , a portion of the platedmetal 52 formed over theprimer resin layer 30 is removed. For that, a wet-etching process with an etchant may be carried out. In that case, theprimer resin layer 30 formed on the surface of the insulatinglayer 50 can serve as an etch-stop barrier. - And, as shown in
FIG. 13 , a solder resistlayer 70 is formed by dispensing solder resist ink while theprimer resin layer 30 remains. - A printed circuit board manufactured by the processes set forth above is illustrated in
FIG. 14 . With reference toFIG. 14 , a printed circuit board according to this embodiment includes: an insulatinglayer 50, circuit patterns buried in both sides of the insulatinglayer 50; a conductive via 58 electrically connecting the both sides of the insulatinglayer 50; aprimer resin layer 30 stacked over one side of the insulatinglayer 50; and a solder-resist layer covering theprimer resin layer 30. - While the spirit of the present invention has been described in detail with reference to particular embodiments, the embodiments are for illustrative purposes only and shall not limit the present invention. It is to be appreciated that those skilled in the art can change or modify the embodiments without departing from the scope and spirit of the present invention.
- As such, many embodiments other than those set forth above can be found in the appended claims.
Claims (5)
1. A method of manufacturing a printed circuit board, the method comprising:
preparing a carrier including a primer resin layer formed thereon;
forming a circuit pattern on the primer resin layer;
stacking the carrier onto an insulating layer such that the circuit pattern is buried in the insulating layer;
removing the carrier;
forming a via hole in the insulating layer, the primer resin layer being stacked on the insulating layer; and
forming a conductive via in the via hole by forming a plating layer in the via hole and on the primer resin layer and removing a portion of the plating layer formed over the primer resin layer.
2. The method of claim 1 , wherein the carrier is made of metal.
3. The method of claim 1 , wherein the forming of a via hole comprises performing a laser processing from a direction of the primer resin layer.
4. The method of claim 3 , wherein the via hole is a blind via hole (BVH).
5-6. (canceled)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US13/953,650 US20130312901A1 (en) | 2009-10-19 | 2013-07-29 | Printed circuit board and manufacturing method thereof |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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KR1020090099217A KR101012403B1 (en) | 2009-10-19 | 2009-10-19 | Printed circuit board and manufacturing method thereof |
KR10-2009-0099217 | 2009-10-19 | ||
US12/651,191 US8497434B2 (en) | 2009-10-19 | 2009-12-31 | Printed circuit board and manufacturing method thereof |
US13/953,650 US20130312901A1 (en) | 2009-10-19 | 2013-07-29 | Printed circuit board and manufacturing method thereof |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US12/651,191 Division US8497434B2 (en) | 2009-10-19 | 2009-12-31 | Printed circuit board and manufacturing method thereof |
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US20130312901A1 true US20130312901A1 (en) | 2013-11-28 |
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Application Number | Title | Priority Date | Filing Date |
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US12/651,191 Expired - Fee Related US8497434B2 (en) | 2009-10-19 | 2009-12-31 | Printed circuit board and manufacturing method thereof |
US13/953,650 Abandoned US20130312901A1 (en) | 2009-10-19 | 2013-07-29 | Printed circuit board and manufacturing method thereof |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/651,191 Expired - Fee Related US8497434B2 (en) | 2009-10-19 | 2009-12-31 | Printed circuit board and manufacturing method thereof |
Country Status (5)
Country | Link |
---|---|
US (2) | US8497434B2 (en) |
JP (1) | JP4843707B2 (en) |
KR (1) | KR101012403B1 (en) |
CN (1) | CN102045950B (en) |
TW (1) | TWI387423B (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101013992B1 (en) * | 2008-12-02 | 2011-02-14 | 삼성전기주식회사 | Manufacturing method of Printed Circuit Board |
TWI474450B (en) * | 2013-09-27 | 2015-02-21 | Subtron Technology Co Ltd | Package carrier and manufacturing method thereof |
TWI517775B (en) * | 2014-03-06 | 2016-01-11 | 相互股份有限公司 | Printed circuit board and method thereof |
KR102126611B1 (en) * | 2014-12-30 | 2020-06-25 | 서키트 호일 룩셈부르크, 에스에이알엘 | Method for manufacturing peelable copper foil, coreless substrate and coreless substrate obtained by this method |
CN112638031A (en) * | 2019-09-24 | 2021-04-09 | 李家铭 | Circuit structure with interlayer guide hole and manufacturing method thereof |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060284640A1 (en) * | 2005-06-20 | 2006-12-21 | Shing-Ru Wang | Structure of circuit board and method for fabricating the same |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3612594B2 (en) * | 1998-05-29 | 2005-01-19 | 三井金属鉱業株式会社 | Composite foil with resin, method for producing the same, multilayer copper-clad laminate using the composite foil, and method for producing multilayer printed wiring board |
JP2001326436A (en) | 2000-05-17 | 2001-11-22 | Matsushita Electric Ind Co Ltd | Circuit formation substrate and its manufacturing method |
JP2002026475A (en) * | 2000-07-07 | 2002-01-25 | Mitsui Mining & Smelting Co Ltd | Copper foil circuit with carrier foil, method of manufacturing printed wiring board, using the same, and printed wiring board |
US6898850B2 (en) * | 2002-08-06 | 2005-05-31 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing circuit board and communication appliance |
JP4826053B2 (en) | 2003-08-18 | 2011-11-30 | 東レ株式会社 | Circuit board forming transfer sheet |
DE102004005300A1 (en) * | 2004-01-29 | 2005-09-08 | Atotech Deutschland Gmbh | Process for treating carrier material for the production of powder carriers and application of the process |
KR20070007173A (en) * | 2004-03-31 | 2007-01-12 | 다다히로 오미 | Circuit board and manufacturing method thereof |
KR100601485B1 (en) * | 2004-12-30 | 2006-07-18 | 삼성전기주식회사 | BGA package board and method for manufacturing thereof |
KR100782407B1 (en) | 2006-10-30 | 2007-12-05 | 삼성전기주식회사 | Method for manufacturing circuit board |
TWI337058B (en) * | 2007-02-16 | 2011-02-01 | Unimicron Technology Corp | Circuit board process |
-
2009
- 2009-10-19 KR KR1020090099217A patent/KR101012403B1/en not_active IP Right Cessation
- 2009-12-18 JP JP2009288125A patent/JP4843707B2/en not_active Expired - Fee Related
- 2009-12-28 TW TW098145375A patent/TWI387423B/en not_active IP Right Cessation
- 2009-12-31 CN CN2009102657695A patent/CN102045950B/en not_active Expired - Fee Related
- 2009-12-31 US US12/651,191 patent/US8497434B2/en not_active Expired - Fee Related
-
2013
- 2013-07-29 US US13/953,650 patent/US20130312901A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060284640A1 (en) * | 2005-06-20 | 2006-12-21 | Shing-Ru Wang | Structure of circuit board and method for fabricating the same |
Also Published As
Publication number | Publication date |
---|---|
TW201116184A (en) | 2011-05-01 |
CN102045950B (en) | 2013-12-11 |
CN102045950A (en) | 2011-05-04 |
TWI387423B (en) | 2013-02-21 |
US20110088930A1 (en) | 2011-04-21 |
US8497434B2 (en) | 2013-07-30 |
KR101012403B1 (en) | 2011-02-09 |
JP2011086897A (en) | 2011-04-28 |
JP4843707B2 (en) | 2011-12-21 |
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