KR20140146447A - Printed circuit board and method for manufacturing of the same - Google Patents

Abstract

The present invention relates to a printed circuit board and a manufacturing method thereof. The printed circuit board according to the embodiment of the present invention includes an insulation layer, a plurality of metal pillars which are formed in the insulation layer and are mutually stacked, and a circuit layer which is formed on the insulation layer and is formed between the stacked metal pillars. The printed circuit board and the manufacturing method thereof according to the embodiment of the present invention remove a polishing process by forming the metal pillars.

Description

TECHNICAL FIELD [0001] The present invention relates to a printed circuit board and a method of manufacturing the printed circuit board.

The present invention relates to a printed circuit board and a method for manufacturing a printed circuit board.

Recently, trend of multi - functional and high - speed electronic products is progressing at a rapid pace. In order to cope with this trend, printed circuit boards on which semiconductor chips and semiconductor chips are mounted are also developing at a very high speed. Such a printed circuit board is required to have a light weight and short circuit, a fine circuit, excellent electrical characteristics, high reliability, and high-speed signal transmission.

Conventionally, a core substrate for preventing warpage of a printed circuit board by inserting a core layer therein has been mainly used. However, in the case of the core substrate, the thickness is thick and the signal processing time is long (US Patent Publication No. 20040058136). Accordingly, in order to cope with thinning of the printed circuit board due to power generation, A coreless substrate capable of shortening a signal processing time has been attracting attention. When forming the build-up layer of the core-less substrate, a via is formed for interlayer connection. The via formation is performed after the via hole is formed in the insulating layer and the via is formed in the via hole, followed by the polishing process. Or even if a via is formed first and an insulating layer is formed, polishing must be performed to expose the top surface of the via. Such a polishing process adds stress to the substrate.

One aspect of the present invention is to provide a printed circuit board and a printed circuit board manufacturing method which can omit the polishing process.

Another aspect of the present invention is to provide a printed circuit board and a method of manufacturing a printed circuit board which can easily manufacture various numbers of layers.

According to an embodiment of the present invention, there is provided a printed circuit board comprising a plurality of insulating layers, a plurality of insulating layers formed in the insulating layer, a plurality of metal fillers formed on the insulating layers and a circuit layer formed between the metal fillers, / RTI >

The circuit layer is formed on the metal pillar and may be further formed on at least one of the one surface and the other surface of the insulating layer.

And a solder resist layer formed on at least one of the one surface and the other surface of the insulating layer and including an opening exposing the circuit layer.

The insulating layer may be formed of ABF (Ajinomoto Build up Film).

One or more inner layer circuit layers may be further formed in the insulating layer.

According to another embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of preparing a carrier substrate, forming a first metal filler on a carrier substrate, forming a first insulating layer on the carrier substrate, Forming a first circuit layer on at least one of a first surface and a second surface of the first insulating layer and the first metal filler.

The carrier substrate may include an insulating resin and a copper foil formed on at least one surface of the insulating resin.

The step of forming the metal filler includes the steps of forming a first photosensitive resist, which is formed on at least one surface of the carrier substrate and on the other surface, the first photosensitive resist including a first opening, filling the first opening with a conductive metal, And removing the first photosensitive resist.

The step of forming the first insulating layer includes the steps of preparing a first insulating layer having an opening through which the first metal filler is inserted, and stacking a first insulating layer on the carrier substrate so that the first metal filler is inserted into the opening One surface of the first insulating layer stacked on the carrier substrate and one surface of the first metal filler may be located on the same line.

The step of forming the first circuit layer includes the steps of forming a first plating layer on the first insulating layer, forming a first etching resist patterned on the first plating layer and patterned to be located in a region corresponding to the first circuit layer Etching the first plated layer to form a first circuit layer, and removing the first etch resist.

Forming the first seed layer by an electroless plating method on the first insulating layer before the step of forming the first plating layer.

In the step of forming the first plating layer, the first plating layer may be formed by an electrolytic plating method.

And forming a first solder resist, which is formed on the first insulating layer after the step of forming the first circuit layer, on which the opening is formed to expose the first circuit layer.

Forming a second metal filler on the first circuit layer after the step of forming the first circuit layer, forming a second insulating layer on the first insulating layer and exposing one surface or the other surface of the second metal filler And forming a second circuit layer on the second insulating layer and the second metal filler.

Forming a second metal filler comprises forming a second photosensitive resist formed in the first insulating layer and including a second opening exposing the first circuit layer, filling the second opening with a conductive metal to form a second, Forming the metal filler, and removing the second photosensitive resist.

The forming of the second insulating layer may include preparing a second insulating layer having an opening into which the second metal filler is inserted, and stacking a second insulating layer on the first insulating layer such that the second metal filler is inserted into the opening Wherein one surface of the second insulating layer stacked on the first insulating layer and one surface of the second metal filler may be located on the same line.

The step of forming the second circuit layer includes the steps of forming a second plating layer on the second insulating layer, forming a second etching resist patterned on the second plating layer and patterned to be located in a region corresponding to the second circuit layer Etching the second plating layer to form a second circuit layer, and removing the second etching resist.

And forming the second seed layer by an electroless plating method on the second insulating layer before the step of forming the second plating layer.

In the step of forming the second plating layer, the second plating layer may be formed by an electrolytic plating method.

And forming a second solder resist, which is formed on the second insulating layer after the step of forming the second circuit layer, and in which an opening is formed to expose the second circuit layer.

One or more inner layer circuit layers may be further formed in the first insulating layer.

The features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings.

Prior to that, terms and words used in the present specification and claims should not be construed in a conventional and dictionary sense, and the inventor may properly define the concept of the term in order to best explain its invention It should be construed as meaning and concept consistent with the technical idea of the present invention.

In the method for manufacturing a printed circuit board and a printed circuit board according to an embodiment of the present invention, the metal pillar is formed, so that the polishing process can be omitted.

In the method of manufacturing a printed circuit board and a printed circuit board according to an embodiment of the present invention, the stress applied to the printed circuit board may be reduced by omitting the polishing process.

The printed circuit board and the printed circuit board manufacturing method according to the embodiments of the present invention can easily manufacture various numbers of layers.

1 is an exemplary view illustrating a printed circuit board according to an embodiment of the present invention.
2 to 28 are flowcharts illustrating a method of manufacturing a printed circuit board according to an embodiment of the present invention.
29 is an exemplary view illustrating a printed circuit board according to another embodiment of the present invention.
30 to 40 are flowcharts illustrating a method of manufacturing a printed circuit board according to another embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The objectives, specific advantages, and novel features of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. It should be noted that, in the present specification, the reference numerals are added to the constituent elements of the drawings, and the same constituent elements are assigned the same number as much as possible even if they are displayed on different drawings. It will be further understood that terms such as " first, "" second," " one side, "" other," and the like are used to distinguish one element from another, no. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description of the present invention, detailed description of related arts which may unnecessarily obscure the gist of the present invention will be omitted.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an exemplary view illustrating a printed circuit board according to an embodiment of the present invention.

Referring to FIG. 1, the printed circuit board 100 is a coreless substrate including five circuit layers. The printed circuit board 100 includes a first insulating layer 121 to a fourth insulating layer 124, a first metal filler 111 to a fourth metal filler 114, a first circuit layer 151, Layer 155 and a first solder resist layer 161 to a second solder resist layer 162. [

The first insulating layer 121 to the fourth insulating layer 124 may be an insulating material capable of electroless plating. For example, ABF (Ajinomoto Build up Film). However, the material of the first insulating layer 121 to the fourth insulating layer 124 is not limited to ABF, and any insulating material capable of electroless plating may be employed. In addition, the first insulating layer 121 to the fourth insulating layer 124 may be formed in the form of a substrate or a film.

The first metal filler 111 to the fourth metal filler 114 may be embedded in the first insulating layer 121 to the fourth insulating layer 124. The first metal filler 111 to the fourth metal filler 114 may be formed of an electrically conductive metal. For example, the first metal filler 111 to the fourth metal filler 114 may be formed of copper. However, the materials of the first metal filler 111 to the fourth metal filler 114 are not limited to copper. The first metal filler 111 to the fourth metal filler 114 are applicable to any conductive metal conventionally used in the field of circuit boards.

The first to fifth circuit layers 151 to 155 may include circuit patterns and connection pads. Here, the connection pad is a structure for electrically connecting the stacked metal pillars. In the embodiment of the present invention, a structure for transmitting an electric signal such as a circuit pattern and a connection pad will be collectively referred to as a circuit layer. The first circuit layer 151 to the fifth circuit layer 155 may be electrically connected to the first metal filler 111 to the fourth metal filler 114. Here, the fourth circuit layer 154 and the fifth circuit layer 155 formed at the outermost portion of the printed circuit board 100 may be electrically connected to an external electronic component (not shown) or a substrate (not shown). The first circuit layer 151 to the fifth circuit layer 155 may be formed of an electrically conductive metal. For example, the first to fifth circuit layers 151 to 155 may be formed of copper. However, the material of the first circuit layer 151 to the fifth circuit layer 155 is not limited to copper. The first circuit layer 151 to the fifth circuit layer 155 are applicable without limitation as long as they are used as a conductive metal conventionally used in the field of circuit boards.

According to the printed circuit board 100 of the five-layer structure shown in FIG. 1, the first metal filler 111 may be formed in the first insulating layer 121. The first circuit layer 151 may be formed on one surface of the first insulating layer 121 and the first metal pillar 111. The second insulating layer 122 may be formed on one surface of the first insulating layer 121 and the first circuit layer 151. The second metal filler 112 may be formed on one surface of the first circuit layer 151 and may be embedded in the second insulating layer 122. The second circuit layer 152 may be formed on one surface of the second insulating layer 122 and the second metal filler 112. The third insulating layer 123 may be formed on one surface of the second insulating layer 122 and the second circuit layer 152. The third metal filler 113 may be formed on one surface of the second circuit layer 152 and may be embedded in the third insulating layer 123. The third circuit layer 153 may be formed on one surface of the third insulating layer 123 and the third metal pillar 113. The fourth insulating layer 124 may be formed on one surface of the third insulating layer 123 and the third circuit layer 153. The fourth metal filler 114 may be formed on one surface of the third circuit layer 153 and may be embedded in the fourth insulating layer 124. The fourth circuit layer 154 may be formed on one surface of the fourth insulating layer 124 and the fourth metal filler 114. The fifth circuit layer 155 may be formed on the other surface of the first insulating layer 121 and the first metal pillar 111.

The first solder resist layer 161 may be formed on one side of the fourth insulating layer 124. The first solder resist layer 161 may be formed with an opening for exposing the connection pad of the fourth circuit layer 154 to the outside.

The second solder resist layer 162 may be formed on the other surface of the first insulating layer 121. The second solder resist layer 162 may be formed with an opening for exposing the connection pad of the fifth circuit layer 155 to the outside.

Although the printed circuit board 100 according to the embodiment of the present invention is not shown, when a circuit pattern is formed on one surface of the fourth insulating layer 124, the circuit pattern is buried by the first solder resist layer 161, . Further, when a circuit pattern is formed on the other surface of the first insulating layer 121, the circuit pattern can be buried and protected by the second solder resist layer 162.

2 to 28 are flowcharts illustrating a method of manufacturing a printed circuit board according to an embodiment of the present invention.

According to the method for manufacturing a printed circuit board according to an embodiment of the present invention, a coreless substrate having a five-layer structure can be manufactured.

Referring to FIG. 2, a carrier substrate 210 may be provided. According to an embodiment of the present invention, the carrier substrate 210 may have a CCL structure in which a copper foil 212 is laminated on both sides of an insulating material 211 and an insulating material 211. However, the type of the carrier substrate 210 is not limited thereto, and any of the types of the carrier substrate 210 that is typically used can be used.

Referring to FIG. 3, a first plating resist 221 may be formed on one side and the other side of the carrier substrate 210. The first plating resist 221 may be a photosensitive resist. For example, the first plating resist 221 may be formed of a dry film. The first plating resist 221 can be patterned by performing exposure and development. The first plating resist 221 may be patterned such that a region where the first metal filler (111 in FIG. 4) is to be formed later is opened.

Referring to FIG. 4, a first metal filler 111 may be formed. The first metal filler 111 may be formed by filling an electrically conductive metal in an area opened by the first plating resist 221. For example, the first metal filler 111 may be formed of copper. However, the material of the first metal filler 111 is not limited to copper, and is not limited as long as it is used as a conductive metal conventionally used in the field of circuit boards. After the first metal filler 111 is formed, the first plating resist 221 can be removed.

Referring to FIG. 5, a first insulating layer 121 may be formed. The first insulating layer 121 may be formed to fill the first metal filler 111. At this time, one surface of the first metal filler 111 and one surface of the first insulating layer 121 are located on the same line, and one surface of the first metal filler 111 may be exposed to the outside. For example, the first insulating layer 121 may have an opening through which the first metal filler 111 is inserted. The first insulating layer 121 may be stacked on the carrier substrate 210 by inserting the first metal filler 111 into the opening. The first insulating layer 121 may have a thickness such that one surface of the first insulating layer 121 and one surface of the first metal filler 111 may be positioned on the same line when the carrier insulating layer 121 is laminated on the carrier substrate 210 .

The first insulating layer 121 may be a material capable of chemical plating. For example, the first insulation layer 121 may be an ABF (Ajinomoto Build-up Film). However, the material of the first insulating layer 121 is not limited to ABF, and may be any insulating material capable of chemical plating.

In an embodiment of the present invention, the metal filler may be formed by a plating resist having an opening formed therein. Therefore, the plurality of metal pillar can be formed to have the same thickness. Since the metal filler can be formed to have the same thickness, the insulating layer can also be patterned in advance so as to have a thickness that can be located on the same line as one surface of the metal filler. By previously adjusting the thickness of the insulating layer and then laminating the insulating layer on the substrate, the polishing step or the via hole forming step performed after the insulating layer is stacked as in the conventional method can be omitted.

Referring to FIG. 6, a first plating layer 141 may be formed. First, a first seed layer 131 may be formed on one surface of the first insulating layer 121 and the first metal filler 111. The first seed layer 131 may be formed by an electroless plating method. For example, the first seed layer 131 may be formed by a chemical plating method. Also, the first seed layer 131 may be formed thinly by PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition) method. A first plating layer 141 may be formed on one surface of the first seed layer 131. The first plating layer 141 may be formed by an electrolytic plating method. The first seed layer 131 and the first plating layer 141 may be formed of an electrically conductive metal. For example, the first seed layer 131 and the first plating layer 141 may be formed of copper. However, the materials of the first seed layer 131 and the first plating layer 141 are not limited to copper. The first seed layer 131 and the first plating layer 141 are not limited as long as they are used as a conductive metal conventionally used in the field of circuit boards.

Referring to FIG. 7, a first etching resist 231 may be formed on one surface of the first plating layer 141. The first etching resist 231 may be patterned to be present only in a portion of the first plating layer 141 where the first circuit layer (151 in FIG. 8) is to be formed later. For example, the first etching resist 231 may be patterned to exist in the upper region of the first metal pillar 111.

Referring to FIG. 8, a first circuit layer 151 may be formed. The first circuit layer 151 may include circuit patterns and connection pads. After the first etching resist 231 is formed, etching of the first plating layer 141 and the first seed layer 131 can be performed. Thus, the first plating layer 141 and the first seed layer 131 in the region where the first etching resist 231 is not present can be removed. Thereafter, the first etching resist 231 can be removed. The first circuit layer 151 electrically connected to the first metal filler 111 may be formed through the above process.

Referring to FIG. 9, a second plating resist 222 may be formed on one surface of the first insulating layer 121 and the first circuit layer 151. The second plating resist 222 may be a photosensitive resist. For example, the second plating resist 222 may be formed of a dry film. The second plating resist 222 can be patterned by performing exposure and development. The second plating resist 222 may be patterned so that a region where the second metal filler (112 of FIG. 10) is to be formed later is opened.

Since the process of forming the circuit layer, the insulating layer, and the metal filler is the same on one side and the other side of the carrier substrate 210, the following description of the process steps performed on the other side of the carrier substrate 210 will be omitted.

Referring to FIG. 10, a second metal filler 112 may be formed. The second metal filler 112 may be formed by filling an electrically conductive metal in an area opened by the second plating resist 222. The second metal filler 112 may be formed by an electroplating method. After the second metal filler 112 is formed, the second plating resist 222 can be removed.

Referring to FIG. 11, a second insulating layer 122 may be formed. The second insulating layer 122 may be formed to expose one surface of the second metal filler 112. At this time, one surface of the second metal filler 112 and one surface of the second insulating layer 122 may be located on the same line. For example, the second insulating layer 122 may be formed with an opening through which the second metal filler 112 is inserted. The second insulating layer 122 may be stacked on the first insulating layer 121 by inserting a second metal filler 112 into the opening. The second insulating layer 122 may have a thickness such that one surface of the second insulating layer 122 and one surface of the second metal filler 112 may be positioned on the same line when the first insulating layer 122 is stacked on the first insulating layer 121 .

The second insulating layer 122 may be a material capable of chemical plating. For example, the second insulation layer 122 may be ABF (Ajinomoto Build-up Film). However, the material of the second insulating layer 122 is not limited to ABF, and may be any insulating material capable of chemical plating.

Referring to FIG. 12, a second plating layer 142 may be formed. First, a second seed layer 132 may be formed on one surface of the second insulating layer 122 and the second metal filler 112. The second seed layer 132 may be formed by an electroless plating method. For example, the second seed layer 132 may be formed by a chemical plating method. In addition, the second seed layer 132 may be formed thinly by PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition) method. A second plating layer 142 may be formed on one surface of the second seed layer 132. The second plating layer 142 may be formed by an electrolytic plating method. The second seed layer 132 and the second plating layer 142 may be formed of copper. However, the material of the second seed layer 132 and the second plating layer 142 is not limited to copper, and is not limited as long as it is used as a conductive metal conventionally used in the field of circuit boards.

Referring to FIG. 13, a second etching resist 232 may be formed on one surface of the second plating layer 142. The second etching resist 232 may be patterned to be present only in a region of the second plating layer 142 where the second circuit layer (152 in Fig. 14) is to be formed later. For example, the second etch resist 232 may be patterned to reside in the upper region of the second metal filler 112.

Referring to FIG. 14, a second circuit layer 152 may be formed. The second circuit layer 152 may be formed by performing etching on the second plating layer 142 and the second seed layer 132 of the region exposed by the second etching resist 232. [ Thereafter, the second etching resist 232 can be removed. The second circuit layer 152 thus formed may be electrically connected to the second metal filler 112.

Referring to FIG. 15, a third plating resist 223 may be formed on one surface of the second insulating layer 122 and the second circuit layer 152. The third plating resist 223 may be a photosensitive resist. For example, the third plating resist 223 may be formed of a dry film. The third plating resist 223 can be patterned by performing exposure and development. The third plating resist 223 may be patterned so that the area where the third metal filler (113 of FIG. 16) is to be formed later is opened.

Referring to FIG. 16, a third metal filler 113 may be formed. The third metal filler 113 may be formed by filling an electrically conductive metal in a region opened by the third plating resist 223. The third metal filler 113 may be formed by an electroplating method. After the third metal filler 113 is formed, the third plating resist 223 can be removed.

Referring to FIG. 17, a third insulating layer 123 may be formed. For example, the third insulating layer 123 may have an opening through which the third metal filler 113 is inserted. The third insulating layer 123 may be stacked on the second insulating layer 122 by inserting a third metal filler 113 into the opening. The third insulating layer 123 may have a thickness that allows one surface of the third insulating layer 123 and one surface of the third metal filler 113 to be located on the same line when stacked on the second insulating layer 122 . The third insulating layer 123 may be an insulating material capable of chemical plating such as ABF (Ajinomoto Build-up Film).

Referring to FIG. 18, a third plating layer 143 may be formed. First, a third seed layer 133 may be formed on one surface of the third insulating layer 123 and the third metal filler 113. The third seed layer 133 may be formed by an electroless plating method. For example, the third seed layer 133 may be formed by a chemical plating method. Also, the third seed layer 133 may be formed thinly by PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition) method. A third plating layer 143 may be formed on one surface of the third seed layer 133. The third plating layer 143 may be formed by an electrolytic plating method. The third seed layer 133 and the third plating layer 143 may be formed of copper. However, the material of the third seed layer 133 and the third plating layer 143 is not limited to copper, and is not limited as long as it is used as a conductive metal conventionally used in the field of circuit boards.

Referring to FIG. 19, a third etching resist 233 may be formed on one surface of the third plating layer 143. The third etching resist 233 may be patterned to be present only in a region of the third plating layer 143 where the third circuit layer (153 in FIG. 20) is to be formed later. For example, the third etch resist 233 may be patterned to be present in the upper region of the third metal filler 113.

Referring to FIG. 20, a third circuit layer 153 may be formed. The third circuit layer 153 may be formed by performing etching on the third plating layer 143 and the third seed layer 133 in the region exposed by the third etching resist 233. [ Thereafter, the third etching resist 233 can be removed. The third circuit layer 153 thus formed may be electrically connected to the third metal filler 113.

Referring to FIG. 21, a fourth plating resist 224 may be formed on one surface of the third insulating layer 123 and the third circuit layer 153. The fourth plating resist 224 may be a photosensitive resist. For example, the fourth plating resist 224 may be formed of a dry film. The fourth plating resist 224 may be patterned by performing exposure and development. The fourth plating resist 224 may be patterned so that the region where the fourth metal filler (114 of FIG. 22) is to be formed later is opened.

Referring to FIG. 22, a fourth metal filler 114 may be formed. The fourth metal filler 114 may be formed by filling an electrically conductive metal into the open area by the fourth plating resist 224. The fourth metal filler 114 may be formed by an electroplating method. After the fourth metal filler 114 is formed, the fourth plating resist 224 can be removed.

Referring to FIG. 23, a fourth insulating layer 124 may be formed. For example, the fourth insulating layer 124 may have an opening in which the fourth metal filler 114 is inserted. The fourth insulating layer 124 may be stacked on the third insulating layer 123 by inserting a fourth metal filler 114 into the opening. The fourth insulating layer 124 has a thickness such that one surface of the fourth insulating layer 124 and one surface of the fourth metal filler 114 can be positioned in the same line when the third insulating layer 124 is laminated on the third insulating layer 123 . The fourth insulating layer 124 may be an insulating material capable of chemical plating such as ABF (Ajinomoto Build-up Film).

Referring to Fig. 24, the carrier substrate 210 (Fig. 23) can be removed. By removing the carrier substrate 210 (Fig. 23), the buildup layer A formed on one side and the other side of the carrier substrate 210 (Fig. 23) can be separated. The carrier substrate 210 (Fig. 23) can be removed by a conventional carrier substrate removing method. Although only the buildup layer A formed on one side of the carrier substrate 210 (FIG. 23) is shown in FIG. 24, it is obvious that the buildup layer formed on the other side of the carrier substrate 210 has the same structure.

Referring to FIG. 25, a fourth plating layer 144 and a fifth plating layer 145 may be formed. First, the fourth seed layer 134 may be formed on one surface of the fourth insulating layer 124 and the fourth metal filler 114. In addition, a fifth seed layer 135 may be formed on the other surface of the first insulating layer 121 and the first metal filler 111. The fourth seed layer 134 and the fifth seed layer 135 may be formed by an electroless plating method. For example, the fourth seed layer 134 and the fifth seed layer 135 may be formed by a chemical plating method. The fourth seed layer 134 and the fifth seed layer 135 may be thinly formed by a PVD (Physical Vapor Deposition) method or a CVD (Chemical Vapor Deposition) method. A fourth plating layer 144 may be formed on one surface of the fourth seed layer 134. In addition, a fifth plating layer 145 may be formed on the other surface of the fifth seed layer 135. The fourth plating layer 144 and the fifth plating layer 145 may be formed by an electrolytic plating method. The fourth seed layer 134, the fifth seed layer 135, the fourth plating layer 144, and the fifth plating layer 145 may be formed of copper. However, the material of the fourth seed layer 134, the fifth seed layer 135, the fourth plating layer 144, and the fifth plating layer 145 is not limited to copper, and may be a conductive metal The present invention is not limited thereto.

Referring to FIG. 26, a fourth etching resist 234 may be formed on one surface of the fourth plating layer 144. A fifth etching resist 235 may be formed on the other surface of the fifth plating layer 145.

The fourth etching resist 234 may be patterned so as to be present only in a region where the fourth circuit layer (154 in FIG. 27) is to be formed later. For example, a fourth etch resist 234 may be patterned to reside in the upper region of the fourth metal filler 114.

The fifth etching resist 235 may be patterned so as to exist later only in the region where the fifth circuit layer (155 in FIG. 27) is to be formed. For example, the fifth etching resist 235 may be patterned to exist in the lower region of the first metal pillar 111. [

Referring to FIG. 27, a fourth circuit layer 154 and a fifth circuit layer 155 may be formed.

The fourth circuit layer 154 may be formed by performing etching on the fourth plating layer 144 and the fourth seed layer 134 of the region exposed by the fourth etching resist 234. [ Thereafter, the fourth etching resist 234 can be removed. One surface of the fourth circuit layer 154 thus formed may be electrically connected to an external electronic component (not shown) or a substrate (not shown) to be mounted later. The other surface of the fourth circuit layer 154 may be electrically connected to the fourth metal filler 114.

The fifth circuit layer 155 may be formed by performing etching on the fifth plating layer 145 and the fifth seed layer 135 of the region exposed by the fifth etching resist 235. [ Thereafter, the fifth etching resist 235 can be removed. One surface of the fifth circuit layer 155 thus formed may be electrically connected to the first metal pillar 111. The other surface of the fifth circuit layer 155 may be electrically connected to an external electronic component (not shown) or a substrate (not shown) to be mounted later.

Referring to FIG. 28, a first solder resist layer 161 and a second solder resist layer 162 may be formed.

The first solder resist layer 161 and the second solder resist layer 162 are formed on the printed circuit board 100 according to an embodiment of the present invention when external electronic components (not shown) or a substrate (not shown) The fourth circuit layer 154, and the fifth circuit layer 155, as shown in FIG.

The first solder resist layer 161 may be formed on one side of the fourth insulating layer 124. The first solder resist layer 161 may be formed with an opening exposing the fourth circuit layer 154. Here, the fourth circuit layer 154 exposed by the first solder resist layer 161 may be a connection pad electrically connected to an external electronic component (not shown) or a substrate (not shown).

The second solder resist layer 162 may be formed on the other surface of the first insulating layer 121. The second solder resist layer 162 may be formed with an opening exposing the fifth circuit layer 155. Here, the fifth circuit layer 155 exposed by the second solder resist layer 162 may be a connection pad electrically connected to an external electronic component (not shown) or a substrate (not shown).

In the method of manufacturing a printed circuit board according to an embodiment of the present invention, the formation of a via hole and the filling of a via hole for electrical connection between circuit layers can be omitted by forming a metal filler.

In the embodiments of the present invention, a printed circuit board having a five-layer structure and a method of manufacturing the same are described, but the present invention is not limited thereto. That is, a printed circuit board having an odd number of circuit layers as well as a five-layer structure can be manufactured from the printed circuit board and the manufacturing method thereof according to the embodiment of the present invention.

29 is an exemplary view illustrating a printed circuit board according to another embodiment of the present invention.

Referring to FIG. 29, the printed circuit board 300 is a coreless substrate including a six-layer circuit layer. The printed circuit board 300 includes a first insulating layer 121 to a fifth insulating layer 125, a first metal filler 111 to a fifth metal filler 115, a first circuit layer 151 to a sixth circuit Layer 156 and a first solder resist layer 161 to a second solder resist layer 162.

The first insulating layer 121 to the fifth insulating layer 125 may be an insulating material capable of electroless plating. For example, ABF (Ajinomoto Build up Film). However, the material of the first insulating layer 121 to the fifth insulating layer 125 is not limited to ABF, and any insulating material capable of electroless plating may be employed.

The first metal filler 111 to the fifth metal filler 115 may be embedded in the first insulating layer 121 to the fifth insulating layer 125. The first metal filler 111 to the fifth metal filler 115 may be formed of an electrically conductive metal. For example, the first metal filler 111 to the fifth metal filler 115 may be formed of copper. However, the materials of the first metal filler 111 to the fifth metal filler 115 are not limited to copper. The first metal filler 111 to the fifth metal filler 115 may be used as a conductive metal conventionally used in the field of circuit boards without limitation.

The first to sixth circuit layers 151 to 156 may include circuit patterns and connection pads. The first circuit layer 151 to the sixth circuit layer 156 may be electrically connected to the first metal filler 111 to the fifth metal filler 115. The fifth circuit layer 155 and the sixth circuit layer 156 formed at the outermost portion of the printed circuit board 300 may be electrically connected to an external electronic component (not shown) or a substrate (not shown) . The first circuit layer 151 to the sixth circuit layer 156 may be formed of an electrically conductive metal. For example, the first circuit layer 151 to the sixth circuit layer 156 may be formed of copper. However, the material of the first circuit layer 151 to the sixth circuit layer 156 is not limited to copper. The first circuit layer 151 to the sixth circuit layer 156 can be applied without limitation as long as they are used as a conductive metal conventionally used in the field of circuit boards.

The first solder resist layer 161 may be formed on one surface of the fifth insulating layer 125. The first solder resist layer 161 may be formed with an opening for exposing the connection pad of the fifth circuit layer 155 to the outside.

The second solder resist layer 162 may be formed on the other surface of the first insulating layer 121. The second solder resist layer 162 may be formed with an opening for exposing the connection pad of the sixth circuit layer 156 to the outside.

30 to 40 are flowcharts illustrating a method of manufacturing a printed circuit board according to another embodiment of the present invention.

According to the method for manufacturing a printed circuit board according to another embodiment of the present invention, a coreless substrate having a six-layer structure can be manufactured.

Up to the step of forming the third insulating layer 123 among the methods of manufacturing the printed circuit board having the six-layer structure, the steps of providing the carrier substrate 210 to the third insulating layer 123 of FIGS. 2 to 17, And the forming method are the same. Therefore, the corresponding drawings and descriptions will be referred to FIG. 2 to FIG. 17, which will be omitted in the present embodiment. In addition, since the process of forming the circuit layer, the insulating layer, and the metal filler is the same on one side and the other side of the carrier substrate 210, the description and illustration of the process steps performed on the other side of the carrier substrate 210 will be omitted.

Referring to FIG. 30, after the third insulating layer 123 is formed, the carrier substrate 210 (FIG. 17) can be removed. By removing the carrier substrate 210 (Fig. 17), the buildup layer B formed on one side and the other side of the carrier substrate 210 (Fig. 17) can be separated. The carrier substrate (210 in Fig. 17) can be removed by a conventional carrier substrate removing method.

Referring to FIG. 31, a third plating layer 143 and a fourth plating layer 144 may be formed.

First, a third seed layer 133 and a fourth seed layer 134 may be formed. The third seed layer 133 may be formed on one surface of the third insulating layer 123 and the third metal filler 113. The fourth seed layer 134 may be formed on the other surface of the first insulating layer 121 and the first metal filler 111. The third seed layer 133 and the fourth seed layer 134 may be formed by an electroless plating method. For example, the third seed layer 133 and the fourth seed layer 134 may be formed by a chemical plating method. In addition, the third seed layer 133 and the fourth seed layer 134 may be formed thinly by PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition) method.

The third plating layer 143 may be formed on one surface of the third seed layer 133. The fourth plating layer 144 may be formed on the other surface of the fourth seed layer 134. The third plating layer 143 and the fourth plating layer 144 may be formed by an electrolytic plating method. The third seed layer 133, the fourth seed layer 134, the third plating layer 143, and the fourth plating layer 144 may be formed of copper. However, the material of the third seed layer 133, the fourth seed layer 134, the third plating layer 143 and the fourth plating layer 144 is not limited to copper, and may be a conductive metal The present invention is not limited thereto.

Referring to FIG. 32, a third etching resist 233 may be formed on one surface of the third plating layer 143. A fourth etching resist 234 may be formed on the other surface of the fourth plating layer 144.

The third etching resist 233 may be patterned so as to exist later only in the region where the third circuit layer (153 in FIG. 33) is to be formed. For example, the third etch resist 233 may be patterned to be present in the upper region of the third metal filler 113.

The fourth etching resist 234 may be patterned so that the fourth circuit layer (154 of FIG. 33) is present only in the region where it is to be formed. For example, a fourth etch resist 234 may be patterned to reside in the lower region of the first metal filler 111.

Referring to FIG. 33, a third circuit layer 153 and a fourth circuit layer 154 may be formed.

The third circuit layer 153 may be formed by performing etching on the third plating layer 143 and the third seed layer 133 in the region exposed by the third etching resist 233. [ Thereafter, the third etching resist 233 can be removed.

The fourth circuit layer 154 may be formed by performing etching on the fourth plating layer 144 and the fourth seed layer 134 of the region exposed by the fourth etching resist 234. [ Thereafter, the fourth etching resist 234 can be removed.

Referring to FIG. 34, the third plating resist 223 and the fourth plating resist 224 may be included.

The third plating resist 223 may be formed on one surface of the third insulating layer 123 and the third circuit layer 153. The third plating resist 223 may be patterned so that the region where the fourth metal filler (114 of FIG. 35) is to be formed later is opened.

The fourth plating resist 224 may be formed on the other surface of the fourth insulating layer 124 and the fourth circuit layer 154. The fourth plating resist 224 may be patterned so that the area where the fifth metal filler (115 of FIG. 35) is to be formed later is opened.

The third plating resist 223 and the fourth plating resist 224 may be photosensitive resist. For example, the third plating resist 223 and the fourth plating resist 224 may be formed of a dry film. The third plating resist 223 and the fourth plating resist 224 may be patterned by performing exposure and development.

Referring to FIG. 35, a fourth metal filler 114 and a fifth metal filler 115 may be formed. The fourth metal filler 114 may be formed by filling an electrically conductive metal in an area opened by the third plating resist 223. The fifth metal filler 115 may be formed by filling an electrically conductive metal in a region open by the fourth plating resist 224. For example, the fourth metal filler 114 and the fifth metal filler 115 may be formed of copper. However, the material of the fourth metal filler 114 and the fifth metal filler 115 is not limited to copper, and is not limited as long as it is used as a conductive metal conventionally used in the field of circuit boards. After the fourth metal filler 114 and the fifth metal filler 115 are formed, the third plating resist 223 and the fourth plating resist 224 can be removed.

Referring to FIG. 36, a fourth insulating layer 124 and a fifth insulating layer 125 may be formed.

The fourth insulating layer 124 may be formed on one surface of the third insulating layer 123 and may be formed so that one surface of the fourth insulating layer 124 and one surface of the fourth metal filler 114 are located on the same line. For example, the fourth insulating layer 124 may have an opening in which the fourth metal filler 114 is inserted. The fourth insulating layer 124 may be stacked on the third insulating layer 123 by inserting a fourth metal filler 114 into the opening. The fourth insulating layer 124 has a thickness such that one surface of the fourth insulating layer 124 and one surface of the fourth metal filler 114 can be positioned in the same line when the third insulating layer 124 is laminated on the third insulating layer 123 .

The fifth insulating layer 125 may be formed on the other surface of the first insulating layer 121 and may be formed so that the other surface of the fifth insulating layer 125 and the other surface of the fifth metal filler 115 are located on the same line. For example, the fifth insulating layer 125 may be formed with an opening through which the fifth metal filler 115 is inserted. The fifth insulating layer 125 may be stacked on the other surface of the first insulating layer 121 by inserting a fifth metal filler 115 into the opening. The fifth insulating layer 125 has a thickness that allows the other surface of the fifth insulating layer 125 and the other surface of the fifth metal filler 115 to be located on the same line when the first insulating layer 125 is laminated on the first insulating layer 121 .

The fourth insulating layer 124 and the fifth insulating layer 125 according to the embodiment of the present invention may be chemically-plated materials. For example, the fourth insulating layer 124 and the fifth insulating layer 125 may be ABF (Ajinomoto Build-up Film). However, the materials of the fourth insulating layer 124 and the fifth insulating layer 125 are not limited to ABF, and any of insulating materials capable of chemical plating can be employed.

Referring to FIG. 37, a fifth plating layer 145 and a sixth plating layer 146 may be formed.

First, a fifth seed layer 135 and a sixth seed layer 136 may be formed. The fifth seed layer 135 may be formed on one surface of the fourth insulating layer 124 and the fourth metal filler 114. The sixth seed layer 136 may be formed on the other surface of the fifth insulating layer 125 and the fifth metal filler 115. The fifth seed layer 135 and the sixth seed layer 136 may be formed by an electroless plating method. For example, the fifth seed layer 135 and the sixth seed layer 136 may be formed by a chemical plating method. The fifth seed layer 135 and the sixth seed layer 136 may be formed thinly by PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition) method.

The fifth plating layer 145 may be formed on one surface of the fifth seed layer 135. The sixth plating layer 146 may be formed on the other surface of the sixth seed layer 136. The fifth plating layer 145 and the sixth plating layer 146 may be formed by an electrolytic plating method. The fifth seed layer 135, the sixth seed layer 136, the fifth plating layer 145, and the sixth plating layer 146 may be formed of copper. However, the material of the fifth seed layer 135, the sixth seed layer 136, the fifth plating layer 145, and the sixth plating layer 146 is not limited to copper, and may be a conductive metal The present invention is not limited thereto.

Referring to FIG. 38, a fifth etching resist 235 may be formed on one surface of the fifth plating layer 145. A sixth etching resist 236 may be formed on the other surface of the sixth plating layer 146.

The fifth etching resist 235 may be patterned so as to exist later only in the region where the fifth circuit layer (155 in FIG. 39) is to be formed. For example, a fifth etch resist 235 may be patterned to reside in the upper region of the fourth metal filler 114.

The sixth etching resist 236 may be patterned so as to be present only in a region where a sixth circuit layer (156 in FIG. 39) is to be formed later. For example, the sixth etching resist 236 may be patterned to be present in the lower region of the fifth metal filler 115.

Referring to FIG. 39, a fifth circuit layer 155 and a sixth circuit layer 156 may be formed.

The fifth circuit layer 155 may be formed by performing etching on the fifth plating layer 145 and the fifth seed layer 135 of the region exposed by the fifth etching resist 235. [ Thereafter, the fifth etching resist 235 can be removed. One surface of the fifth circuit layer 155 thus formed may be electrically connected to an external electronic component (not shown) or a substrate (not shown) to be mounted later. The other surface of the fifth circuit layer 155 may be electrically connected to the fourth metal filler 114.

The sixth circuit layer 156 may be formed by performing etching on the sixth plating layer 146 and the sixth seed layer 136 of the region exposed by the sixth etching resist 236. [ Thereafter, the sixth etching resist 236 can be removed. One surface of the sixth circuit layer 156 thus formed may be electrically connected to the fifth metal pillar 115. The other surface of the sixth circuit layer 156 may be electrically connected to an external electronic component (not shown) or a substrate (not shown) to be mounted later.

Referring to FIG. 40, a first solder resist layer 161 and a second solder resist layer 162 may be formed.

The first solder resist layer 161 and the second solder resist layer 162 are formed on the printed circuit board 300 according to the embodiment of the present invention when external electronic components (not shown) or a substrate (not shown) The fifth circuit layer 155, and the sixth circuit layer 156, as shown in FIG.

The first solder resist layer 161 may be formed on one side of the fourth insulating layer 124. The first solder resist layer 161 may be formed with an opening exposing the connection pad of the fifth circuit layer 155.

The second solder resist layer 162 may be formed on the other surface of the fifth insulating layer 125. The second solder resist layer 162 may be formed with an opening exposing the connection pad of the sixth circuit layer 156.

Here, the connection pads of the fifth circuit layer 155 and the sixth circuit layer 156 may be constituent parts electrically connected to external electronic components (not shown) or a substrate (not shown).

In the embodiments of the present invention, a printed circuit board having a six-layer structure and a method of manufacturing the same are described, but the present invention is not limited thereto. That is, a printed circuit board having an even number of circuit layers as well as a six-layer structure can be manufactured from the printed circuit board and the manufacturing method thereof according to the embodiment of the present invention.

In the method of manufacturing a printed circuit board and a printed circuit board according to an embodiment of the present invention, the formation of the via hole and the polishing step can be omitted by forming the metal filler. Omission of the via hole forming or polishing process may reduce the stress applied to the printed circuit board. In addition, by forming the metal filler using the photosensitive resist, the interlayer spacing can be formed to be the same. Further, the printed circuit board and the printed circuit board manufacturing method according to the embodiment of the present invention can easily manufacture various numbers of layers The core-less substrate can be manufactured.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the same is by way of illustration and example only and is not to be construed as limiting the present invention. It is obvious that the modification or improvement is possible.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

100, 300: printed circuit board 111: first metal filler
112: second metal filler 113: third metal filler
114: fourth metal filler 115: fifth metal filler
121: first insulation layer 122: second insulation layer
123: third insulating layer 124: fourth insulating layer
125: fifth insulating layer 131: first seed layer
132: second seed layer 133: third seed layer
134: fourth seed layer 135: fifth seed layer
136: sixth seed layer 141: first plating layer
142: second plating layer 143: third plating layer
144: fourth plated layer 145: fifth plated layer
146: sixth plating layer 151: first circuit layer
152: second circuit layer 153: third circuit layer
154: fourth circuit layer 155: fifth circuit layer
156: sixth circuit layer 161: first solder resist layer
162: second solder resist layer 210: carrier substrate
211: Insulation material 212: Copper foil
221: first plating resist 222: second plating resist
223: third plating resist 224: fourth plating resist
231: first etching resist 232: second etching resist
233: Third etching resist 234: Fourth etching resist
235: Fifth etching resist 236: Sixth etching resist
A, B: buildup layer

Claims (21)

Insulating layer;
A plurality of metal pillars in which a plurality of the insulating layers are stacked; And
A circuit layer formed on the insulating layer and formed between the stacked metal pillars;
And a printed circuit board.
The method according to claim 1,
Wherein the circuit layer is formed on the metal pillar and is further formed on at least one of the one surface and the other surface of the insulating layer.
The method of claim 2,
And a solder resist layer formed on at least one of the one surface and the other surface of the insulating layer and including an opening exposing the circuit layer.
The method according to claim 1,
Wherein the insulating layer is formed of ABF (Ajinomoto Build-up Film).
The method according to claim 1,
Wherein one or more inner layer circuit layers are further formed inside the insulating layer.
Preparing a carrier substrate;
Forming a first metal filler on the carrier substrate;
Forming a first insulation layer on the carrier substrate, the first insulation layer being formed to expose one surface of the first metal filler;
Removing the carrier substrate; And
Forming a first circuit layer on at least one side of the first insulating layer and the first metal filler;
≪ / RTI >
The method of claim 6,
Wherein the carrier substrate includes an insulating resin and a copper foil formed on at least one surface of the insulating resin.
The method of claim 6,
Wherein forming the metal filler comprises:
Forming a first photosensitive resist on at least one surface of the carrier substrate, the first photosensitive resist including a first opening;
Filling the first opening with a conductive metal to form the first metal filler; And
Removing the first photosensitive resist;
≪ / RTI >
The method of claim 6,
The forming of the first insulating layer may include:
Preparing a first insulating layer having an opening through which the first metal filler is inserted; And
Stacking the first insulating layer on the carrier substrate such that the first metal filler is inserted into the opening;
Wherein one surface of the first insulating layer laminated on the carrier substrate and one surface of the first metal pillar are located on the same line.
The method of claim 6,
Wherein forming the first circuit layer comprises:
Forming a first plating layer on the first insulating layer;
Forming a first etch resist patterned on the first plating layer and patterned to be located in a region corresponding to the first circuit layer;
Etching the first plating layer to form the first circuit layer; And
Removing the first etch resist;
≪ / RTI >
The method of claim 6,
Before the step of forming the first plating layer,
And forming a first seed layer on the first insulating layer by an electroless plating method.
The method of claim 10,
In the step of forming the first plating layer,
Wherein the first plating layer is formed by an electrolytic plating method.
The method of claim 6,
After the step of forming the first circuit layer,
Further comprising forming a first solder resist formed on the first insulating layer and having an opening to expose the first circuit layer.
The method of claim 6,
After the step of forming the first circuit layer,
Forming a second metal filler on the first circuit layer;
Forming a second insulating layer on the first insulating layer and exposing one surface or the other surface of the second metal filler; And
Forming a second circuit layer on the second insulating layer and the second metal filler;
Further comprising the steps of:
15. The method of claim 14,
Wherein forming the second metal filler comprises:
Forming a second photosensitive resist on the first insulating layer, the second photosensitive resist including a second opening exposing the first circuit layer;
Filling the second opening with a conductive metal to form the second metal filler; And
Removing the second photosensitive resist;
Further comprising the steps of:
15. The method of claim 14,
Wherein forming the second insulating layer comprises:
Preparing a second insulating layer having an opening through which the second metal filler is inserted; And
Stacking the second insulating layer on the first insulating layer such that the second metal filler is inserted into the opening;
Wherein one surface of the second insulating layer laminated on the first insulating layer and one surface of the second metal filler are located on the same line.
15. The method of claim 14,
Wherein forming the second circuit layer comprises:
Forming a second plating layer on the second insulating layer;
Forming a second etch resist patterned on the second plating layer and patterned to be located in a region corresponding to the second circuit layer;
Etching the second plating layer to form a second circuit layer; And
Removing the second etch resist;
≪ / RTI >
15. The method of claim 14,
Before the step of forming the second plating layer,
And forming a second seed layer on the second insulating layer by an electroless plating method.
18. The method of claim 17,
In the step of forming the second plating layer,
Wherein the second plating layer is formed by an electrolytic plating method.
15. The method of claim 14,
After the step of forming the second circuit layer,
Further comprising forming a second solder resist formed on the second insulating layer and having an opening to expose the second circuit layer.
The method of claim 6,
Wherein at least one inner layer circuit layer is further formed inside the first insulating layer.

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