US20130277737A1

US20130277737A1 - Semiconductor device and method of manufacturing the same

Info

Publication number: US20130277737A1
Application number: US13/917,612
Authority: US
Inventors: Wan Soo Kim
Original assignee: SK Hynix Inc
Current assignee: SK Hynix Inc
Priority date: 2010-07-01
Filing date: 2013-06-13
Publication date: 2013-10-24
Also published as: KR101061296B1; US8486819B2; US20120001258A1

Abstract

A semiconductor device includes a gate metal buried within a trench included in a semiconductor substrate including an active region defined by an isolation layer, a spacer pattern disposed on an upper portion of a sidewall of a gate metal, a first gate oxide layer disposed between the spacer pattern and the trench, a second gate oxide layer disposed below the first gate oxide layer and the gate metal, and a junction region disposed in the active region to overlap the first gate oxide layer.

Description

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority to Korean patent application number 10-2010-0063421 filed on 01 Jul. 2010, which is incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Technical Field
The present invention relates to a semiconductor device with improved gate refresh characteristics and a method of fabricating the same.
2. Related Art
With the high integration degree of semiconductor devices, the size of an active region and a channel length of a transistor formed in the active region are reduced. As the channel length of a transistor is reduced, short channel effect or source/drain punch-through occurs, which negatively influences the electric field or electric potential in the channel of the transistor. For example, when a short channel effect is generated in an access transistor adapted to memory cells of dynamic random access memories (DRAMs), a threshold voltage of the DRAM cells is reduced and a leakage current increases, thereby degrading the refresh characteristics of DRAMs. Thus, in order to suppress the short channel effect, a method of increasing the gate channel length of the device formed on a substrate has been suggested. For example, even if the memory cells of a DRAM device are scaled down to a very small size, a transistor having a recessed channel retains fairly good refresh characteristics.
Hereinafter, a method of manufacturing a transistor having a recessed channel in the related art will be described. A source/drain region is formed by implanting impurities into a substrate. A mask opening a portion of the substrate in which a recessed channel is to be formed is formed and the exposed portion of the substrate is etched using the mask to form a trench in the substrate. Subsequently, a gate oxide layer is formed on an inner wall of the trench. At this time, the gate oxide layer includes a high dielectric (high-k) material layer such as a silicon oxide layer, a hafnium oxide layer and a hafnium silicon oxide layer. A gate conductive layer fills the trench. The gate conductive layer includes a stacking structure of polysilicon/metal or metal/polysilicon/metal, which has a lower resistance characteristic than polysilicon while having a property similar to polysilicon. The gate conductive layer is isotropically etched using a gate mask to form a gate electrode, thereby completing a transistor having the gate electrode and the source/drain.
Thus, as the integrity degree of the semiconductor device rapidly increases, in order to reduce a gate leakage current and power consumption, a high dielectric material layer is used as the gate oxide layer and a stacking structure, which includes a polysilicon layer on a metal layer, is formed on the high dielectric material layer as the gate conductive layer. However, when a transistor having a recessed channel is formed by the related art, due to low etch selectivity between the metal layer used as a gate conductive layer and the high dielectric material layer, when the high dielectric layer is etched to form the gate electrode, silicon substrate is removed.
On the other hand, as integrity of the semiconductor device increases, the thickness of the gate oxide layer is reduced to improve controllability of the gate. As a result, an electric field is concentrated at an area between the gates thus causing gate induced drain leakage (GIDL). That is, since an overlap between the gate and a junction region is increased by bridges between a word line and a bit line or between word lines, GIDL current is increased by direct tunneling between the gate electrode and the drain region. Such a GIDL current seriously degrades a semiconductor device, such as DRAM, having a recessed channel.

SUMMARY

The present invention is directed to providing a semiconductor device capable of preventing the degradation of refresh characteristics due to GIDL caused by concentration of an electric field in an overlap area between gates, which occurs when reducing the thickness of a gate oxide layer to improve controllability of a gate as the integrity of the semiconductor device increases, and a method of manufacturing the same.
According to one aspect of an exemplary embodiment, a semiconductor device includes a gate metal buried within a trench in a semiconductor substrate including an active region defined by a device isolation layer, a spacer pattern disposed on an upper portion of a sidewall of the gate metal, a first gate oxide layer disposed between the spacer pattern and the trench, a second gate oxide layer disposed below the first gate oxide layer and the gate metal, and a junction region disposed in the active region to overlap the first gate oxide layer.
The first gate oxide layer may have a thicker thickness than the second gate oxide layer.
The first gate oxide layer may have the thickness of 70 Åto 100 Å.
The second oxide layer may have a thickness of 50 Å to 60 Å.
The junction region and the gate metal may be spaced by the spacer pattern and the first gate oxide layer.
According to another aspect of another exemplary embodiment, a semiconductor device includes a first buried gate formed at a first level in a substrate; a second buried gate extending from the first buried gate and formed at a second level in the substrate, the second level being higher than the first level; a junction region formed at a side of the second buried gate at the second level; a spacer pattern formed between the junction region and the second buried gate at the second level; and a first gate oxide layer formed between the spacer pattern and the junction region, wherein a thickness and a material of the spacer pattern and the first gate oxide layer are configured to inhibit leakage between the buried gate and the junction region.
The device further comprising a second gate oxide layer formed between the first buried gate and the substrate, wherein the first gate oxide layer is formed to be thicker than the second gate oxide layer.
According to another aspect of another exemplary embodiment, a method of manufacturing a semiconductor device includes forming a trench in a semiconductor substrate including an active region defined by a device isolation layer, forming an insulating layer on an inner surface of the trench, forming a sacrificial metal pattern on the insulating layer to be filled within a lower portion of the trench, forming a spacer pattern at a sidewall of the trench on the sacrificial metal pattern, removing the sacrificial metal pattern, removing the insulating layer using the spacer pattern as a mask to form a first gate oxide layer, forming a second gate oxide layer on a surface of the trench from which the sacrificial metal pattern is removed, forming a gate metal on the second gate oxide layer to overlap the spacer pattern, and forming a junction region in the active region to overlap the first gate oxide layer by performing an ion implantation process.
The forming the trench may include forming a hard mask pattern on the semiconductor substrate and etching the semiconductor substrate using the hard mask pattern as a mask.
The forming the insulating layer on the inner surface of the trench may include oxidizing a surface of the trench.
The forming the insulating layer on the inner surface of the trench may include forming an oxide layer having a thickness of 70 Å to 100 Å.
The forming the sacrificial metal pattern may include forming a sacrificial metal layer on the insulating layer and performing an etching back process for the sacrificial metal layer by taking a channel region, which is to be formed within the semiconductor substrate, into consideration.
The forming the spacer pattern may include forming a spacer insulating layer on the sacrificial metal pattern and the insulating layer and performing an etching back process for the spacer insulating layer.
The removing the insulating layer may include performing a cleaning process for the insulating layer.
The forming the second oxide layer may include oxidizing a surface of the trench exposed by the spacer pattern.
The forming the second oxide layer may include forming an oxide layer having a thickness of 50 Å to 60 Å.
The method may further include forming an insulating layer on the gate metal after forming the gate metal.
According to another aspect of another exemplary embodiment, a method of manufacturing a semiconductor device includes forming a trench in a substrate, wherein the trench includes a lower part located at a first level and an upper part located at a second level, forming an insulating layer over a surface of the trench at the first level and at the second level, forming a sacrificial metal pattern in the trench at the first level, forming a spacer pattern at a sidewall of the trench at the second level, removing the sacrificial metal pattern, removing the insulating layer at the first level and allowing the insulating layer at the second level to remain to form a first gate oxide layer, forming a gate electrode in the trench so as to extend from the first level to the second level and forming a junction region in the substrate at a side of the first gate oxide layer at the second level.
These and other features, aspects, and embodiments are described below in the section entitled “DESCRIPTION OF EXEMPLARY EMBODIMENT.”

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features, and other advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the present invention; and

FIGS. 2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

DESCRIPTION OF EXEMPLARY EMBODIMENT

Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of exemplary embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated herein, but may include deviations in shapes that result, for example, from manufacturing. In the drawings, lengths and sizes of layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like elements. It is also understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present.
Hereinafter, exemplary embodiments of the present invention will be described with reference to accompanying drawings.
Referring to FIG. 1, a semiconductor device according to an exemplary embodiment of the present invention includes a gate metal 118 buried in a trench 106, which is formed in a semiconductor substrate including an active region defined by a device isolation layer 102; a spacer pattern 114 disposed over an upper portion of a sidewall of the gate metal 118; a first gate oxide layer 110 a disposed between the spacer pattern 114 and a sidewall of the trench 106, a second gate oxide layer 116 disposed below the first gate oxide layer 110 a and the gate metal 118; and a junction region 122 disposed in the active region to overlap the first gate oxide layer 110 a.
The semiconductor device further includes an insulating layer 120 disposed over the gate metal 118 and a hard mask pattern 108 defining the trench 106. Here, a thickness of the first oxide layer 110 a may be thicker than that of the second gate oxide layer 116. Specifically, the first gate oxide layer 110 a may have a thickness of 70 Å to 100 Å and the second gate oxide layer 116 may have a thickness of 50 Å to 60 Å.
Hereinafter, a method of manufacturing a semiconductor device having the above-described structure according to an exemplary embodiment of the present invention will be described.
Referring to FIG. 2A, a hard mask pattern 108 is formed on a semiconductor substrate 100, which includes an active region 104 defined by a device isolation layer 102. The semiconductor substrate 100 is etched using the hard mask pattern 108 as a mask to form a trench 106. The trench 106 may be a region where a gate is to be formed.
Referring to FIG. 2B, an insulating layer 110 is formed over the surface of the trench 106. Here, the insulating layer 110 may be formed to a thickness of 70 Å to 100 Å.
Referring to FIG. 2C, a sacrificial metal layer is formed on the semiconductor substrate 100 including the trench 106 and then an etching back process is performed to form a sacrificial metal pattern 112 in a lower portion of the trench 106. Here, the sacrificial metal pattern 112 defines a channel region.
Referring to FIG. 2D, a spacer insulating layer is formed on the sacrificial metal pattern 112, the insulating layer 110, and the hard mask pattern 108 and an etching back process for the spacer insulating layer is performed to form a spacer pattern 114 only on sidewalls of the insulating layer 110 and the hard mask pattern 108. The spacer pattern 114 prevents a gate oxide layer from being damaged in the following process.
Referring to FIG. 2E, the sacrificial metal pattern 112, which fills the lower portion of the trench 106, is removed. A cleaning process is performed so that the insulating layer under the sacrificial metal pattern 112 is also removed, thus exposing a surface of the trench 106. As a result, a first gate oxide layer 110 a is obtained along an upper inner wall of the trench. As described above, the first gate oxide layer 110 a can prevent gate induced drain leakage (GIDL) current due to a direct tunneling between a gate electrode and a drain region.
Referring to FIG. 2F, a second gate oxide layer 116 is formed over the surface of the trench 106 exposed by removing the first oxide layer 110 a. Here, the second gate oxide layer 116 may be formed by performing an oxidation process on the semiconductor substrate 100. The second gate oxide layer 116 may have a shallower thickness than the first gate oxide layer 110 a and may have a thickness of 50 Å to 60 Å. The area where the second gate oxide layer 116 is formed is an area in which a channel is to be formed. Accordingly, the second gate oxide layer 116 is thinly formed to easily control a gate.
Referring to FIG. 2G, a gate conductive layer is formed within the trench 106 and then an etching back process is performed to form a gate 118 buried in the trench 106. The gate 118 may extend over the spacer pattern 114.
Referring to FIG. 2H, an insulating layer 120 is formed in the trench 106 to be over the gate 118 and an ion implantation process is performed on the semiconductor substrate 100 to form a junction region 122. Here, the junction region 122 may be formed at such a level that it overlaps with the space pattern 114 and the first gate oxide layer 110 a. That is, the junction region 122 is spaced apart from the gate 118 by the thicknesses of the spacer pattern 114 and the first gate oxide layer 110 a to suppress the direct tunneling effect in an “A” area, thereby reducing GIDL.
As described above, according to an exemplary embodiment of the present invention, the gate oxide layer is thickly formed in an overlapping area between the gate and the junction to reduce GIDL, thereby improving refresh characteristics and reducing parasitic capacitance to improve characteristics of the semiconductor device.
The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the embodiment described herein. Nor is the invention limited to any specific type of semiconductor device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.

Claims

1.-11. (canceled)

12. A semiconductor device, comprising:

a gate metal buried within a trench formed in a semiconductor substrate, the semiconductor including an active region defined by a device isolation layer;

a spacer pattern formed over an upper portion of the gate metal and extending upward from a sidewall of the gate metal;

a first gate oxide layer disposed between the spacer pattern and a sidewall of the trench;

a second gate oxide layer extending from the bottom of the first gate oxide layer to be formed under the gate metal; and

a junction region formed at a side of the gate metal while having the first gate oxide layer interposed therebetween.

13. The semiconductor device of claim 12, wherein the first gate oxide layer has a thicker thickness than the second gate oxide layer.

14. The semiconductor device of claim 12, wherein the first gate oxide layer has the thickness of 70 Å to 100 Å.

15. The semiconductor device of claim 12, wherein the second oxide layer has a thickness of 50 Å to 60 Å.

16. The semiconductor device of claim 12, wherein the junction region and the gate metal is spaced apart by the spacer pattern and the first gate oxide layer.

17. A semiconductor device, comprising:

a first buried gate formed at a first level in a substrate;

a second buried gate extending from the first buried gate and formed at a second level in the substrate, the second level being higher than the first level;

a junction region formed at a side of the second buried gate at the second level;

a spacer pattern formed between the junction region and the second buried gate at the second level; and

a first gate oxide layer formed between the spacer pattern and the junction region,

wherein a thickness and a material of the spacer pattern and the first gate oxide layer are configured to inhibit leakage between the buried gate and the junction region.

18. The semiconductor device of claim 17, the device further comprising a second gate oxide layer formed between the first buried gate and the substrate,

wherein the first gate oxide layer is formed to be thicker than the second gate oxide layer.