US20130191568A1 - Operating m-phy based communications over universal serial bus (usb) interface, and related cables, connectors, systems and methods - Google Patents

Operating m-phy based communications over universal serial bus (usb) interface, and related cables, connectors, systems and methods Download PDF

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Publication number
US20130191568A1
US20130191568A1 US13/356,521 US201213356521A US2013191568A1 US 20130191568 A1 US20130191568 A1 US 20130191568A1 US 201213356521 A US201213356521 A US 201213356521A US 2013191568 A1 US2013191568 A1 US 2013191568A1
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Prior art keywords
phy
pin
usb
pins
data path
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US13/356,521
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English (en)
Inventor
Yuval Corey Hershko
Yoram Rimoni
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Qualcomm Inc
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Qualcomm Inc
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Priority to US13/356,521 priority Critical patent/US20130191568A1/en
Assigned to QUALCOMM INCORPORATED reassignment QUALCOMM INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HERSHKO, Yuval Corey, RIMONI, YORAM
Priority to TW102102578A priority patent/TW201344453A/zh
Priority to JP2014553541A priority patent/JP2015508194A/ja
Priority to EP13705290.8A priority patent/EP2807571A1/en
Priority to PCT/US2013/022795 priority patent/WO2013112620A1/en
Priority to CN201380006200.1A priority patent/CN104067251A/zh
Publication of US20130191568A1 publication Critical patent/US20130191568A1/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation

Definitions

  • the technology of the present disclosure relates generally to communications interfaces used for communications between electronic devices.
  • the MIPI® Alliance has recently proposed the M-PHY SM physical layer standard defining a data rate of 10 Kbps to 5.8 Gbps per lane.
  • the M-PHY standard is optimized for mobile applications, such as cameras, displays for mobile terminals, smart phones, and the like.
  • the M-PHY standard provides a serial interface technology with high bandwidth capabilities
  • the M-PHY specification deliberately avoids connector definitions and advocates for a permanent trace based connection between devices. Permanent trace based connections eliminates the flexibility of user desired connections.
  • Embodiments disclosed in the detailed description include operating the M-PHY communications over a universal serial bus (USB) interface, and related cables, connectors, systems, and methods.
  • embodiments of the present disclosure take the M-PHY standard compliant signals and direct them through a USB compliant connector (and optionally cable) so as to allow two M-PHY standard compliant devices having USB connectors to communicate.
  • an electronic device is configured to operate using the M-PHY standard.
  • the electronic device comprises a communications interface having a plurality of data paths conforming to the M-PHY standard and a USB connector having a plurality of pins.
  • the plurality of pins of the USB connector comprises a first receive pin electrically coupled to a M-PHY RXDN data path of the communications interface, and a second receive pin electrically coupled to a M-PHY RXDP data path of the communications interface.
  • the plurality of pins also comprises a first transmit pin electrically coupled to a M-PHY TXDN data path of the communications interface, and a second transmit pin electrically coupled to a M-PHY TXDP data path of the communications interface.
  • a method of connecting an electronic device, configured to operate using the M-PHY standard, to a second electronic device comprises providing a plurality of data paths conforming to the M-PHY standard and providing a USB connector having a plurality of pins.
  • the method comprises electrically coupling a first receive pin to a M-PHY RXDN data path and electrically coupling a second receive pin to a M-PHY RXDP data path.
  • the method comprises electrically coupling a first transmit pin to a M-PHY TXDN data path of the communications interface and electrically coupling a second transmit pin to a M-PHY TXDP data path of the communications interface.
  • FIG. 1A is a block diagram of an exemplary conventional direct mated universal serial bus (USB) connection between a host and other device;
  • USB universal serial bus
  • FIG. 1B is a block diagram of an exemplary conventional cable mated USB connection between a host and other device
  • FIG. 1C is a perspective view of a conventional USB Standard-A connector
  • FIG. 2 is a table illustrating an exemplary mapping of USB pins of a USB connector to a M-PHY data path for a M-PHY standard
  • FIG. 3 is a block diagram of an exemplary embodiment of a conventional M-PHY single lane signal path layout for connection of M-PHY standard compliant electronic devices;
  • FIG. 4 is a flowchart illustrating an exemplary process for mapping USB pins of a USB connector to M-PHY standard data paths
  • FIG. 5 illustrates an exemplary embodiment of a particular configuration of a mapping of USB pins of a USB connector to M-PHY standard signals
  • FIG. 6 illustrates an alternate embodiment of a particular configuration of a mapping of USB pins of a USB connector to M-PHY standard signals
  • FIG. 7 illustrates an alternate embodiment of a particular configuration of a mapping of USB pins of a USB connector to M-PHY standard signals
  • FIG. 8 is a block diagram of an exemplary processor-based system that can include a USB connector having USB pins mapped to a M-PHY standard data paths.
  • Embodiments disclosed in the detailed description include operating the M-PHY communications over a universal serial bus (USB) interface, and related devices, systems, and methods.
  • embodiments of the present disclosure take the M-PHY standard compliant signals and direct them through a USB compliant connector (and optionally cable) so as to allow two M-PHY standard compliant devices having USB connectors to communicate.
  • an electronic device is configured to operate using the M-PHY standard.
  • the electronic device comprises a communications interface having a plurality of data paths conforming to the M-PHY standard and a USB connector having a plurality of pins.
  • the plurality of pins of the USB connector comprises a first receive pin electrically coupled to a M-PHY RXDN data path of the communications interface, and a second receive pin electrically coupled to a M-PHY RXDP data path of the communications interface.
  • the plurality of pins also comprises a first transmit pin electrically coupled to a M-PHY TXDN data path of the communications interface, and a second transmit pin electrically coupled to a M-PHY TXDP data path of the communications interface.
  • the MIPI® Alliance has proposed the M-PHY standard, which is a physical layer protocol detailing how devices communicate with one another.
  • M-PHY is a physical layer protocol detailing how devices communicate with one another.
  • the MIPI® Alliance has to date, not defined or constrained the M-PHY standard to a particular connector type that complies with the standard, leaving the design of the physical connectors to the entities deploying products in this space.
  • an existing connector is adapted herein to satisfy the signal integrity and other requirements of the MIPI® Alliance M-PHY standard, namely the USB connector currently used for USB protocol compliant devices.
  • the USB connector that is adapted to be used for the MIPI® Alliance M-PHY standard standard can be a USB 3.0 connector.
  • USB is an industry standard introduced in the mid 1990s. USB 3.0 was subsequently introduced in 2008. More information on the conventional USB 3.0 standard and connectors can be found at www.usb.org/developers/docs/ and in particular, in the Universal Serial Bus Revision 3.0 Specification published on the website, the contents of which are hereby incorporated herein by reference in its entirety. Before discussing the embodiments of adapting the USB connector to the M-PHY standard, USB connectors are first discussed with regard to FIGS. 1A-1C .
  • FIG. 1A is an exemplary block diagram of a conventional USB connection 10 .
  • the USB connection 10 is USB 3.0 compliant and includes a host 12 and a device 14 .
  • the device 14 is directly plugged into the host 12 through a mated connector 16 .
  • the host 12 includes a transmitter with an amplifier 18 , filtering capacitors 20 , and a receiver with amplifier 22 .
  • the device 14 similarly has a receiver with amplifier 24 , a transmitter with amplifier 26 and filtering capacitors 28 .
  • the host transmitter sends TXP and TXN signals to the device 14 , which treats the incoming signals as RXP and RXN signals respectively.
  • the device transmitter sends TXP and TXN signals to the host 12 , which treats the incoming signals as RXP and RXN signals respectively.
  • a non-limiting example of this arrangement might be a FLASH memory stick (device 14 ) inserted into a USB port on a computer (host 12 ).
  • FIG. 1B illustrates a USB connection 10 A similar to the USB connection 10 in FIG. 1A .
  • the host 12 may include a connector 16 A
  • the device 14 includes a connector 16 B with a cable 30 extending therebetween.
  • connector 16 A may be a mated connection, with a connector on the host 12 and a connector on the cable 30
  • the connector 16 B may similarly be a mated connection, with a connector on the device 14 and a connector on the cable 30 .
  • a non-limiting example of this arrangement might be a camera (device 14 ) being plugged into a computer (host 12 ) through a USB cable (cable 30 ). While not illustrated, another possibility does exist.
  • That other possibility is a cable with a connector at one end and “hard wired” to the device at the other end.
  • An example would be a USB computer mouse, which has a cable that is hard-wired to the mouse on one end, and has a Standard-A plug on the other end.
  • FIG. 1C is a perspective view of an exemplary conventional connector plug 32 that is compliant with USB 3.0.
  • the connector plug 32 is consistent with USB 3.0 Standard-A Plug, but Standard-A receptacles, Standard-B plug and receptacle, Micro-A Plug and receptacle, Micro-B Plug and receptacle, and Micro-AB receptacle share the majority of the same features, although the Micro set of connectors do not support the pin staggering outlined below.
  • the connector plug 32 includes ten conductive elements.
  • An outer grounding shell 34 is a first conductive element, and nine pins 36 A- 36 I (collectively: pins 36 ) form the remainder of the ten conductive elements.
  • TABLE 1 As defined by the USB 3.0 standard, the names and uses of the outer grounding shell 34 and the pins 36 A- 36 I are summarized in TABLE 1 set forth below. Note that TABLE 1 is specifically set forth with reference to a Standard-A connector, although similar tables are readily available for the other connectors. Additionally, the reference number for the present disclosure is included in TABLE 1 set forth below.
  • the arrangement of the outer grounding shell 34 and pins 36 A- 36 I (at least in Standard-A plugs and receptacles), and, in particular, the physical geometries associated with the outer grounding shell 34 and pins 36 A- 36 I, causes a particular mating sequence when the connector plug 32 is mated. That is, when the connector plug 32 is inserted into a receptacle, the outer grounding shell 34 is exterior to the pins 36 A- 36 I and extends further than any of the pins 36 A- 36 I, and thus makes the first electrical connection with its counterpart in the receptacle. Subsequently, the pins 36 A and 36 D make an electrical connection because they extend further forward than any other pin 36 .
  • pins 36 B and 36 C make the third round of electrical connections, and pins 36 E- 36 I make the last round of electrical connections.
  • This sequence is summarized in the “Mating Sequence” column in Table 1. The present disclosure allows for use of this mating sequence as explained in greater detail below.
  • USB standard is several years old, the industry has had time to develop a standardized connector plug 32 (illustrated in FIG. 1C ).
  • USB 3.0 compliant connectors There are numerous manufacturers capable of manufacturing USB 3.0 compliant connectors according to the well established form factor. Likewise, stress and bend tolerances and other fatigue related tolerances and the like are well understood by those who use such connectors. Many specific definitions and requirements are set forth in the USB specification, chapter 5, and the industry has acclimated to meeting these definitions and requirements.
  • the present disclosure takes advantage of the familiarity with which industry treats the USB 3.0 connectors and particularly with plug 32 (and corresponding receptacles) and proposes repurposing such connectors for use with M-PHY standard compliant devices.
  • use of the existing USB 3.0 connector in an M-PHY standard compliant device allows all the expertise and familiarity the industry has with the USB 3.0 connector to be leveraged into ready acceptance of its use with M-PHY standard compliant devices.
  • the well-developed manufacturing base allows for ease in securing the connectors for incorporation into M-PHY standard compliant devices.
  • the chart 40 illustrates the mapping of the M-PHY standard compliant pin names to the corresponding USB 3.0 signal.
  • FIG. 2 illustrates that pins 36 E, 36 F, 36 H, and 36 I are repurposed from their respective USB signal use to a corresponding M-PHY signal use.
  • pin 36 E which was used for the SSRX ⁇ signal is used for the RXDN signal 38 E; the SSRX+ signal is used for the RXDP signal 38 F; the SSTX ⁇ signal is used for the TXDN signal 38 H; and the SSTX+ signal is used for the TXDP signal 38 I.
  • the pins 36 E, 36 F, 36 H, and 36 I are used for a receiver differential pair and transmitter differential pair as noted.
  • FIG. 3 An exemplary conventional M-PHY signal path layout 42 with pin requirements is provided with reference to FIG. 3 . That is, a first electronic device 44 is connected to a second electronic device 46 .
  • the first electronic device 44 can include a control system or processor (discussed below in regard to FIG. 8 ), which may, through appropriate device drivers, control the signal lanes 48 A, 48 H of a communications interface (sometimes referred to herein as a means for interfacing) according to the M-PHY standard.
  • the signal lane 48 A is the lane through which the first electronic device 44 transmits data to the second electronic device 46 through the TXDP and TXDN pins 50 A, 50 B to RXDP and RXDN pins 52 A, 52 B.
  • the second electronic device 46 transmits data to the first electronic device 44 through the TXDP and TXDN pins 54 A, 54 B to RXDP and RXDN pins 56 A, 56 B.
  • Each electronic device 44 , 46 has its own respective transmitter M-TX 58 A, 58 B and receiver M-RX 60 A, 60 B controlled by respective lane management module 62 A, 62 B.
  • the lane management modules 62 A, 62 B may be hardware or software or a mix of the two as desired and may communicate with the control system via links 70 A, 70 B.
  • the pins 50 A, 50 B, 56 A, 56 B may be in a single M-Port 64 , while the pins 52 A, 52 B, 54 A, and 54 B may be in a second M-Port 66 .
  • the lane management module 62 A may communicate with the transmitter 58 A through a peripheral interchange format (PIF) link 68 A and with the receiver 60 A through a PIF link 68 B.
  • PIF peripheral interchange format
  • the lane management module 62 B may communicate with the transmitter 58 B through a PIF link 68 C and the receiver 60 B through a PIF link 68 D.
  • the lane management modules 62 a , 62 B, the links 70 A, 70 B, the transmitters 58 A, 60 B, receivers 58 B, 60 A, and PIF links 68 A- 68 D are set forth in the M-PHY standard, and the interested reader is directed thereto for more information regarding these elements.
  • the first electronic device 44 is directly connected to the second electronic device 46 . While not explicitly illustrated, it should be appreciated that the direct connection could be replaced by a connector, cable, or combination.
  • the signals and lane management elements are defined by the M-PHY standard, but the arrangement of the pins and any connectors is left undefined. However, as noted with reference to FIG.
  • a USB connector 32 may be repurposed by mapping the pins 36 E, 36 F, 36 H, and 36 I to the RXDN 38 E, RXDP 38 F, TXDN 38 H, and TXDP 38 I respectively without requiring any physical changes to the connector 32 .
  • the connector 32 may sometimes be referred to herein as a means for connecting.
  • FIG. 4 a flow chart is provided illustrating a method of connecting a first electronic device, such as electronic device 44 , configured to operating using a M-PHY standard to a second electronic device, such as electronic device 46 through a mated connection, a cable with mated connectors or the like.
  • the method provides an electronic device (block 100 ) and forms a plurality of data paths in the electronic device, wherein each path conforms to M-PHY standard. (block 102 ).
  • the method provides a USB connector (e.g., a plug or a receptacle) having a plurality of pins to the electronic device (block 104 ).
  • a USB connector e.g., a plug or a receptacle
  • the USB connector is a USB plug that conforms to the USB 3.0 Standard-A with the outer grounding shell 34 and pins 36 A- 36 I described above, with reference to FIG. 1C and TABLE 1.
  • a Standard B, Micro-A, or Micro-B connector may be used without departing from the teachings of the present disclosure.
  • the method electrically couples the pins in the connector to the data paths (block 106 ).
  • the pins 36 A- 36 I are mapped by electrically coupling a first receive pin (e.g., the SSRX+) to a M-PHY RXDN data path, electrically coupling a second receive pin (e.g., the SSRX ⁇ ) to a M-PHY RXDP data path, electrically coupling a first transmit pin (e.g., the SSTX ⁇ ) to a M-PHY TXDN data path, and electrically coupling a second transmit pin (e.g., SSTX+) to a M-PHY TXDP data path.
  • a first receive pin e.g., the SSRX+
  • a second receive pin e.g., the SSRX ⁇
  • a first transmit pin e.g., the SSTX ⁇
  • a second transmit pin e.g., SSTX+
  • the electronic device may be connected to a second electronic device (e.g., second device 46 ) (block 108 ).
  • the control system associated with the connector may perform insertion detection (block 110 ) and/or provide power (block 112 ) to the second electronic device 46 .
  • USB connector plug 32 allows for insertion detection and provides the ability to supply power to the second electronic device 46 .
  • Insertion detection allows the first electronic device 44 to know when it is acceptable to send data or listen for data from the second electronic device 46 .
  • the second electronic device 46 should detect that the first electronic device 44 has been connected.
  • Other advantages may also be realized through insertion detection, and the present disclosure is not so limited.
  • providing power to the second electronic device 46 allows the designers to avoid having to provide a power cord or alternate power source for the second electronic device. There are a number of possible configurations which would allow this to happen. Three exemplary configurations using USB Standard-A connectors (plugs, receptacles and/or cables) are illustrated in FIGS. 5-7 .
  • the first electronic device 44 is considered the host device and the second electronic device 46 is considered the auxiliary device.
  • M-PHY does not make this distinction, although it is preserved in the present disclosure to facilitate the explanation.
  • pin 36 A which in the USB 3.0 standard is the VBUS signal
  • pin 36 C which in the USB 3.0 standard is the D+ signal.
  • Pins 36 B and 36 D may be used for insertion detection. Power may be supplied through the pins 36 A and 36 D.
  • pins 36 E, 36 F, 36 H, and 36 I are used for the data lanes of the M-PHY standard.
  • the pin 36 B may be connected to pin 36 D.
  • the auxiliary device 46 may detect insertion based on whether the auxiliary device 46 has power.
  • the host device 44 detects insertion by detection of DC levels.
  • the D ⁇ pin is pulled to GND potential and the D ⁇ pin in the auxiliary device is pulled to VBUS potential.
  • Trivial electronic circuitry could detect that a pin potential has changed from a floating (unconnected) value to either GND or VBUS potential. Thus, no AC signal needs to be injected and the already available DC voltages are reused.
  • This configuration allows for use of a USB 3.0 Standard A connector and is appropriate for use when it is uncertain whether the auxiliary device 46 needs to draw power.
  • both the first electronic device 44 and the second electronic device 46 can detect insertion and the first electronic device 44 can provide power as desired. Note also that the process can be effectively reversed to detect disconnection. That is, if the signals that are detected during insertion are lost, then the devices may infer disconnection.
  • FIG. 6 A second exemplary configuration is illustrated in FIG. 6 .
  • power is supplied from the host device (first electronic device 44 ) to the auxiliary device (second electronic device 16 ) through the pins 36 A and 36 D.
  • auxiliary device 46 pins 36 B and 36 C are connected to one another.
  • the host device 44 may send a signal, which may just be a DC voltage reference, on pin 36 B and, if the signal is received by the host device 44 at pin 36 C, the host device 44 ascertains insertion.
  • the auxiliary device 16 ascertains insertion by the reception of power from pins 36 A and 36 D. This configuration is likewise well suited for use with a USB 3.0 Standard A connector.
  • FIG. 7 A third exemplary configuration is illustrated in FIG. 7 .
  • Power is again supplied from the host device (first electronic device 44 ) to the auxiliary device (second electronic device 36 ) through the pins 36 A and 36 D.
  • Pins 36 B and 36 C may be used to support an additional data lane (either in the forward or reverse direction) or a shared clock as needed or desired.
  • the auxiliary device 46 sinks power.
  • the power sinking may be a requirement for the auxiliary device 46 to draw a minimal current for a specific period. (e.g., must draw a current of no less than 10 mA for no less than 2 seconds after power is applied).
  • the host device 44 may include circuitry to detect this power sink.
  • the provision of power to the auxiliary device 46 allows the host 44 to detect insertion.
  • This configuration allows use of a USB 3.0 Standard A connector, a standard B connector, as well as Micro-A and Micro-B connectors because this configuration does not rely on the four phase insertion that is used in the other configurations.
  • the additional lane may be a data lane.
  • the clock signal may be used. Note that the first two configurations ( FIGS. 5 and 6 ) described above do not support such a clock signal and thus are appropriate for use with M-PHY Type-I.
  • the third configuration of FIG. 7 allows for a shared clock, and thus supports M-PHY Type II. Still other uses for this lane may be provided.
  • the data lane formed from pins 36 B and 36 C may not support high data rates. This distinction results from the quality of the shielding and the physical geometries of the pins. However, even if the quality of the connector and the cable does not support high data rates, the data lane formed from pins 36 B and 36 C is still usable for low data rates, such as the M-PHY LS-MODE PWM data rate.
  • the operation of the M-PHY communications protocol over a USB interface and related devices, systems, and methods, according to embodiments disclosed herein, may be provided in or integrated into any processor-based device.
  • Examples include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone or smart phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, and a portable digital video player.
  • PDA personal digital assistant
  • FIG. 8 illustrates an example of a processor-based system 170 that can employ the connector plug 32 illustrated in FIG. 1C (or other USB compliant plug or receptacle), with the mapping of FIG. 2 (in any of the configurations set forth above or other comparable configurations tailored to a different plug or receptacle) applied thereto.
  • a controller 200 interoperates with the lane management module 62 A as illustrated.
  • the processor-based system 170 includes one or more central processing units (CPUs) 172 , each including one or more processors 174 .
  • the CPU(s) 172 may be a master device.
  • the CPU(s) 172 may have cache memory 176 coupled to the processor(s) 174 for rapid access to temporarily stored data.
  • the CPU(s) 172 is coupled to a system bus 180 and can intercouple master devices and slave devices included in the processor-based system 170 .
  • the system bus 180 may be a bus interconnect.
  • the CPU(s) 172 communicates with these other devices by exchanging address, control, and data information over the system bus 180 .
  • the CPU(s) 172 can communicate bus transaction requests to the memory controller 168 (N) as an example of a slave device.
  • N memory controller 168
  • multiple system buses 180 could be provided, wherein each system bus 180 constitutes a different fabric.
  • Other master and slave devices can be connected to the system bus 180 . As illustrated in FIG. 8 , these devices can include a memory system 182 , one or more input devices 184 , one or more output devices 186 , one or more network interface devices 188 , and one or more display controllers 190 , as examples.
  • the input device(s) 184 can include any type of input device, including but not limited to input keys, switches, voice processors, etc.
  • the output device(s) 186 can include any type of output device, including but not limited to audio, video, other visual indicators, etc.
  • the network interface device(s) 188 can be any devices configured to allow exchange of data to and from a network 192 .
  • the network 192 can be any type of network, including but not limited to a wired or wireless network, private or public network, a local area network (LAN), a wide local area network (WLAN), and the Internet.
  • the network interface device(s) 188 can be configured to support any type of communication protocol desired.
  • the memory system 182 can include one or more memory units 193 ( 0 -N).
  • the arbiter may be provided between the system bus 180 and master and slave devices coupled to the system bus 180 , such as, for example, the memory units 193 ( 0 -N) provided in the memory system 182 .
  • the CPU 172 may also be configured to access the display controller(s) 190 over the system bus 180 to control information sent to one or more displays 194 .
  • the display controller(s) 190 sends information to the display(s) 194 to be displayed via one or more video processors 196 , which process the information to be displayed into a format suitable for the display(s) 194 .
  • the display(s) 194 can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.
  • the CPU(s) 172 and the display controller(s) 190 may act as master devices to make memory access requests to an arbiter over the system bus 180 . Different threads within the CPU(s) 172 and the display controller(s) 190 may make requests to the arbiter.
  • the CPU(s) 172 and the display controller(s) 1 . 90 may provide the MID to the arbiter, as previously described, as part of a bus transaction request.
  • a processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
  • a processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
  • RAM Random Access Memory
  • ROM Read Only Memory
  • EPROM Electrically Programmable ROM
  • EEPROM Electrically Erasable Programmable ROM
  • registers hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art.
  • An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium.
  • the storage medium may be integral to the processor.
  • the processor and the storage medium may reside in an ASIC.
  • the ASIC may reside in a remote station.
  • the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

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US13/356,521 2012-01-23 2012-01-23 Operating m-phy based communications over universal serial bus (usb) interface, and related cables, connectors, systems and methods Abandoned US20130191568A1 (en)

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US13/356,521 US20130191568A1 (en) 2012-01-23 2012-01-23 Operating m-phy based communications over universal serial bus (usb) interface, and related cables, connectors, systems and methods
TW102102578A TW201344453A (zh) 2012-01-23 2013-01-23 於通用串列匯流排（ｕｓｂ）介面上操作以ｍ－ｐｈｙ為基礎之通訊及其相關纜線、連接器、系統及方法
JP2014553541A JP2015508194A (ja) 2012-01-23 2013-01-23 ユニバーサルシリアルバス（ｕｓｂ）インタフェースを介してｍ−ｐｈｙ通信プロトコルを動作すること及び関連する装置、システム並びに方法
EP13705290.8A EP2807571A1 (en) 2012-01-23 2013-01-23 Operating m-phy communications protocol over universal serial bus (usb) interface, and related devices, systems and methods
PCT/US2013/022795 WO2013112620A1 (en) 2012-01-23 2013-01-23 Operating m-phy communications protocol over universal serial bus (usb) interface, and related devices, systems and methods
CN201380006200.1A CN104067251A (zh) 2012-01-23 2013-01-23 在通用串行总线（usb）接口上操作m-phy通信协议，以及相关设备、系统和方法

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