US20120220124A1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- US20120220124A1 US20120220124A1 US13/240,340 US201113240340A US2012220124A1 US 20120220124 A1 US20120220124 A1 US 20120220124A1 US 201113240340 A US201113240340 A US 201113240340A US 2012220124 A1 US2012220124 A1 US 2012220124A1
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- 238000000034 method Methods 0.000 title claims abstract description 83
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000009413 insulation Methods 0.000 claims abstract description 41
- 239000012535 impurity Substances 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 128
- 239000002253 acid Substances 0.000 claims description 58
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 50
- 229910052698 phosphorus Inorganic materials 0.000 claims description 50
- 239000011574 phosphorus Substances 0.000 claims description 50
- 229910052796 boron Inorganic materials 0.000 claims description 49
- 230000008569 process Effects 0.000 claims description 48
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 47
- 239000011229 interlayer Substances 0.000 claims description 39
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 26
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 25
- 239000007800 oxidant agent Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 18
- 239000003054 catalyst Substances 0.000 claims description 17
- 238000010494 dissociation reaction Methods 0.000 claims description 17
- 230000005593 dissociations Effects 0.000 claims description 16
- 238000002156 mixing Methods 0.000 claims description 15
- 239000005368 silicate glass Substances 0.000 claims description 14
- 238000000280 densification Methods 0.000 claims description 13
- 230000003247 decreasing effect Effects 0.000 claims description 11
- VRZFDJOWKAFVOO-UHFFFAOYSA-N [O-][Si]([O-])([O-])O.[B+3].P Chemical compound [O-][Si]([O-])([O-])O.[B+3].P VRZFDJOWKAFVOO-UHFFFAOYSA-N 0.000 claims description 8
- 238000001035 drying Methods 0.000 claims description 8
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 5
- VLTRZXGMWDSKGL-UHFFFAOYSA-N perchloric acid Chemical compound OCl(=O)(=O)=O VLTRZXGMWDSKGL-UHFFFAOYSA-N 0.000 claims description 5
- BMYNFMYTOJXKLE-UHFFFAOYSA-N 3-azaniumyl-2-hydroxypropanoate Chemical compound NCC(O)C(O)=O BMYNFMYTOJXKLE-UHFFFAOYSA-N 0.000 claims description 3
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 3
- XMBWDFGMSWQBCA-UHFFFAOYSA-N hydrogen iodide Chemical compound I XMBWDFGMSWQBCA-UHFFFAOYSA-N 0.000 claims description 3
- 229940071870 hydroiodic acid Drugs 0.000 claims description 3
- FHHJDRFHHWUPDG-UHFFFAOYSA-N peroxysulfuric acid Chemical compound OOS(O)(=O)=O FHHJDRFHHWUPDG-UHFFFAOYSA-N 0.000 claims description 3
- -1 sulfuric acid peroxide Chemical class 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 2
- 238000002203 pretreatment Methods 0.000 description 85
- 239000000243 solution Substances 0.000 description 28
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 12
- 239000000463 material Substances 0.000 description 11
- 239000007864 aqueous solution Substances 0.000 description 10
- 230000001965 increasing effect Effects 0.000 description 6
- 150000007513 acids Chemical class 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 4
- 150000007522 mineralic acids Chemical class 0.000 description 4
- 150000007524 organic acids Chemical class 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 229920001709 polysilazane Polymers 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000006227 byproduct Substances 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000005389 semiconductor device fabrication Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000007669 thermal treatment Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- KGBXLFKZBHKPEV-UHFFFAOYSA-N boric acid Chemical compound OB(O)O KGBXLFKZBHKPEV-UHFFFAOYSA-N 0.000 description 2
- YZYDPPZYDIRSJT-UHFFFAOYSA-K boron phosphate Chemical compound [B+3].[O-]P([O-])([O-])=O YZYDPPZYDIRSJT-UHFFFAOYSA-K 0.000 description 2
- 229910000149 boron phosphate Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910015444 B(OH)3 Inorganic materials 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-L Phosphate ion(2-) Chemical compound OP([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-L 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000004327 boric acid Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-M dihydrogenphosphate Chemical compound OP(O)([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-M 0.000 description 1
- 208000018459 dissociative disease Diseases 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003517 fume Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 235000005985 organic acids Nutrition 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 1
- 229940085991 phosphate ion Drugs 0.000 description 1
- 238000007614 solvation Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Definitions
- Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device fabrication method that may secure a proper dimension margin between contact holes.
- CD critical dimensions
- an insulation layer such as a Tetraethyl Orthosilicate (TEOS) layer, a High-Density Plasma (HDP) layer, or a Boron Phosphorus Silicate Glass (BPSG) layer, may be used for an inter-layer dielectric layer.
- TEOS Tetraethyl Orthosilicate
- HDP High-Density Plasma
- BPSG Boron Phosphorus Silicate Glass
- a method of using a Spin-On Dielectric (SOD) layer may be used to obtain excellent gap-fill performance.
- an SOD layer is formed by applying a polysilazane-based material (e.g., perhydropolysilazane (PSZ)) through a spin coating method and performing a high-temperature thermal treatment.
- PSZ perhydropolysilazane
- Processes for forming a polysilazane-based SOD layer are relatively simple and have a high throughput.
- the polysilazane-based SOD layer is often formed by a thermal treatment performed at approximately 850° C. or higher, where a compositional change and a volume shrinkage may occur due to the fume generated during the thermal treatment and thus cause deformation in pattern shapes.
- voids may be produced during subsequent processes.
- a BPSG layer has an advantage that its gap-fill performance may be increased by increasing the concentrations of boron and phosphorus in the layer and increasing the temperature of a subsequent annealing process.
- FIG. 1 is a cross-sectional view illustrating a method for fabricating a semiconductor device according to prior art.
- an inter-layer dielectric layer 14 is formed over the substrate structure including the contact plugs 13 .
- the inter-layer dielectric layer 14 includes BPSG.
- the inter-layer dielectric layer 14 is planarized through a Chemical Mechanical Polishing (CMP) process.
- a method for fabricating a semiconductor device includes: forming an insulation layer containing an impurity; forming a contact hole by etching the insulation layer; performing a treatment to decrease a concentration of the impurity on a surface of the insulation layer; and rinsing the contact hole.
- a method for fabricating a semiconductor device includes: forming a first contact plug over a substrate; forming a Boron-Phosphorus-Silicate Glass (BPSG) layer over the first contact plug; forming a contact hole that exposes the first contact plug by etching the BPSG layer; performing a treatment on sidewalls of the contact hole by using a solution prepared by mixing sulfuric acid and hydrogen peroxide; rinsing the contact hole; and forming a second contact plug in the contact hole.
- BPSG Boron-Phosphorus-Silicate Glass
- FIGS. 3A to 3E are cross-sectional views describing a method for fabricating a semiconductor device using a pre-treatment method in accordance with an exemplary embodiment of the present invention.
- FIG. 5B is a graph showing wet etch rates of the BPSG layer after a pre-treatment.
- first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate but also a case where a third layer exists between the first layer and the second layer or the substrate.
- FIG. 2 is a cross-sectional view illustrating a pre-treatment on an insulation layer in accordance with an exemplary embodiment of the present invention.
- a pre-treatment 102 is performed.
- the pre-treatment 102 is performed using a pre-treatment solution.
- the pre-treatment solution is prepared by mixing a catalyst which captures an impurity (e.g., boron (B) and/or phosphorus (P)) in the insulation layer 101 and an oxidizing agent for oxidizing areas after the removal of the impurity by the catalyst.
- the catalyst may be any reasonably suitable acid having a relatively small acid dissociation constant (pKa). Examples of the catalyst include perchloric acid, hydroiodic acid, hydrobromic acid, hydrochloric acid, peroxymonosulfuric acid, and sulfuric acid.
- the impurity removal and the densification resulting from the pre-treatment 102 depend on the length of time that a pre-treatment is performed, mixing ratio, and the temperature used. For example, as the length of time that the pre-treatment is performed becomes longer, the ratio of the oxidizing agent in the pre-treatment solution becomes greater, or the temperature used increases, the impurity removal and the densification intensify.
- the pre-treatment 102 is followed by a rinsing process and a drying process.
- a rinsing process alcohol and/or water may be used.
- the drying process may be performed in the atmosphere of isopropyl alcohol (IPA) and nitrogen (N 2 ) gas.
- IPA isopropyl alcohol
- N 2 nitrogen
- the surface of the insulation layer 101 is densified.
- the process of densifying the surface of the insulation layer 101 is as follows.
- a pre-treatment is performed on an insulation layer including at least any one impurity among boron (B) and phosphorus (P) by using a material having a relatively small acid dissociation constant (pKa).
- the insulation layers including boron and/or phosphorus include BPSG, PSG, and BSG.
- the acid dissociation constant (pKa) is used a barometer for quantitatively representing the intensity of an acid. More specifically, a dissociation reaction where protons are released from an acid is taken into consideration and is represented by the balance integer Ka or its negative common logarithms ( ⁇ log) (pKa) according to an example. As described above, as the pKa becomes smaller, the acid becomes stronger. According to an example, a material having a relatively small acid dissociation constant (pKa) may be an acid aqueous solution. The material having a relatively small acid dissociation constant (pKa) is a strong acid material. In the exemplary embodiment of the present invention, a strong acid has an acid dissociation constant (pKa) ranging from approximately ⁇ 10 to approximately 1.
- Strong acids include inorganic acids and organic acids having an acid dissociation constant (pKa) ranging from approximately ⁇ 10 to approximately 1.
- pKa acid dissociation constant
- the use of a strong acid may shorten the pre-treatment time and maximize the densification of the insulation layer. If a weaker acid is used, it takes a longer time to perform the pre-treatment and since the pre-treatment takes longer, materials around the insulation layer may be damaged.
- the aqueous solution becomes an oxidizing agent
- the strong acid becomes a catalyst that removes impurities. Therefore, when the pre-treatment is performed using a pre-treatment solution including an aqueous solution where a strong acid is dissolved for BPSG, PSG and BSG, the surface of the insulation layer is dehydrated and/or oxidized and thus further densify (e.g., achieve greater density and/or hardness) the surface.
- boron (B) and phosphorus (P) melt in the presence of the strong acid, and the voids previously occupied by the molten boron (B) and phosphorus (P) become oxidized by the oxidizing agent.
- the insulation layer becomes densified to form a densified layer 103 .
- B 2 O 3 (s), P 2 O 3 (s), and P 2 O 5 (s) present in the insulation layer 101 receive acidic proton from the high-acidity pre-treatment solution to thereby form ions such as boric acid (B(OH) 3 ), tetrahydroxyborate ion, phosphate ion, hydrogen phosphate ion, and dihydrogen phosphate ion.
- B(OH) 3 boric acid
- tetrahydroxyborate ion tetrahydroxyborate ion
- phosphate ion phosphate ion
- hydrogen phosphate ion hydrogen phosphate ion
- dihydrogen phosphate ion dihydrogen phosphate ion
- boron and phosphorus are removed from the surface of the insulation layer, where the concentrations of boron and phosphorus become lower on the surface. With the remaining structure, loss of BPSG during the subsequent rinsing process may be reduced and CD margin may be secured.
- the concentration of boron and phosphorus may be reduced.
- the concentrations of boron and phosphorus within the insulation layer are decreased, diffusion into neighboring materials may be prevented so as to improve the reliability of the semiconductor device.
- the decrease in the concentrations of boron and phosphorus does not affect the insulation characteristics of the insulation layer 101 .
- the high concentrations of boron and phosphorus already contributed to improvement of the gap-fill characteristics of the insulation layer 101 , the subsequent decrease in the concentrations of boron and phosphorus does not cause functional detriments.
- the pre-treatment 102 is performed using the pre-treatment solution obtained by mixing the catalyst (strong acid), which induces densification of the insulation layer 101 (e.g., BPSG and PSG) including boron and phosphorus and the oxidizing agent for causing oxidization, the insulation layer 101 becomes densified. As a result, loss of neighboring materials does not occur in subsequently performing the rinsing process.
- the catalyst strong acid
- the byproducts generated during the pre-treatment 102 may be properly removed during the subsequent rinsing and drying processes without causing damage to the resulting structure.
- FIGS. 3A to 3E are cross-sectional views describing a method for fabricating a semiconductor device using a pre-treatment method in accordance with an exemplary embodiment of the present invention.
- an isolation layer 202 is formed over the substrate 201 to fill trenches through a Shallow Trench Isolation (STI) process.
- the isolation layer 202 may be a Spin-On Dielectric (SOD) layer or a I-Ugh-Density Plasma (HDP) oxide layer.
- First contact plugs 203 are formed over the substrate 201 .
- the first contact plugs 203 may be landing plugs and may be formed of polysilicon. Although not illustrated in the drawings, buried gates may be formed in the substrate 201 .
- the inter-layer dielectric layer 204 may be an insulation layer including at least any one impurity among boron (B) and phosphorus (P).
- the inter-layer dielectric layer 204 includes a silicon oxide layer including an impurity.
- the inter-layer dielectric layer 204 may include BPSG containing boron (B) and phosphorus (P),
- P PSG containing phosphorus
- B BSG containing boron
- the contact holes 205 expose the surface of the first contact plugs 203 . Also, the inter-layer dielectric layer 204 is exposed on the sidewalls outlining each contact hole 205 .
- a pre-treatment 206 is performed.
- the pre-treatment 206 is performed using a pre-treatment solution.
- the pre-treatment solution is a solution containing a catalyst for removing the impurity (boron (B) and/or phosphorus (P)) in the inter-layer dielectric layer 204 and an oxidizing agent for oxidizing the areas from which the impurity has been removed.
- the catalyst includes acids having a relatively small acid dissociation constant (pKa).
- the examples of the catalyst include perchloric acid, hydroiodic acid, hydrobromic acid, hydrochloric acid, peroxymonosulfuric acid, and sulfuric acid.
- the acid dissociation constant (pKa) of the above acids ranges from approximately ⁇ 10 to approximately 1.
- An acid having such a small acid dissociation constant (pKa) is considered to be a strong acid and may be an inorganic acid or an organic acid.
- the pre-treatment solution includes such an acid in an amount of approximately 10 to approximately 40 wt %.
- the oxidizing agent may be any reasonably suitable aqueous solution.
- the oxidizing agent may be hydrogen peroxide (H 2 O 2 ), ozone (O 3 ), etc.
- the pre-treatment solution may include the oxidizing agent in an amount of approximately 1 wt % to approximately 10 wt %.
- the mixing ratio of the oxidizing agent to the catalyst may range from approximately 4:1 to approximately 50:1, where the 4:1 pre-treatment solution has a higher oxidizing agent ratio in the solution than a 50:1 pre-treatment solution.
- the pre-treatment 206 process is performed by immersing the substrate 201 in the pre-treatment solution at a room temperature to approximately 250° C. for approximately 5 minutes to approximately 60 minutes. According to an example, the pre-treatment 206 is performed at a temperature of approximately 90° C. to approximately 250° C. Here, as the temperature for performing the pre-treatment 206 is increased, the impurity removal and the densification intensify.
- the impurity removal and the densification resulting from the pre-treatment 206 depend on the length of time that a pre-treatment time is performed, mixing ratio, and the temperature used. For example, as the pre-treatment time becomes longer, the ratio of the oxidizing agent in the pre-treatment solution becomes greater, and the temperature is high, the densification and the impurity removal intensify.
- the pre-treatment 206 is followed by a rinsing process and a drying process.
- a rinsing process alcohol and/or water may be used.
- the drying process may be performed in the atmosphere of isopropyl alcohol (IPA) and nitrogen (N 2 ) gas.
- IPA isopropyl alcohol
- N 2 nitrogen
- the densified layer 207 is a silicon oxide layer with decreased concentration of boron (B) and phosphorus (P).
- the densified layer 207 is denser than untreated BPSG, PSG, and BSG.
- a strong acid has an acid dissociation constant (pKa) ranging from approximately ⁇ 10 to approximately 1.
- a strong acid may be an inorganic acid or an organic acid having an acid dissociation constant (pKa) ranging from approximately ⁇ 10 to approximately 1.
- the use of a strong acid may shorten the pre-treatment time and maximize the densification effect of the inter-layer dielectric layer 204 . If a weak acid having an acid dissociation constant (pKa) of 1 or more is used, it takes a relatively long time to perform the pre-treatment and because of the long pre-treatment time, the materials around the inter-layer dielectric layer 204 may be damaged.
- the pre-treatment 206 is performed using the pre-treatment solution obtained by mixing the catalyst (strong acid), which induces densification of the inter-layer dielectric layer 204 (e.g., BPSG and PSG) including boron (B) and phosphorus (P) and the oxidizing agent for causing oxidization, the inter-layer dielectric layer 204 becomes densified.
- the pre-treatment 206 is formed, and loss of the inter-layer dielectric layer 204 does not occur in the subsequently performed rinsing process due to the presence of the densified layer 207 .
- the byproducts generated during the pre-treatment 206 may be properly removed during the subsequent rinsing and drying processes without causing damage to the resulting structure.
- FIGS. 4A and 4B are graphs showing the concentrations of boron and phosphorus of a Boron-Phosphorus-Silicate Glass (BPSG) layer after a pre-treatment in accordance with an exemplary embodiment of the present invention.
- BPSG Boron-Phosphorus-Silicate Glass
- the concentration ( 300 ) of boron (B) and the concentration ( 320 ) of phosphorus (P) on the sidewalls outlining each contact hole are remarkably decreased to a certain depth below the surface.
- concentration 310 shows a decreased concentration of boron (B)
- a concentration 330 shows a decreased concentration of phosphorus (P).
- a Boron-Phosphorus-Silicate Glass (BPSG) layer was deposited at a thickness of approximately 1.8 K ⁇ over a plane silicon wafer, and an annealing process was performed at approximately 750° C. Subsequently, the BPSG layer was removed by approximately 300 ⁇ through a “touch” Chemical Mechanical Polishing (CMP) process. Subsequently, the wt % concentrations of the boron (B) and phosphorus (P) in the BPSG layer were measured. Then, the BPSG layer went through a pre-treatment using diverse kinds of acid aqueous solutions and the wt % concentrations of the boron (B) and phosphorus (P) in the BPSG layer were measured.
- CMP Chemical Mechanical Polishing
- FIG. 5A shows the differences in the concentrations of boron (B) and phosphorus (P) after the pre-treatment was performed on the BPSG layer. It may be seen from FIG. 5A that the differences between the concentrations ( ⁇ ) before and after the pre-treatment are relatively great. The differences in the concentrations before and after the pre-treatment have different magnitudes and reflect differences in the pre-treatment conditions such as time, temperature, etc. Here, when the pre-treatment is not performed, there are little changes in the concentrations of boron (B) and phosphorus (P).
- sample specimens acids A, B, B′, B′′, and C had the following pre-treatment conditions.
- a BPSG layer is deposited at a thickness of approximately 1.8 K ⁇ over a plane silicon wafer, and an annealing process is performed at approximately 750° C. Subsequently, the BPSG layer is removed by approximately 300 ⁇ through a “touch” CMP process. Subsequently, a pattern having a hole of approximately 115 nm in the major axis and approximately 66 nm in the minor axis is formed through a mask process and an etch process. Subsequently, a splitting process is performed according to whether a pre-treatment using an acid aqueous solution is performed or not, and then a rinsing process is performed using a buffered oxide etchant.
- the acid aqueous solution is an SPM solution.
- FIGS. 6A and 6B are photographs showing a critical dimension (CD) decrease of a minimum bar after a pre-treatment.
- the surface of the insulation layer may be induced to be densified. Due to the resulting dense surface of the insulation layer, loss of the insulation layer may be minimized during a subsequent cleaning process to thereby decrease the frequency of the generation of bridges and other defects.
- an insulation layer e.g., BPSG, PSG, or BSG
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Abstract
Description
- The present application claims priority of Korean Patent Application No. 10-2011-0017805, filed on Feb. 28, 2011, which is incorporated herein by reference in its entirety.
- 1. Field
- Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device fabrication method that may secure a proper dimension margin between contact holes.
- 2. Description of the Related Art
- As the integration degree of semiconductor devices increase with the development of under-30 nm processing technology, the critical dimensions (CD) (e.g., line widths) of patterns for gates, bit lines, vias, contact holes, etc. become smaller and thus, it becomes more difficult to form the appropriate patterns. Particularly, with the increased integration degree, the aspect ratios of patterns also increase, and thus, it is more difficult to perform processes for forming an inter-layer dielectric (ILD) layer.
- Here, an insulation layer, such as a Tetraethyl Orthosilicate (TEOS) layer, a High-Density Plasma (HDP) layer, or a Boron Phosphorus Silicate Glass (BPSG) layer, may be used for an inter-layer dielectric layer. However, due to limitations as a gap-fill material, use of TEOS layer or HDP layer as an inter-layer dielectric layer has been difficult.
- According to another example, a method of using a Spin-On Dielectric (SOD) layer may be used to obtain excellent gap-fill performance. Here, an SOD layer is formed by applying a polysilazane-based material (e.g., perhydropolysilazane (PSZ)) through a spin coating method and performing a high-temperature thermal treatment. Processes for forming a polysilazane-based SOD layer are relatively simple and have a high throughput.
- The polysilazane-based SOD layer, however, is often formed by a thermal treatment performed at approximately 850° C. or higher, where a compositional change and a volume shrinkage may occur due to the fume generated during the thermal treatment and thus cause deformation in pattern shapes. As the inner and lower portions of the polysilazane-based SOD layer are prone to not having complete densification, voids may be produced during subsequent processes.
- Because of the above-discussed features of conventional examples, Boron-Phosphorus-Silicate Glass (BPSG) has been often used for forming an inter-layer dielectric layer.
- A BPSG layer has an advantage that its gap-fill performance may be increased by increasing the concentrations of boron and phosphorus in the layer and increasing the temperature of a subsequent annealing process.
-
FIG. 1 is a cross-sectional view illustrating a method for fabricating a semiconductor device according to prior art. - Referring to
FIG. 1 , anisolation layer 12 to fill trenches is formed by performing a Shallow Trench Isolation (STI) process on asubstrate 11. Subsequently,contact plugs 13 are formed over thesubstrate 11. - Subsequently, an inter-layer dielectric layer 14 is formed over the substrate structure including the
contact plugs 13. The inter-layer dielectric layer 14 includes BPSG. The inter-layer dielectric layer 14 is planarized through a Chemical Mechanical Polishing (CMP) process. - Subsequently,
contact holes 15 are formed by etching the inter-layer dielectric layer 14, which is cleaned afterward through a cleaning process. - According to an example, BPSG used as the inter-layer dielectric layer 14 may produce byproducts such as boron phosphate (BPO4) crystallite when the concentration of boron and/or phosphorus is relatively high. In such a case, it may be difficult to perform a CMP process. Further, with respect to an etchant used during a dry etch process and a wet etch process, BPSG has a faster etch rate than a silicon oxide (SiO2) layer, where, if the cleaning process is performed rigorously, a
bridge 16 may be produced in the resulting structure. - Thus, it may be useful to have a semiconductor device fabrication method that can minimize/reduce the loss of an inter-layer dielectric layer during etching processes by inducing densification locally on exposed BPSG.
- An exemplary embodiment of the present invention is directed to a semiconductor device fabrication method that may prevent bridge formation due to loss of an inter-layer dielectric layer during a cleaning process.
- In accordance with an exemplary embodiment of the present invention, a method for fabricating a semiconductor device includes: forming an insulation layer containing an impurity; forming a contact hole by etching the insulation layer; performing a treatment to decrease a concentration of the impurity on a surface of the insulation layer; and rinsing the contact hole.
- In accordance with another exemplary embodiment of the present invention, a method for fabricating a semiconductor device includes: forming a plurality of patterns over a substrate; forming an inter-layer dielectric layer to gap-fill spaces between the patterns, wherein inter-layer dielectric layer contains phosphorus as an impurity; forming a contact hole by etching the inter-layer dielectric layer; performing a treatment for decreasing a concentration of the impurity on a surface of the inter-layer dielectric layer; and rinsing the contact hole.
- In accordance with another exemplary embodiment of the present invention, a method for fabricating a semiconductor device includes: forming a first contact plug over a substrate; forming a Boron-Phosphorus-Silicate Glass (BPSG) layer over the first contact plug; forming a contact hole that exposes the first contact plug by etching the BPSG layer; performing a treatment on sidewalls of the contact hole by using a solution prepared by mixing sulfuric acid and hydrogen peroxide; rinsing the contact hole; and forming a second contact plug in the contact hole.
-
FIG. 1 is a cross-sectional view illustrating a method for fabricating a semiconductor device according to prior art. -
FIG. 2 is a cross-sectional view illustrating a pre-treatment method for performing a pre-treatment on an insulation layer in accordance with an exemplary embodiment of the present invention. -
FIGS. 3A to 3E are cross-sectional views describing a method for fabricating a semiconductor device using a pre-treatment method in accordance with an exemplary embodiment of the present invention. -
FIGS. 4A and 4B are graphs showing the concentrations of boron and phosphorus of a Boron-Phosphorus-Silicate Glass (BPSG) layer after a pre-treatment in accordance with an exemplary embodiment of the present invention. -
FIG. 5A is a graph showing the concentrations of boron and phosphorus of a BPSG layer after a pre-treatment in accordance with an exemplary embodiment of the present invention. -
FIG. 5B is a graph showing wet etch rates of the BPSG layer after a pre-treatment. -
FIGS. 6A and 6B are photographs showing a critical dimension decrease of a minimum bar after a pre-treatment. - Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and exemplary embodiments of the present invention.
- The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the exemplary embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate but also a case where a third layer exists between the first layer and the second layer or the substrate.
-
FIG. 2 is a cross-sectional view illustrating a pre-treatment on an insulation layer in accordance with an exemplary embodiment of the present invention. - Referring to
FIG. 2 , aninsulation layer 101 including boron (B) and phosphorus (P) is formed over asubstrate 100 as an inter-layer dielectric (ILD) layer. Here, theinsulation layer 101 includes at least any one impurity among boron and phosphorus. For example, theinsulation layer 101 may include BPSG including boron (B) and phosphorus (P), phosphorus silicate glass (PSG) including phosphorus (P), and boron silicate glass (BSG) including boron (B). Also, theinsulation layer 101 may be formed to gap-fill the gap between the patterns formed over thesubstrate 100. The surface of theinsulation layer 101 may be planarized through a Chemical Mechanical Polishing (CMP) processing. - Subsequently, a pre-treatment 102 is performed. The pre-treatment 102 is performed using a pre-treatment solution. The pre-treatment solution is prepared by mixing a catalyst which captures an impurity (e.g., boron (B) and/or phosphorus (P)) in the
insulation layer 101 and an oxidizing agent for oxidizing areas after the removal of the impurity by the catalyst. The catalyst may be any reasonably suitable acid having a relatively small acid dissociation constant (pKa). Examples of the catalyst include perchloric acid, hydroiodic acid, hydrobromic acid, hydrochloric acid, peroxymonosulfuric acid, and sulfuric acid. The acid dissociation constant (pKa) for the foregoing acids ranges from approximately −10 to approximately 1. An acid having such a relatively small acid dissociation constant (pKa) is considered to be a strong acid and may be an inorganic acid or an organic acid. The pre-treatment solution includes such an acid in an amount of approximately 10 wt % to approximately 40 wt %. The oxidizing agent may be any reasonably suitable aqueous solution. For example, the oxidizing agent may be hydrogen peroxide (H2O2), ozone (O3), etc. The pre-treatment solution may include the oxidizing agent in an amount of approximately 1 wt % to approximately 10 wt %. The mixing ratio of the oxidizing agent to the catalyst may range from approximately 4:1 to approximately 50:1, where the 4:1 pre-treatment solution has a higher oxidizing agent ratio in the solution than a 50:1 pre-treatment solution. - The pre-treatment 102 process is performed by immersing the
substrate 100 in the pre-treatment solution at a room temperature to approximately 250° C. for approximately 5 minutes to approximately 60 minutes. According to an example, the pre-treatment 102 is performed at a temperature of approximately 90° C. to approximately 250° C. Here, as the temperature for performing the pre-treatment 102 is increased, the impurity removal and the densification (e.g., achieving greater density and/or hardness) intensify. - Here, the impurity removal and the densification resulting from the pre-treatment 102 depend on the length of time that a pre-treatment is performed, mixing ratio, and the temperature used. For example, as the length of time that the pre-treatment is performed becomes longer, the ratio of the oxidizing agent in the pre-treatment solution becomes greater, or the temperature used increases, the impurity removal and the densification intensify.
- The pre-treatment 102 is followed by a rinsing process and a drying process. For the rinsing process, alcohol and/or water may be used. The drying process may be performed in the atmosphere of isopropyl alcohol (IPA) and nitrogen (N2) gas.
- As described above, when the pre-treatment 102 is performed, the surface of the
insulation layer 101 is densified. - The process of densifying the surface of the
insulation layer 101 is as follows. - As described above, a pre-treatment is performed on an insulation layer including at least any one impurity among boron (B) and phosphorus (P) by using a material having a relatively small acid dissociation constant (pKa). Examples of the insulation layers including boron and/or phosphorus include BPSG, PSG, and BSG.
- Here, the acid dissociation constant (pKa) is used a barometer for quantitatively representing the intensity of an acid. More specifically, a dissociation reaction where protons are released from an acid is taken into consideration and is represented by the balance integer Ka or its negative common logarithms (−log) (pKa) according to an example. As described above, as the pKa becomes smaller, the acid becomes stronger. According to an example, a material having a relatively small acid dissociation constant (pKa) may be an acid aqueous solution. The material having a relatively small acid dissociation constant (pKa) is a strong acid material. In the exemplary embodiment of the present invention, a strong acid has an acid dissociation constant (pKa) ranging from approximately −10 to approximately 1. Strong acids include inorganic acids and organic acids having an acid dissociation constant (pKa) ranging from approximately −10 to approximately 1. The use of a strong acid may shorten the pre-treatment time and maximize the densification of the insulation layer. If a weaker acid is used, it takes a longer time to perform the pre-treatment and since the pre-treatment takes longer, materials around the insulation layer may be damaged.
- According to the exemplary embodiment, the aqueous solution becomes an oxidizing agent, and the strong acid becomes a catalyst that removes impurities. Therefore, when the pre-treatment is performed using a pre-treatment solution including an aqueous solution where a strong acid is dissolved for BPSG, PSG and BSG, the surface of the insulation layer is dehydrated and/or oxidized and thus further densify (e.g., achieve greater density and/or hardness) the surface. For example, boron (B) and phosphorus (P) melt in the presence of the strong acid, and the voids previously occupied by the molten boron (B) and phosphorus (P) become oxidized by the oxidizing agent. As such, the insulation layer becomes densified to form a densified
layer 103. In addition, B2O3(s), P2O3(s), and P2O5(s) present in theinsulation layer 101 receive acidic proton from the high-acidity pre-treatment solution to thereby form ions such as boric acid (B(OH)3), tetrahydroxyborate ion, phosphate ion, hydrogen phosphate ion, and dihydrogen phosphate ion. The ions thus formed undergo solvation in the aqueous solution and removed during a rinsing process. In the foregoing processes, boron and phosphorus are removed from the surface of the insulation layer, where the concentrations of boron and phosphorus become lower on the surface. With the remaining structure, loss of BPSG during the subsequent rinsing process may be reduced and CD margin may be secured. - As described above, once the boron and phosphorus melt in the presence of the strong acid, the concentration of boron and phosphorus may be reduced. When the concentrations of boron and phosphorus within the insulation layer are decreased, diffusion into neighboring materials may be prevented so as to improve the reliability of the semiconductor device. After gap-filling the gap, the decrease in the concentrations of boron and phosphorus does not affect the insulation characteristics of the
insulation layer 101. Here, the high concentrations of boron and phosphorus already contributed to improvement of the gap-fill characteristics of theinsulation layer 101, the subsequent decrease in the concentrations of boron and phosphorus does not cause functional detriments. - According to the above description, since the pre-treatment 102 is performed using the pre-treatment solution obtained by mixing the catalyst (strong acid), which induces densification of the insulation layer 101 (e.g., BPSG and PSG) including boron and phosphorus and the oxidizing agent for causing oxidization, the
insulation layer 101 becomes densified. As a result, loss of neighboring materials does not occur in subsequently performing the rinsing process. - The byproducts generated during the pre-treatment 102 may be properly removed during the subsequent rinsing and drying processes without causing damage to the resulting structure.
-
FIGS. 3A to 3E are cross-sectional views describing a method for fabricating a semiconductor device using a pre-treatment method in accordance with an exemplary embodiment of the present invention. - Referring to
FIG. 3A , anisolation layer 202 is formed over thesubstrate 201 to fill trenches through a Shallow Trench Isolation (STI) process. According to another example, theisolation layer 202 may be a Spin-On Dielectric (SOD) layer or a I-Ugh-Density Plasma (HDP) oxide layer. - First contact plugs 203 are formed over the
substrate 201. The first contact plugs 203 may be landing plugs and may be formed of polysilicon. Although not illustrated in the drawings, buried gates may be formed in thesubstrate 201. - Subsequently, an
inter-layer dielectric layer 204 is formed over the substrate structure including the first contact plugs 203. Theinter-layer dielectric layer 204 may be an insulation layer including at least any one impurity among boron (B) and phosphorus (P). For example, theinter-layer dielectric layer 204 includes a silicon oxide layer including an impurity. Theinter-layer dielectric layer 204 may include BPSG containing boron (B) and phosphorus (P), - PSG containing phosphorus (P), or BSG containing boron (B).
- Referring to
FIG. 3B , contact holes 205 are formed by etching theinter-layer dielectric layer 204. Here, the contact holes 205 may be bit line contact holes or storage node contact holes. Here, for purposes of illustration, it is assumed that the contact holes 205 are storage node contact holes. - The contact holes 205 expose the surface of the first contact plugs 203. Also, the
inter-layer dielectric layer 204 is exposed on the sidewalls outlining eachcontact hole 205. - Referring to
FIG. 3C , a pre-treatment 206 is performed. The pre-treatment 206 is performed using a pre-treatment solution. The pre-treatment solution is a solution containing a catalyst for removing the impurity (boron (B) and/or phosphorus (P)) in theinter-layer dielectric layer 204 and an oxidizing agent for oxidizing the areas from which the impurity has been removed. The catalyst includes acids having a relatively small acid dissociation constant (pKa). The examples of the catalyst include perchloric acid, hydroiodic acid, hydrobromic acid, hydrochloric acid, peroxymonosulfuric acid, and sulfuric acid. The acid dissociation constant (pKa) of the above acids ranges from approximately −10 to approximately 1. An acid having such a small acid dissociation constant (pKa) is considered to be a strong acid and may be an inorganic acid or an organic acid. The pre-treatment solution includes such an acid in an amount of approximately 10 to approximately 40 wt %. The oxidizing agent may be any reasonably suitable aqueous solution. For example, the oxidizing agent may be hydrogen peroxide (H2O2), ozone (O3), etc. The pre-treatment solution may include the oxidizing agent in an amount of approximately 1 wt % to approximately 10 wt %. The mixing ratio of the oxidizing agent to the catalyst may range from approximately 4:1 to approximately 50:1, where the 4:1 pre-treatment solution has a higher oxidizing agent ratio in the solution than a 50:1 pre-treatment solution. - The pre-treatment 206 process is performed by immersing the
substrate 201 in the pre-treatment solution at a room temperature to approximately 250° C. for approximately 5 minutes to approximately 60 minutes. According to an example, the pre-treatment 206 is performed at a temperature of approximately 90° C. to approximately 250° C. Here, as the temperature for performing the pre-treatment 206 is increased, the impurity removal and the densification intensify. - Here, the impurity removal and the densification resulting from the pre-treatment 206 depend on the length of time that a pre-treatment time is performed, mixing ratio, and the temperature used. For example, as the pre-treatment time becomes longer, the ratio of the oxidizing agent in the pre-treatment solution becomes greater, and the temperature is high, the densification and the impurity removal intensify.
- The pre-treatment 206 is followed by a rinsing process and a drying process. For the rinsing process, alcohol and/or water may be used. The drying process may be performed in the atmosphere of isopropyl alcohol (IPA) and nitrogen (N2) gas.
- As described above, when the pre-treatment 206 is performed, the surface of inter-layer
dielectric layer 204 on the sidewalls of eachcontact hole 205 densify. As a result, a densifiedlayer 207 is formed. - The densified
layer 207 is a silicon oxide layer with decreased concentration of boron (B) and phosphorus (P). The densifiedlayer 207 is denser than untreated BPSG, PSG, and BSG. In the exemplary embodiment of the present invention, a strong acid has an acid dissociation constant (pKa) ranging from approximately −10 to approximately 1. A strong acid may be an inorganic acid or an organic acid having an acid dissociation constant (pKa) ranging from approximately −10 to approximately 1. The use of a strong acid may shorten the pre-treatment time and maximize the densification effect of theinter-layer dielectric layer 204. If a weak acid having an acid dissociation constant (pKa) of 1 or more is used, it takes a relatively long time to perform the pre-treatment and because of the long pre-treatment time, the materials around theinter-layer dielectric layer 204 may be damaged. - As described above, by melting the boron (B) and phosphorus (P) with the strong acid, the concentration of boron (B) and phosphorus (P) in the
inter-layer dielectric layer 204 may be acquired. When the concentration of boron (B) and phosphorus (P) in theinter-layer dielectric layer 204 are decreased, diffusion into the neighboring materials may be prevented so as to improve the reliability of the semiconductor device. After gap-filling the gap, the decrease in the concentrations of boron (B) and phosphorus (P) does not affect the insulation characteristics of theinter-layer dielectric layer 204. Here, the high concentrations of boron (B) and phosphorus (P) already contributed to improvement of the gap-fill characteristics of theinter-layer dielectric layer 204, the subsequent decrease in the concentration of boron and phosphorus does not cause functional detriments. - According to the above description, since the pre-treatment 206 is performed using the pre-treatment solution obtained by mixing the catalyst (strong acid), which induces densification of the inter-layer dielectric layer 204 (e.g., BPSG and PSG) including boron (B) and phosphorus (P) and the oxidizing agent for causing oxidization, the
inter-layer dielectric layer 204 becomes densified. As a result, the pre-treatment 206 is formed, and loss of theinter-layer dielectric layer 204 does not occur in the subsequently performed rinsing process due to the presence of the densifiedlayer 207. - The byproducts generated during the pre-treatment 206 may be properly removed during the subsequent rinsing and drying processes without causing damage to the resulting structure.
- Referring to
FIG. 3D , therinsing process 208 is performed. Therinsing process 208 is performed to facilitate the subsequent formation of second contact plugs. Therinsing process 208 includes a dry rinsing process performed using a gas and/or a wet rinsing process performed using a solution. According to an example, therinsing process 208 is performed using a buffer oxide echant (BOE) solution. - Although the
rinsing process 208 may be rigorously performed, the loss of theinter-layer dielectric layer 204 may be reduced due to the decreased concentrations of boron (B) and phosphorus (P) on the sidewalls of eachcontact hole 205. As a result, the critical dimension (CD) margin between the contact holes 205 may be appropriately secured. - Referring to
FIG. 3E , second contact plugs 209 filling the contact holes 205 are formed. The second contact plugs 209 may be storage node contact plugs and may be formed of polysilicon or metal. According to an example, polysilicon or metal is deposited until the contact holes 205 are filled, and the contact holes 205 may be separated from each other by performing a Chemical Mechanical Polishing (CMP) process. -
FIGS. 4A and 4B are graphs showing the concentrations of boron and phosphorus of a Boron-Phosphorus-Silicate Glass (BPSG) layer after a pre-treatment in accordance with an exemplary embodiment of the present invention. - Referring to
FIGS. 4A and 4B , when the contact holes 205 inFIG. 3C are formed by etching the BPSG layer and pre-treatment using sulfuric acid peroxide mixture (SPM) is performed, the concentration (300) of boron (B) and the concentration (320) of phosphorus (P) on the sidewalls outlining each contact hole are remarkably decreased to a certain depth below the surface. As shown in the drawings, concentration 310 shows a decreased concentration of boron (B), while a concentration 330 shows a decreased concentration of phosphorus (P). - In Experimental Example 1, variations in the concentrations of boron (B) and phosphorus (P) were examined by using plane wafers.
- A Boron-Phosphorus-Silicate Glass (BPSG) layer was deposited at a thickness of approximately 1.8 KÅ over a plane silicon wafer, and an annealing process was performed at approximately 750° C. Subsequently, the BPSG layer was removed by approximately 300 Å through a “touch” Chemical Mechanical Polishing (CMP) process. Subsequently, the wt % concentrations of the boron (B) and phosphorus (P) in the BPSG layer were measured. Then, the BPSG layer went through a pre-treatment using diverse kinds of acid aqueous solutions and the wt % concentrations of the boron (B) and phosphorus (P) in the BPSG layer were measured. The results showed that the pre-treatment reduced the wt % concentrations of the boron (B) and phosphorus (P) in the BPSG layer to some degree. When a wet etch process was performed using a buffered oxide etchant (BOE), the etch rate was decreased.
-
FIG. 5A shows the differences in the concentrations of boron (B) and phosphorus (P) after the pre-treatment was performed on the BPSG layer. It may be seen fromFIG. 5A that the differences between the concentrations (Δ) before and after the pre-treatment are relatively great. The differences in the concentrations before and after the pre-treatment have different magnitudes and reflect differences in the pre-treatment conditions such as time, temperature, etc. Here, when the pre-treatment is not performed, there are little changes in the concentrations of boron (B) and phosphorus (P). -
FIG. 5B shows wet etch rates after the pre-treatment is performed on the BPSG layer. It may be seen fromFIG. 5B that the etch rate is significantly decreased when the subsequent rinsing process using a BOE solution was performed. Although there is a difference in the wet etch rate, it is because the conditions such as time, temperature, etc. were different during the pre-treatment. Here, when the pre-treatment was not performed, approximately 180 Å of loss occurred through the subsequent rinsing process. - In
FIGS. 5A and 5B , sample specimens acids A, B, B′, B″, and C had the following pre-treatment conditions. - The pre-treatment conditions of Acid A were H2SO4:H2O2=10:1, 180° C., and 600 seconds.
- The pre-treatment conditions of Acid B were H2SO4:H2O2=4:1, 120° C., and 450 seconds.
- The pre-treatment conditions of Acid B′ were H2SO4:H2O2=4:1, 120° C., and 1800 seconds.
- The pre-treatment conditions of Acid B″ were H2SO4:H2O2=4:1, 120° C., and 3600 seconds.
- The pre-treatment conditions of Acid C were H2SO4:H2O2=50:1, 80° C., and 450 seconds.
- In Experimental Example 2, the critical dimension margin of a BPSG layer is secured by using a pattern wafer.
- A BPSG layer is deposited at a thickness of approximately 1.8 KÅ over a plane silicon wafer, and an annealing process is performed at approximately 750° C. Subsequently, the BPSG layer is removed by approximately 300 Å through a “touch” CMP process. Subsequently, a pattern having a hole of approximately 115 nm in the major axis and approximately 66 nm in the minor axis is formed through a mask process and an etch process. Subsequently, a splitting process is performed according to whether a pre-treatment using an acid aqueous solution is performed or not, and then a rinsing process is performed using a buffered oxide etchant. Here, the acid aqueous solution is an SPM solution.
-
FIGS. 6A and 6B are photographs showing a critical dimension (CD) decrease of a minimum bar after a pre-treatment. - It may be seen from
FIGS. 6A and 6B that, when comparing the critical dimensions of a BPSG minimum bar between holes, by using the acid aqueous solution, the loss was reduced by approximately 7 nm to approximately 10 nm. Here, for example, when the pre-treatment is not performed, the critical dimensions of the BPSG minimum bar are approximately 15 nm, whereas the critical dimensions of the BPSG minimum bar are approximately 23 nm when the pre-treatment is performed. - According to an exemplary embodiment of the present invention, since a pre-treatment is performed when an insulation layer, e.g., BPSG, PSG, or BSG, is exposed during the formation of via holes and/or contact holes of a semiconductor device, the surface of the insulation layer may be induced to be densified. Due to the resulting dense surface of the insulation layer, loss of the insulation layer may be minimized during a subsequent cleaning process to thereby decrease the frequency of the generation of bridges and other defects.
- While the present invention has been described with respect to the specific exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
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CN107195620A (en) * | 2017-05-19 | 2017-09-22 | 睿力集成电路有限公司 | A kind of preparation method and structure of high aspect ratio hole |
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US7619310B2 (en) * | 2006-11-03 | 2009-11-17 | Infineon Technologies Ag | Semiconductor interconnect and method of making same |
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KR100262400B1 (en) * | 1995-11-20 | 2000-09-01 | 김영환 | Method of planarization semiconductor device |
KR100214073B1 (en) * | 1995-12-16 | 1999-08-02 | 김영환 | Bpsg film forming method |
KR100316603B1 (en) * | 1999-12-23 | 2001-12-12 | 황인길 | Method for manufacturing intermetal dielectric layer of semiconductor devices |
KR20050024010A (en) | 2003-09-04 | 2005-03-10 | 주식회사 하이닉스반도체 | Method for Manufacturing of Semiconductor Device |
KR20060099608A (en) | 2005-03-14 | 2006-09-20 | 주식회사 하이닉스반도체 | Method for fabricating pattern in semiconductor device |
KR20080092538A (en) | 2007-04-12 | 2008-10-16 | 주식회사 하이닉스반도체 | Contact manufacturing method of semiconductor device |
KR100965008B1 (en) | 2007-12-28 | 2010-06-21 | 주식회사 하이닉스반도체 | Method of forming isolation film of semiconductor memory device |
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US5592024A (en) * | 1993-10-29 | 1997-01-07 | Kabushiki Kaisha Toshiba | Semiconductor device having a wiring layer with a barrier layer |
US6008117A (en) * | 1996-03-29 | 1999-12-28 | Texas Instruments Incorporated | Method of forming diffusion barriers encapsulating copper |
US6376328B1 (en) * | 1999-06-01 | 2002-04-23 | Nec Corporation | Method for producing capacitor elements, and capacitor element |
US7619310B2 (en) * | 2006-11-03 | 2009-11-17 | Infineon Technologies Ag | Semiconductor interconnect and method of making same |
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CN107195620A (en) * | 2017-05-19 | 2017-09-22 | 睿力集成电路有限公司 | A kind of preparation method and structure of high aspect ratio hole |
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