KR100316603B1 - Method for manufacturing intermetal dielectric layer of semiconductor devices - Google Patents

Method for manufacturing intermetal dielectric layer of semiconductor devices Download PDF

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KR100316603B1
KR100316603B1 KR1019990061051A KR19990061051A KR100316603B1 KR 100316603 B1 KR100316603 B1 KR 100316603B1 KR 1019990061051 A KR1019990061051 A KR 1019990061051A KR 19990061051 A KR19990061051 A KR 19990061051A KR 100316603 B1 KR100316603 B1 KR 100316603B1
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film
bpsg film
bpsg
interlayer insulating
semiconductor device
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백승룡
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황인길
아남반도체 주식회사
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/0206Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02065Cleaning during device manufacture during, before or after processing of insulating layers the processing being a planarization of insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
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    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819Smoothing of the dielectric

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Abstract

층간 절연막으로 사용되는 BPSG막의 증착에서 불순물의 고농도화 및 치밀화 공정 온도의 저온화로 인해 발생할 수 있는 이상 입석출이나 습온에 의한 막 표면의 이상을 사전에 방지하여 층간 절연막의 막질을 안정적으로 유지시킬 수 있도록 하기 위하여, 각 정의된 반도체 소자 영역에 모스 소자가 형성된 실리콘웨이퍼 상부에 불순물이 도핑되지 않은 산화막을 적정 두께로 증착하고, APCVD 또는 SACVD 방식으로 TEOS계 BPSG막을 증착한 다음, 오존수 세정 처리를 통해 BPSG막 표면의 유기성 오염물을 분해하여 제거함과 동시에 BPSG막 표면에 불순물이 도핑되지 않은 산화막을 형성한다. 이후, BPSG막을 열처리하여 막질을 치밀화하고, 수용성 슬러리를 이용한 CMP로 평탄화하여 층간 절연막을 제조하는 것으로, BPSG막 증착 후 오존수 세정 처리를 통해 BPSG막 표면의 유기성 오염물을 분해하여 제거함과 동시에 BPSG막 표면에 불순물이 도핑되지 않은 산화막을 형성하므로 BPSG막 증착 후의 친수성인 막 표면을 소수성(疎水性)인 표면으로 전환시켜 공기중의 수분과의 반응으로 인한 막질 저하를 줄일 수 있을 뿐만 아니라 후속 공정과 연계하여 반도체 소자 내의 BPSG막에 대한 신뢰성을 향상시킬 수 있다.In the deposition of the BPSG film used as the interlayer insulating film, the film quality of the interlayer insulating film can be stably maintained by preventing the abnormality of the film surface due to the precipitation or the humid temperature, which may be caused by the high concentration of impurities and the low temperature of the densification process temperature. To this end, an oxide-doped oxide film is deposited to an appropriate thickness on the silicon wafer where the MOS device is formed in each defined semiconductor device region, and a TEOS-based BPSG film is deposited by APCVD or SACVD method, followed by ozone water cleaning. The organic contaminants on the surface of the BPSG film are decomposed and removed, and an oxide film which is not doped with impurities is formed on the surface of the BPSG film. Thereafter, the BPSG film is heat-treated to densify the film quality, and planarized to CMP using a water-soluble slurry to prepare an interlayer insulating film. After depositing the BPSG film, the organic contaminants on the surface of the BPSG film are decomposed and removed by ozone water cleaning. Since the oxide film is not doped with impurities, the hydrophilic film surface after the BPSG film deposition is converted into a hydrophobic surface to reduce the film quality deterioration due to the reaction with moisture in the air and is linked to subsequent processes. Thus, the reliability of the BPSG film in the semiconductor device can be improved.

Description

반도체 소자의 층간 절연막 제조 방법{METHOD FOR MANUFACTURING INTERMETAL DIELECTRIC LAYER OF SEMICONDUCTOR DEVICES}METHODS FOR MANUFACTURING INTERMETAL DIELECTRIC LAYER OF SEMICONDUCTOR DEVICES

본 발명은 반도체 소자를 제조하는 공정에 관한 것으로, 더욱 상세하게는 반도체 소자를 제조하는 공정중 실리콘웨이퍼와 금속 배선층, 금속 배선층과 금속 배선층 사이를 전기적으로 절연하기 위한 층간 절연막을 제조하는 방법에 관한 것이다.The present invention relates to a process for manufacturing a semiconductor device, and more particularly, to a method for manufacturing an interlayer insulating film for electrically insulating between a silicon wafer and a metal wiring layer, a metal wiring layer and a metal wiring layer during a semiconductor device manufacturing process. will be.

일반적으로 반도체 소자를 제조하는 공정에서 모스 소자가 형성된 실리콘웨이퍼와 금속 배선층과 금속 배선층, 금속 배선층과 금속 배선층 사이를 전기적으로 절연하기 위한 층간 절연막은 산화막을 증착하여 형성하게 되는데, 산화막의 증착시 금속 배선층 형성 이전의 평탄화, 나트륨 이온(Na+) 게터링(gettering) 등의 목적으로 붕소(B)나 인(P)을 함유하는 반응물을 첨가하여 SiO2-B2O3-P2O5의 BPSG(borophosphosilicate glass)을 형성하고 있다.In general, in the process of manufacturing a semiconductor device, an interlayer insulating film for electrically insulating a silicon wafer, a metal wiring layer and a metal wiring layer, and a metal wiring layer and a metal wiring layer having a MOS device formed thereon is formed by depositing an oxide film. SiO 2 -B 2 O 3 -P 2 O 5 was added by adding a reactant containing boron (B) or phosphorus (P) for the purpose of planarization before forming the wiring layer, and gettering of sodium ions (Na + ). It forms borophosphosilicate glass (BPSG).

그러면, 도 1a와 도 1b를 참조하여 종래 반도체 소자의 층간 절연막을 제조하는 방법을 개략적으로 설명한다.Next, a method of manufacturing an interlayer insulating film of a conventional semiconductor device will be described with reference to FIGS. 1A and 1B.

먼저 도 1a에 도시한 바와 같이, LOCOS(local oxidation of silicon) 공정에 의한 필드 산화막이나 STI(shallow trench isolation) 공정에 의한 트렌치(2) 등에 의해 소자 분리 영역이 정의된 실리콘웨이퍼(1)의 소자 영역에 게이트(G), 소스(S), 드레인(D)을 포함하는 N모스 또는 P모스 트랜지스터를 형성한다. 그리고, N모스 또는 P모스 트랜지스터의 역할을 위해 티타늄(Ti) 스퍼터(sputter) 및 실리사이드(silicide) 형성 공정 이후, 실리콘웨이퍼(1)에 바로 BPSG막이 접촉할 경우 불순물인 붕소나 인이 실리콘에 침투할 수가 있으므로 실리콘웨이퍼(1) 전면에 불순물이 도핑(doping)되지 않은 산화막(3)을 약 1000Å 내지 1500Å의 두께로 증착한다.First, as shown in FIG. 1A, an element of a silicon wafer 1 in which an element isolation region is defined by a field oxide film by a LOCOS process, a trench 2 by a shallow trench isolation (STI) process, or the like. An N-MOS or P-MOS transistor including a gate G, a source S, and a drain D is formed in the region. In addition, after the process of forming a titanium sputter and silicide for the role of an NMOS or PMOS transistor, boron or phosphorus, which is an impurity, penetrates into silicon when the BPSG film contacts the silicon wafer 1 directly. Since it is possible to do so, an oxide film 3 having no impurities doped on the entire surface of the silicon wafer 1 is deposited to a thickness of about 1000 kW to 1500 kW.

이후, 금속 배선층 형성 이전의 평탄화, 나트륨 이온 게터링 등의 목적으로 실리콘웨이퍼(1) 전면에 TEOS(tetraethylorthosilicate)계 BPSG막(4)을 APCVD(atmospheric pressure chemical vapor deposition) 또는 SACVD(sub-atmospheric chemical vapor deposition) 방식으로 일정 온도 및 압력하에서 화학식 1에서의 반응에 의해 증착한다.Subsequently, a tetraethylorthosilicate (TEOS) -based BPSG film 4 is deposited on the front surface of the silicon wafer 1 for the purpose of planarization before forming the metal wiring layer, sodium ion gettering, or the like, or an APCVD (sub-atmospheric chemical). vapor deposition) by a reaction in Chemical Formula 1 at a constant temperature and pressure.

TEOS(as-deposited) + TMP(trimethylphosphite) + TMB(trimethylborate)TEOS (as-deposited) + TMP (trimethylphosphite) + TMB (trimethylborate)

(SiO2+ B2O3+ P2O5) + By-products (SiO 2 + B 2 O 3 + P 2 O 5 ) + By-products

그리고, BPSG막(4)이 증착된 실리콘웨이퍼(1)를 퍼니스(furnace)에 장입하여 700℃ 내지 750℃의 질소 가스(N2) 분위기에서 40분 내지 50분동안 BPSG막(4)의 치밀화(densify) 공정을 실시하여 후속 공정을 위한 안정된 망상조직(network structure)을 가지도록 하며, 양호한 평탄화 정도를 갖도록 한다.Then, the silicon wafer 1 on which the BPSG film 4 is deposited is charged into a furnace to densify the BPSG film 4 for 40 to 50 minutes in a nitrogen gas (N 2 ) atmosphere of 700 ° C to 750 ° C. The densify process is carried out to have a stable network structure for subsequent processes and to have a good degree of planarization.

그 다음 도 1b에 도시한 바와 같이, 수용성 슬러리(slurry)를 이용하여 후속 공정을 위해 필요로 하는 일부 두께를 남기고 BPSG막(4)을 CMP(chemical mechanical polishing)하여 최종적으로 평탄화된 층간 절연막을 완성한다.Then, as shown in FIG. 1B, the BPSG film 4 is chemically mechanically polished (CMP), leaving some thickness required for the subsequent process using a water-soluble slurry to complete the finally planarized interlayer insulating film. do.

이와 같은 종래의 층간 절연막 제조 방법에서, APCVD 또는 SACVD 방식으로 증착된 BPSG막 들은 증착 후 대기에 장시간 노출되게 되면 친수성(親水性)인 본래의 성질로 인해 공기중의 수분과 반응하게 되며, 이때 BPSG막의 표면에서는 다음의 화학식 2에서와 같은 반응에 의해 붕산(H3PO4)과 인산(H3PO4, H3PO3)이 형성되게 된다.In the conventional method of manufacturing an interlayer insulating film, BPSG films deposited by APCVD or SACVD methods react with moisture in the air due to their inherent hydrophilic properties when exposed to air for a long time after deposition. On the surface of the film, boric acid (H 3 PO 4 ) and phosphoric acid (H 3 PO 4 , H 3 PO 3 ) are formed by a reaction as in the following Chemical Formula 2.

P2O5+ 3H22H3PO4,P 2 O 5 + 3H 2 2H 3 PO 4 ,

P2O3+ 3H22H3PO3,P 2 O 3 + 3H 2 2H 3 PO 3 ,

B2O3+ 3H22H3BO3 B 2 O 3 + 3 H 2 2 H 3 BO 3

그리고, 만약 BPSG막 표면에 이런 산성 파티클(particle, 붕산과 인산)이 성장한 상태에서 치밀화 공정을 진행하게 되면, 다음의 화학식 3에서와 같은 반응에 의해 붕산과 인산이 H2O를 잃으며 서로 반응하여 BPO4라는 이상(異常) 입석출(粒析出)을 형성하게 된다.And, if the densification process is performed in the state in which such acid particles (particles, boric acid and phosphoric acid) is grown on the surface of the BPSG film, boric acid and phosphoric acid loses H 2 O by the reaction as shown in the following formula (3) As a result, BPO 4 forms abnormal granules.

H3BO3+ H3PO4BPO4·3H2O(soluble) H 3 BO 3 + H 3 PO 4 BPO 4 · 3H 2 O (soluble)

BPO4·3H2BPO4(insoluble) + 3H2OBPO 4 3H 2 BPO 4 (insoluble) + 3H 2 O

이러한 BPO4의 이상 입석출은 후속 콘택(contact)이나 비아(via) 패턴 형성을 위한 사진 식각 공정시 임계 선폭(critical dimension) 사이즈의 변화나 식각시에 블록킹(blocking) 등의 문제를 유발시킬 수 있으며, 또한 후속 평탄화를 위한 CMP 공정에서 실리콘웨이퍼 표면에 스크래치(scratch)를 유발할 수도 있다.Such abnormal deposition of BPO 4 may cause problems such as changing of critical dimension size or blocking during etching in the photolithography process for forming subsequent contact or via patterns. It may also cause scratches on the silicon wafer surface in a CMP process for subsequent planarization.

본 발명은 이와 같은 문제점을 해결하기 위한 것으로, 그 목적은 층간 절연막으로 사용되는 BPSG막의 증착에서 불순물의 고농도화 및 치밀화 공정 온도의 저온화로 인해 발생할 수 있는 이상 입석출이나 습온에 의한 막 표면의 이상을 사전에 방지하여 층간 절연막의 막질을 안정적으로 유지시킬 수 있도록 하는 반도체 소자의 층간 절연막 제조 방법을 제공하는 데 있다.The present invention has been made to solve the above problems, and its object is that abnormality of the surface of the film due to precipitation or wet temperature may occur due to the high concentration of impurities and the low temperature of the densification process in the deposition of the BPSG film used as the interlayer insulating film. The present invention provides a method for manufacturing an interlayer insulating film of a semiconductor device, which can prevent the film in advance, thereby stably maintaining the film quality of the interlayer insulating film.

도 1a와 도 1b는 종래의 방법에 따라 반도체 소자의 층간 절연막을 제조하는 방법을 개략적으로 도시한 공정도이고,1A and 1B are process diagrams schematically showing a method of manufacturing an interlayer insulating film of a semiconductor device according to a conventional method,

도 2a 내지 도 2d는 본 발명의 일 실시예에 따라 반도체 소자의 층간 절연막을 제조하는 방법을 개략적으로 도시한 공정도이다.2A to 2D are process diagrams schematically illustrating a method of manufacturing an interlayer insulating film of a semiconductor device according to an embodiment of the present invention.

상기와 같은 목적을 달성하기 위하여, 본 발명은 실리콘웨이퍼 상부에 TEOS계 BPSG막을 증착하고, BPSG막을 열처리하여 막질을 치밀화하기 전, BPSG막 표면을 오존수 세정 처리하여 BPSG막 표면의 유기성 오염물을 제거함과 동시에 BPSG막 표면에 불순물이 도핑되지 않은 산화막을 형성하는 것을 특징으로 한다.In order to achieve the above object, the present invention is to deposit a TEOS-based BPSG film on the silicon wafer, and before the heat treatment of the BPSG film to densify the film quality, the surface of the BPSG film is washed with ozone water to remove organic contaminants on the surface of the BPSG film and At the same time, an oxide film which is not doped with impurities is formed on the surface of the BPSG film.

이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명의 일 실시예에 따라 반도체 소자의 층간 절연막을 제조하는 방법을 개략적으로 도시한 공정도이다.2A to 2D are process diagrams schematically illustrating a method of manufacturing an interlayer insulating film of a semiconductor device according to an embodiment of the present invention.

먼저 도 2a에 도시한 바와 같이, LOCOS 공정에 의한 필드 산화막이나 STI 공정에 의한 트렌치(12) 등에 의해 소자 분리 영역이 정의된 실리콘웨이퍼(11)의 소자 영역에 게이트(G), 소스(S), 드레인(D)을 포함하는 N모스 또는 P모스 트랜지스터를 형성한다. 그리고, N모스 또는 P모스 트랜지스터의 역할을 위해 티타늄 스퍼터 및 실리사이드 형성 공정 이후, 실리콘웨이퍼(11)에 바로 BPSG막이 접촉할 경우 불순물인 붕소나 인이 실리콘에 침투할 수가 있으므로 실리콘웨이퍼(11) 전면에 불순물이 도핑되지 않은 산화막(13)을 약 1000Å 내지 1500Å의 두께로 증착한다.First, as shown in FIG. 2A, the gate G and the source S are formed in the device region of the silicon wafer 11 in which the device isolation region is defined by the field oxide film by the LOCOS process, the trench 12 by the STI process, or the like. An N-MOS or P-MOS transistor including a drain D is formed. After the titanium sputtering and silicide formation process for the role of N-MOS or P-MOS transistors, boron or phosphorus as impurities may penetrate into silicon when the BPSG film is directly in contact with the silicon wafer 11, so that the front surface of the silicon wafer 11 may be The oxide film 13 which is not doped with impurities is deposited to a thickness of about 1000 mW to 1500 mW.

이후, 금속 배선층 형성 이전의 절연, 평탄화, 나트륨 이온 게터링 등의 목적으로 실리콘웨이퍼(11) 전면에 TEOS계 BPSG막(14)을 일 예로 APCVD 또는 SACVD 방식으로 일정 온도 및 압력하에서 화학식 4에서와 같은 반응에 의해 증착한다.Subsequently, the TEOS-based BPSG film 14 is formed on the silicon wafer 11 in front of the silicon wafer 11 for the purpose of insulation, planarization, sodium ion gettering, etc. before forming the metallization layer. Deposit by the same reaction.

(SiO2+ B2O3+ P2O5) + By-products (SiO 2 + B 2 O 3 + P 2 O 5 ) + By-products

그 다음 도 2b에 도시한 바와 같이, BPSG막(14) 증착 후의 불순물 농도에 따른 이상 입석출 및 흡습성을 최소화시키기 위하여 BPSG막(14) 표면의 소수성(疎水性)을 목적으로 오존수(O3/DIW(deionized water)) 세정 처리를 실시한다. 그러면 BPSG막(14)의 증착 공정에서 발생된 부산물(By-products) 즉, 유기성 오염물이 오존수 세정에 의해 제거되고 BPSG막(14)의 표면층에는 BPSG막(14)과 대기의 접촉을 방지하는 대기 접촉 방지막으로써 불순물이 도핑되지 않은 산화막(15)이 형성된다.Then, as shown in FIG. 2B, ozone water (O 3 / O) is used for the purpose of hydrophobicity on the surface of the BPSG film 14 in order to minimize abnormal precipitation and hygroscopicity according to the impurity concentration after the deposition of the BPSG film 14. DIW (deionized water) washing process is performed. Then, by-products (i.e., organic contaminants) generated in the deposition process of the BPSG film 14 are removed by ozone water washing, and the surface layer of the BPSG film 14 prevents contact between the BPSG film 14 and the atmosphere. As the contact preventing film, an oxide film 15 which is not doped with impurities is formed.

따라서, BPSG막(14) 표면의 산화막(15)이 BPSG막(14)과 대기상의 수분(H2O)과의 반응을 사전에 차단하여 장시간 BPSG막(14)이 대기중에 노출되어도 붕소, 인의 불순물 농도에 따른 흡습성을 최소화할 수 있으며, 이에 따라 산성화로 인한 이상 입석석출의 발생을 방지할 수 있어 안정적인 절연막 성질을 유지할 수 있고, 후속 공정에의 연결성 측면에서 공정 결함없이 신뢰성을 확보할 수 있다.Therefore, the oxide film 15 on the surface of the BPSG film 14 blocks the reaction between the BPSG film 14 and moisture (H 2 O) in the air in advance, so that even if the BPSG film 14 is exposed to the air for a long time, Hygroscopicity according to the impurity concentration can be minimized, thereby preventing abnormal standing precipitation due to acidification, thereby maintaining stable insulating film properties and ensuring reliability without process defects in terms of connectivity to subsequent processes. .

또한, 불순물 농도에 따른 공정 마진(margin)을 넓힐 수 있으므로, 종래에는 APCVD 또는 SACVD 방식으로의 BPSG막의 흡습성 때문에 붕소, 인 불순물을 관리하는 데 어려움이 있었으나 원하는 공정 특성 및 나트륨 이온과 같은 알칼리 이온의 게터링 효과를 얻는 데 붕소, 인의 불순물 농도를 일부 증가시킬 수 있다.In addition, since process margins can be widened according to impurity concentrations, it is difficult to manage boron and phosphorus impurities due to hygroscopicity of BPSG film in APCVD or SACVD method, but desired process characteristics and alkali ions such as sodium ions In order to obtain a gettering effect, some of the impurity concentrations of boron and phosphorus may be increased.

그 다음 도 2c에 도시한 바와 같이, 실리콘웨이퍼(11)를 퍼니스에 장입하여 700℃ 내지 750℃의 질소 가스 분위기에서 40분 내지 50분 동안의 열처리에 의해 BPSG막(14)의 치밀화 공정을 실시하여 후속 공정을 위한 안정된 망상조직을 가지도록 하며, 양호한 평탄화 정도를 갖도록 한다.Then, as shown in FIG. 2C, the silicon wafer 11 is charged into the furnace to perform a densification process of the BPSG film 14 by heat treatment for 40 to 50 minutes in a nitrogen gas atmosphere of 700 ° C to 750 ° C. To have a stable network for subsequent processes and to have a good degree of planarization.

그 다음 도 2d에 도시한 바와 같이, 수용성 슬러리를 이용하여 후속 공정을 위해 필요로 하는 일부 두께를 남기고 BPSG막(14)을 CMP하여 최종적으로 평탄화된 층간 절연막을 완성한다.Then, as shown in FIG. 2D, the BPSG film 14 is CMP to leave a partial thickness required for the subsequent process using a water-soluble slurry to complete the finally planarized interlayer insulating film.

이와 같이 본 발명은 BPSG막 증착 후 오존수 세정 처리를 통해 BPSG막 표면의 유기성 오염물을 제거하고 BPSG막 표면에 불순물이 도핑되지 않은 산화막을 형성하므로 TEOS계 BPSG막의 불순물 변화 및 치밀화 공정 온도의 저온화로 인한 막질의 변화를 안정적으로 유지하여 BPO4등과 같은 이상 입석출의 발생을 최소화시킬 수 있으며, BPSG막 증착 후의 친수성인 막 표면을 소수성인 표면으로 전환시켜 공기중의 수분과의 반응으로 인한 막질 저하를 줄일 수 있을 뿐만 아니라 후속 공정과 연계하여 반도체 소자 내의 BPSG막에 대한 신뢰성을 향상시킬 수 있다.As described above, the present invention removes organic contaminants on the surface of the BPSG film through the ozone water cleaning process after the deposition of the BPSG film, and forms an oxide film which is not doped with impurities on the surface of the BPSG film. By maintaining the change of film quality stably, it can minimize the occurrence of abnormal precipitation such as BPO 4 , and convert the hydrophilic film surface after hydrophobic BPSG film into hydrophobic surface to reduce the film quality caused by reaction with moisture in the air. In addition to the reduction, the reliability of the BPSG film in the semiconductor device can be improved in connection with subsequent processes.

Claims (3)

각 정의된 반도체 소자 영역에 모스 소자가 형성된 실리콘웨이퍼 상부에 TEOS계 BPSG막을 증착하는 단계와;Depositing a TEOS-based BPSG film on a silicon wafer having a MOS device formed in each defined semiconductor device region; 상기 BPSG막을 열처리하여 막질을 치밀화하는 단계와;Heat-treating the BPSG film to densify the film quality; 상기 BPSG막을 수용성 슬러리를 이용한 CMP로 평탄화하는 단계를 포함하되,Planarizing the BPSG film with CMP using a water-soluble slurry, 상기 BPSG막을 열처리하여 막질을 치밀화하는 단계 이전에, 상기 BPSG막 표면을 오존수 세정 처리하여 BPSG막 표면의 유기성 오염물을 제거함과 동시에 BPSG막 표면에 불순물이 도핑되지 않은 산화막을 형성하는 단계를 더 포함하는 반도체 소자의 층간 절연막 제조 방법.Prior to the heat treatment of the BPSG film to densify the film quality, the surface of the BPSG film is ozone-water cleaned to remove organic contaminants on the surface of the BPSG film and to form an oxide film without impurities on the surface of the BPSG film. Method for manufacturing an interlayer insulating film of a semiconductor device. 제 1 항에 있어서, 각 정의된 반도체 소자 영역에 모스 소자가 형성된 실리콘웨이퍼 상부에 TEOS계 BPSG막을 증착하는 단계 이전에, 상기 실리콘웨이퍼 상부에 불순물이 도핑되지 않은 산화막을 적정 두께로 증착하는 단계를 더 포함하는 반도체 소자의 층간 절연막 제조 방법.The method of claim 1, further comprising depositing an oxide-doped oxide film on the silicon wafer to an appropriate thickness before depositing a TEOS-based BPSG film on the silicon wafer having the MOS device formed in each defined semiconductor device region. An interlayer insulating film manufacturing method of a semiconductor device further comprising. 제 1 항 또는 제 2 항에 있어서, 상기 TEOS계 BPSG막의 증착은, APCVD 또는 SACVD 방식에 의해 증착하는 반도체 소자의 층간 절연막 제조 방법.The method for manufacturing an interlayer insulating film of a semiconductor device according to claim 1 or 2, wherein the TEOS-based BPSG film is deposited by APCVD or SACVD.
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