TW434800B - Method for forming shallow trench isolation on a semiconductor chip - Google Patents

Abstract

The present invention provides a method for forming shallow trench isolation on a semiconductor chip including a silicon substrate, a pad oxide layer installed on the surface of the silicon substrate, a SiN layer installed on the pad oxide layer, and at least a shallow trench installed on a specified region on the surface of the silicon substrate. The method comprises forming a SiO2 layer on the surface of the semiconductor chip covering the sidewall and the bottom of the shallow trench; introducing a nitrogen-containing gas and performing a rapid thermal process (RTP) to dope nitrogen atoms in the nitrogen-containing gas into the SiO2 layer thereby forming a nitrogen-containing SiO2 layer; forming at least a dielectric layer on the surface of the nitroge-containing SiO2 layer while filling up the trench; performing a chemical mechanical polishing to align the surface of the dielectric layer in the shallow trench with the surface of the SiN layer; and using a wet etching process to peel off the SiN layer and the pad oxide layer to complete the production of the shallow trench.

Description

V. Description of the invention (1) The field of invention refers to the particularly shallow trench. The second layer of silicon silicon is used to produce oxygen, and the second one is composed of a shallow bottom with a partitioned trench and a wall for the side. Ming trench . The shallow method is described in a variety of backgrounds. In the current semiconductor manufacturing process, localized oxidation isolation (LOCOS) or shallow trench isolation (STI) is generally used to control semiconductors. The various electronic components on the ship's chip are insulated and isolated 'to avoid short circuits or parasitic capacitance. For semiconductor processes with a minimum process line width of 0-25 mm, the shallow trench isolation method with good electrical isolation and high component integration can be used as various electronic components. Inter-electrical isolation technology, so shallow trench isolation has gradually become the mainstream of the current semiconductor device isolation process. Please refer to FIG. 1. FIG. 1 is a schematic diagram of a CMOS device 20 using a trench 26 to isolate the PMOS device 22 and the NMOS device 24. In the current memory manufacturing process, a trench 26 between the PM0S element 22 and the NMOS element 24 is dug out of the surface of the CM & element 20 by dry etching and the like, and a dielectric material is filled. If the depth of the trench 26 exceeds the well depth of the double-twisted (tw'in ^ 113) structure (^ 〇3 element 20) ((1 邛 1; 11〇 丨 心 11) 28, that is,

Page 4 434800 V. Description of the invention (2) PM0S element 22 and NMOS element 24 can be successfully isolated to prevent latch-up. In addition, the shallow trench isolation (STI) method can greatly reduce the spacing of the PM0S element 22 and the NM0S element 24, thereby increasing the integration degree of very large scale integration (VLSI). Therefore, in order to deposit a layer of shallow trench isolation (STI) with good step coverage and no voids, most current VLSI processes are based on high density plasma chemical vapor deposition (HDP CVD). ) To make a dielectric layer in shallow trench isolation (STI). The HDP dielectric layer formed by the HDPCVD method has excellent step coverage and good conformity, which can easily overcome the difficulty of filling the silicon oxide layer with a high aspect ratio. The problem of steep topography (severe topography) further fills shallow trenches between semiconductor devices or gaps between metal lines. Please refer to FIG. 2 and FIG. 3. FIG. 2 and FIG. 3 are schematic diagrams of a conventional process for making a shallow trench 40 on a semiconductor wafer 30. A semiconductor wafer 30 includes a silicon substrate 32 and a silicon oxide layer (sU icon oxide) 34 of several hundred angstroms (λ). The silicon wafer 32 is disposed on the silicon substrate 32 and is used as a pad oxide layer. oxide), and a silicon nitride layer 3 6 are deposited on the silicon oxide layer 3 4 for subsequent chemical mechanical polishing (CMP)

434800 V. Description of the invention (3) Stoplayer® in the process The conventional method for making the shallow trench 40 is to first coat a photoresist layer 38 'on the surface of the semiconductor wafer 30 and use a lithography process to The pattern and position of the shallow trenches 40 are defined on the photoresist layer 38. An anisotropic dry etching process is then performed to remove the silicon nitride layer 36, the silicon oxide layer 34, and the silicon substrate 32 'of a predetermined depth to form a shallow trench 40, which is not covered by the photoresist layer 38. Please refer to Figure 3. Figure 3 is a schematic diagram of conventional shallow trench isolation. 〇 Subsequently, HDPCVD is performed in a high-density plasma environment with tetra-ethyl-ortho-silicate (Si (0C2H5)). 4. TEOS) is a reactive gas. A low dielectric constant (low k) silicon oxide layer 42 is deposited on the surface of the dream substrate 32, and the shallow trench 40 is filled. Then, a silicon dioxide layer 42 is planarized by using a CMP process and an appropriate slurry. After the planarization process, the silicon oxide layer 42 in the shallow trench 40 is approximately aligned with the surface of the silicon nitride layer 36. Finally, a wet etch process is used to sequentially place the silicon nitrogen on the surface of the semiconductor wafer 30 with a phosphoric acid (Η3Ρ04) heated to about 140 ° C and a standard cleaning solution (SC-1). The layer 36 and the silicon oxide layer 34 are completely stripped to complete the shallow trench isolation process. ; Please refer to Figures 4 and 5, Figures 4 and 5 are schematic diagrams of the conventional gate manufacturing process. The conventional method of gate manufacturing is to complete the shallow trench isolation process.

5. Description of the invention (4) After "4", that is, after the active area is defined on the surface of the semiconductor wafer 30, the silicon on the surface of the active area is oxidized to a thickness of about 100 to 25 Angstroms by dry oxidation. Silicon oxide (SiOD) forms a silicon-oxygen layer 44. Then, a poly-crystalline silicon (poly si 1 icon) layer 46 is deposited on the silicon-oxygen layer 44 by a LPCVD method to a thickness of about 2000 to 300,000 angstroms. A diffusion method or an ion implantation method incorporates a high concentration of dopant into the polycrystalline silicon layer 46, thereby reducing the resistivity of the polycrystalline silicon layer 46 and increasing the conductivity of the gate 50 conductive layer to be formed subsequently. A yellow light process is performed, and the position of the gate electrode 50 is defined by the photoresist layer 43. Then, the polycrystalline Mengguang 4 6 and Meng oxygen 4 4 which are not protected by the photoresist layer 43 are removed by a dry etch method Then, the photoresist layer 4 3 is peeled off. After the etching, the remaining polycrystalline silicon layer 46 forms a gate conductive layer, and the remaining stone oxide layer 4 4 forms a gate oxide layer, constituting the main body of the gate 50. The structure β then reuses the yellow light and the ion implantation process to place the semiconductor wafer 30 Each gate 50 structure on the surface forms a PM0S element and a NMOS element. However, the standard silicon cleaning solution (SC-1) is used to completely strip the nitrogen silicon layer 36 and silicon oxide layer 34 on the surface of the semiconductor wafer 30. During the process, the joint between the shallow trench 40 and the silicon substrate 32 will also be continuously etched, so that the joint between the shallow trench 40 and the silicon substrate 32 will form a certain angle 45, which will be subsequently During the deposition of the doped polycrystalline silicon layer 46 and the etching process that defines the gate 50, the doped polycrystalline silicon layer 46 will remain at the corner 45, and a doped polycrystalline silicon wire is formed around the shallow trench 40, so that each electronic component Incomplete electrical isolation is formed between them, and the electrical isolation effect of shallow trench isolation is lost.

434800 V. Description of the invention (5) And as the cut-off 45 becomes more severely eroded, the phenomenon of incomplete electrical isolation between the electronic components caused by the cut-off 45 remaining doped polycrystalline silicon becomes more apparent. This phenomenon of incomplete electrical isolation is quite likely to cause a short circuit or form a high leakage current ', which leads to a reduction in the threshold voltage Vt (threshold voltage) of the M0S transistor device. In addition, for dynamic random access memory (DRAM), 'high leakage current will cause the capacitance in the memory cell to have a short retention time, that is, access to the memory The intracellular signal " 1 " will cause the signal to change to " 0 " due to the higher leakage current, resulting in an excessively high refresh frequency (refresh frequency) reducing performance and even causing data loss. In addition, a PM0S In the transistor, because boron ions have a tendency to diffuse to the silicon oxide layer 22 in the shallow trench 20, the doped boron ions are easily diffused into the silicon oxide layer 22 through the silicon substrate 12 to reduce the PM0S transistor. The number of doped boron ions' increases the resistance and affects the start of the PM0S transistor 丨 voltage V, | Summary of the invention

I | The main purpose of the present invention is to provide a manufacturing method for forming a silicon dioxide layer containing nitrogen on the sidewall and bottom of a shallow trench, and utilizing the nitrogen dioxide

434800 V. Description of the invention (6) —— one by one — ———. — = The strong bonding characteristics of the layer ’in order to solve the shortcomings of the above-mentioned conventional techniques. The present invention provides a shallow trench isolator I for a semiconductor wafer. The semiconductor wafer includes a silicon substrate, a pad oxide layer is disposed on the surface of the silicon substrate, a nitrogen silicon layer is disposed on the pad oxide layer, and at least one shallow trench is provided in a predetermined area on the surface of the silicon substrate. The method of the present invention is to form a < oxidation on the surface of the semiconductor wafer, cover the sidewalls and bottom of the shallow trench, and then pass a nitrogen-containing gas into a rapid thermal process (RTP), so that the An argon-containing gas ^ 的 nitrogen atom # enters the dioxide dream layer 'to form a nitrogen-containing dioxide layer β and then forms at least one dielectric layer on the surface of the nitrogen-containing silicon dioxide layer, and simultaneously fills the dielectric layer. Shallow trench. Finally, a chemical mechanical polishing (CMP) process is performed to align the surface of the dielectric layer in the shallow trench with the surface of the silicon nitride layer, and then a wet etching process is used to strip the silicon nitride layer and the pad. An oxide layer completes the shallow trench process. Since the side wall and bottom of the shallow trench are composed of a nitrogen-containing dioxide layer, and nitrogen atoms can fill the dangle bonds and unsaturated bonds in the molecules of the dioxide under a high temperature environment, so the The nitrogen-containing silicon dioxide layer will be more dense in structure, which can greatly improve the corner phenomenon of the silicon substrate and the corners above the shallow trench, while reducing the effect of leakage current. And for PM0S transistor, because there is a nitrogen-containing dream dioxide layer between the silicon substrate and the broken oxygen layer in the shallow trench, the PM0S transistor is replaced by Zhao.

4348 0 0 V. Description of the invention (7) The shed ions are not easily missed through infiltration, which affects the electrical performance of the pMOS transistor. For a detailed description of the invention, please refer to 26 and 27. FIGS. 6 and 7 are schematic diagrams of a method for making a shallow trench isolation on a semiconductor wafer 60 according to the present invention. As shown in Figure 26, the semiconductor wafer 60 includes a siiicorl substrate 62, a pad oxide 64 is provided on the surface of the silicon substrate 62, and a silicon nitride (SixNy) 66 is provided. Above the pad oxide layer 64, a shallow trench 68 is provided in a predetermined area on the surface of the silicon substrate 62. The shallow trench 68 penetrates the silicon nitride layer 66 and the pad oxide layer 64 and penetrates the silicon substrate 62 to a predetermined depth. The method of the present invention first performs a chemical vapor deposition (CVD) process to form a thickness of about 65 Angstroms (about) to 100 Angstroms (厶) on the surface of the semiconductor wafer 60. Silicon (silicon dioxide) layer 70. The silicon dioxide layer 70 uniformly covers the surface of the semiconductor wafer 60 and the sidewalls and bottom surfaces of the shallow trenches 68. Next, a nitrogen-containing gas is passed in and a rapid heating process (RTP) is performed, so that the nitrogen-containing gas is thermally cracked to produce I, and is incorporated into the silicon dioxide layer 70 to form a nitrogen-containing silicon dioxide. Layer β. The nitrogen-containing gas may be nitrous oxide (N2O), nitric oxide (NOtric oxide), or amroonia (NH3).

^ 3Δ8 005. Description of the invention (8) As shown in Fig. 7 ', a high density plasma chemical vapor deposition (HDP CVD) process is performed on a silicon nitride layer containing nitrogen. 7 A dielectric layer 74 made of silicon oxide is formed on the 0 surface. Since the silicon oxide deposited by the HDPCVD method has excellent step coverage and good conformity, the dielectric layer 74 completely fills the shallow trench 68. Next, a chemical mechanical polishing (CMP) process is performed to remove the dielectric layer 74 and the nitrogen-containing silicon dioxide layer 70 on the surface of the semiconductor wafer 60 outside the shallow trench 68. The surface of the dielectric layer 74 in the shallow trench 6 8 Λ is approximately aligned with the surface of the silicon nitride layer 66. Among them, the nitrogen silicon layer j · 66 is used as a stop j layer in the chemical mechanical polishing process. Finally, a wet etch process is performed with a heat heated to about 140 ° C. Fill with acid (phosphoric acid (H3P〇4)) and standard cleaning solution (SC-1) in order to completely strip the silicon nitride layer 66 and pad oxide layer 64 on the surface of the semiconductor wafer 60 in order to complete the shallow trench isolation. Production.

I Because in the process of making the silicon dioxide layer 70 containing nitrogen, 'the rapid heating process (RTP) can crack a large amount of nitrogen atoms from the thorium-containing gas, so that the nitrogen atoms can fill the silicon dioxide layer 70 A dangle bond or an unsaturated bond forms a nitrided silicon dioxide layer 70 containing nitrogen. In addition, the nitrogen dioxide fragmentation layer 7 formed on the side wall and the bottom of the shallow trench 68 is structurally more oxidized than the one containing no atmosphere.

P. 11 4348 00 5 'Explanation of the invention (9) is dense' and does not cause thermal stress problems such as those caused by nitride layers. : This results in the formation of photoresist, stripping, and engraving on the surface of the semiconductor wafer 60 repeatedly to perform the pM〇 ^ NM〇s device implantation process, the seam between the shallow groove 68 and the dream substrate 62 Will not be easily etched, forming corners. Please refer to FIG. 8 and FIG. 9 after the completion of the shallow trench isolation 68. Then, a thermal oxidation process is performed on the surface of the silicon substrate 62 to form a two-manganese oxide layer 18 and a doped polycrystalline silicon oxide layer. 80 is above the Shi Xi oxygen layer 78. Then, a patterned photoresist layer 82 is formed on the surface of the polycrystalline stone layer 80 to define the positions of the gates 86. Finally, the photoresist layer 82 is used as a hard mask, and an etching process and a photoresist removal process are performed. Process to complete the production of gate 86. Because the formation of the nitrogen-containing silicon dioxide layer greatly improves the shallow trench isolation and the corner defect phenomenon, the subsequent doping of the polycrystalline dream layer U = will not cause the residual problem of the doped polycrystalline silicon wire to be avoided, thereby avoiding The higher leakage current affects the electrical properties of the MoS transistor, or the loss of access to the data ... For the = S, due to the dream oxygen layer 74-1 in the silicon substrate 62 and the shallow trench 68 The silicon dioxide layer 70 isolates the two, so PMot = ions cannot penetrate into the oxide dream layer 74. Compared with the conventional silicon oxide layer made of shallow trench isolation f :::: Shallow trench isolation process. The process of the present invention is on the surface of the shallow trench, that is, the silicon substrate and the shallow trench.

/ 13 ^ 800 5. In the description of the invention (ίο), a dense silicon dioxide layer containing nitrogen is formed to prevent the erosion and damage of the processes such as photoresist, etching, and ion implantation liquid, so as to avoid A chipping phenomenon occurs at the joint between the silicon substrate and the shallow trench, which affects the performance of the components on the semiconductor wafer and improves the throughput. The above description is only a preferred embodiment of the present invention, and any equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of patent coverage of the present invention.

L 3 L 9 A > u. I Schematic description of the diagram, the brief description of the diagram. Figure 1 is a schematic diagram of the structure of the CMOS device. Figure 2 and Figure 3 are the schematic diagrams of semiconductors. Six and twenty-seven are the shallow illustrations of the invention for making the figure eight and nine are the explanatory diagrams of the symbols for making the gate of the invention. A schematic diagram of a process for making a shallow trench on a wafer. Schematic of trench isolation process. Schematic diagram of the process. 20 CMOS element 22 24 NM0S element 26 28 Well depth 30 32 Silicon substrate 34 36 Nitrogen silicon layer 38 40 Shallow trench 42 43 Photoresistive layer 44 45 Notch 46 50 Gate 60 62 Broken substrate 64 66 Nitrogen silicon layer 68 70 Silicon dioxide Layer 74 78 silicon oxide layer 80 PM0S element trench semiconductor wafer silicon oxide layer photoresist layer nitrogen silicon layer silicon oxide layer polycrystalline broken layer semiconductor wafer pad oxide layer shallow trench silicon oxide layer polycrystalline silicon layer

434800 Brief description of the diagram 82 Photoresistive layer 86 Gate

15th I

Claims (1)

434800 VI. Scope of patent application 1. A method for shallow trench isolation (STI) on a semiconductor wafer. The semiconductor wafer includes a silicon substrate and at least _ shallow trench (shallow trench) is disposed in a predetermined area on the surface of the silicon substrate. The method includes the following steps: forming a nitrogen-containing silicon dioxide layer on the surface of the semiconductor wafer and covering the shallow trench A sidewall and a bottom; forming at least one dielectric layer on the surface of the nitrogen-containing dioxide dioxide layer to fill the shallow trench; and i performing a planarization process to make the surface of the dielectric layer in the shallow trench and the silicon The surface of the substrate is cut in a straight line, and the nitrogen-containing silicon dioxide layer located outside the shallow trench is removed. I 2_ The method of claim 1, wherein the method for forming the nitrogen-containing silicon dioxide layer includes the following steps: A chemical vapor deposition (CVD) process is performed on the surface of the semiconductor wafer. A silicon dioxide (Si02) layer is formed to cover the sidewall and bottom of the shallow trench; and a rapid thermal process (RTP) is performed, and a nitrogen-containing gas is passed into the Nitrogen atoms in a nitrogen body are doped into the silicon dioxide layer to form the nitrogen-containing silicon dioxide layer. -3. The method according to item 2 of the scope of patent application, wherein the nitrogen-containing gas is oxygen 434800 6. Scope of patent application Nitrous oxide (N2〇). 4. The method according to item 2 of the scope of patent application, wherein the nitrogen-containing gas is nitric oxide (NO). 5. The method according to item 2 of the patent application, wherein the nitrogen-containing gas is ammonia gas (ammonia, NH3) ° 6. The method according to item 1 of the patent application, wherein the nitrogen-containing silicon oxide layer is formed. The method is to perform a thermal oxidation process and in-situ pass nitrous oxide (N20) gas to form the nitrogen-containing silicon dioxide layer on the surface of the semiconductor wafer. * 7. The method according to item 1 of the scope of patent application, wherein the dielectric layer is composed of silicon oxide. The method according to item 1 of the patent application scope, wherein the planarization process is a two chemical mechanical polishing (CMP) process β A method for shallow trench isolation on a semiconductor wafer, the semiconductor ^ includes a stone In the evening, a pad oxide layer is provided on the chip: on the surface of the wafer, a silicon nitride (SiHcrl nitride (SiNx) layer is provided above the chemical layer) and at least one shallow trench is provided on the substrate. Semiconductor wafer surface Page 17 434S06. Patent application scope—a predetermined area and penetrate the silicon substrate to a predetermined depth through the nitrogen silicon layer and the pad oxide layer, the method includes the following steps: on the semiconductor wafer A nitrogen-containing silicon dioxide layer is formed on the surface and covers the sidewall and bottom of the shallow trench; at least one dielectric layer is formed on the surface of the nitrogen-containing silicon dioxide layer to fill the shallow trench: a planarization is performed In the manufacturing process, the surface of the dielectric layer in the shallow trench is aligned with the surface of the silicon nitride layer; and the nitrogen silicon layer and the pad oxide layer located outside the shallow trench are removed. 10. The method according to item 9 of the patent application, wherein the method for forming the nitrogen-containing dioxide dioxide layer includes the following steps: A chemical vapor deposition (CVD) process is performed to form a dioxide on the surface of the semiconductor wafer. A silicon layer to cover the sidewalls and bottom of the shallow trench; and perform a rapid heating process and pass in a nitrogen-containing gas to incorporate nitrogen atoms in the nitrogen-containing body into the silicon dioxide layer to form The nitrogen-containing silicon dioxide layer. 11. The method according to item li) of the scope of patent application, wherein the nitrogen-containing gas is nitrous oxide (N 20). 6. Scope of patent application 13. The method according to item 10 of the patent application scope, wherein the nitrogen-containing gas is ammonia (NH3). I 14. The method according to item 9 of the scope of patent application, wherein the method for forming the nitrogen-containing silicon dioxide layer is performed by a thermal oxidation process, and a nitrous oxide (N20) gas is simultaneously passed on the semiconductor wafer. The nitrogen-containing silicon dioxide layer is formed on the surface. | Page 19