CN107195620A - A kind of preparation method and structure of high aspect ratio hole - Google Patents
A kind of preparation method and structure of high aspect ratio hole Download PDFInfo
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- CN107195620A CN107195620A CN201710361221.5A CN201710361221A CN107195620A CN 107195620 A CN107195620 A CN 107195620A CN 201710361221 A CN201710361221 A CN 201710361221A CN 107195620 A CN107195620 A CN 107195620A
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- lamination
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- boron
- glass film
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- 238000002360 preparation method Methods 0.000 title claims abstract description 31
- 238000003475 lamination Methods 0.000 claims abstract description 76
- 239000003990 capacitor Substances 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 230000002093 peripheral effect Effects 0.000 claims abstract description 13
- 239000011521 glass Substances 0.000 claims abstract description 6
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 67
- 229910052796 boron Inorganic materials 0.000 claims description 67
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 48
- 239000005368 silicate glass Substances 0.000 claims description 48
- 239000003989 dielectric material Substances 0.000 claims description 27
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 19
- 229910052698 phosphorus Inorganic materials 0.000 claims description 19
- 239000011574 phosphorus Substances 0.000 claims description 19
- 238000004062 sedimentation Methods 0.000 claims description 13
- 230000008021 deposition Effects 0.000 claims description 6
- 239000002305 electric material Substances 0.000 claims description 2
- 230000002035 prolonged effect Effects 0.000 claims 1
- 230000008859 change Effects 0.000 abstract description 5
- 238000003860 storage Methods 0.000 abstract description 4
- 230000001276 controlling effect Effects 0.000 abstract 1
- 239000011148 porous material Substances 0.000 description 13
- 230000000694 effects Effects 0.000 description 7
- 239000005380 borophosphosilicate glass Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000005234 chemical deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000007772 electrode material Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 230000003631 expected effect Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical compound [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
Abstract
The present invention provides a kind of preparation method and structure of high aspect ratio hole, and methods described includes：Conforma lamination, such as boron-phosphorosilicate glass film lamination are formed on substrate；Etch the conforma lamination formation hole；Wherein, the conforma lamination at least includes two layers of conformal layer with different levels of doping, and the III-V element doping concentration in the conformal layer of bottom is higher than the conformal layer positioned at top layer.The present invention improves the appearance structure of high aspect ratio hole using the doping concentration difference in conforma lamination.For semiconductor storage unit, the present invention has obtained perforate and the Special controlling effect of the ratio range of upper perforate under electric capacity hole in the range of the aspect ratio of specific capacitor hole using thickness range and the concentration range of the conformal layer of the change in concentration of peripheral region, so as to increase electric capacity yield, improve DRAM capacitance structures.
Description
Technical field
The present invention relates to technical field of semiconductors, the more particularly to a kind of preparation method and structure of high aspect ratio hole.
Background technology
In semiconductor device processing technology, high aspect ratio micro-structural (High Aspect Ratio Micro
Structures, HARMS) it is widely used, the process especially made in electric capacity hole.High aspect ratio micro-structural is often referred to hole depth
The ratio of degree and bore dia is more than 2：1, width is less than 100 microns of three-dimensional microstructures.In the application of high aspect ratio micro-structural,
It is generally necessary to prepare hard mask to etch high aspect ratio hole, hard mask can use boron-phosphorosilicate glass (Boro-Phospho-
Silicate-Glass, BPSG) etc. material.
Boron-phosphorosilicate glass is the dielectric material commonly used in IC manufacturing, a Publication No. TW426913B patent
Document discloses a kind of equipment and device of the method and correlation that bpsg film layer is formed by two step deposition processing procedures.One
BPSG conformal layer (conformal layer) is deposited on a base material.One more stable bpsg film layer is higher with one
The fast section of deposition is deposited on the conformal layer.This method is suitable to be at least 5.5 with BPSG to fill depth-width ratio:0.06 micron of 1
Narrow channel.
In advanced footpath than in larger via etch processing procedure, such as when aspect ratio reaches 10 or even 20 to 1, control etching is obtained
Obtaining satisfactory size and pattern becomes to be increasingly difficult to.The through hole of the such high aspect ratio of hard mask etching is used at present, generally
The situation that through hole upper and lower opening aperture is differed occurs, when aspect ratio is bigger, lower oral pore footpath just will more be less than aperture suitable for reading, lower oral pore
The ratio in footpath and aperture suitable for reading is often below 60%, i.e. through-hole side wall and tilted, the overall similar inverted circular cone of through hole.Such depth
Hole pattern is often difficult to reach requirement on devices, and in the processing procedure of follow-up filling pore, filling yield is made a big impact.
Accordingly, it would be desirable to seek a kind of to improve the method for this high aspect ratio hole pattern.
The content of the invention
Prior art in view of the above, it is an object of the invention to provide a kind of preparation method of high aspect ratio hole and
Structure, the problems such as difference of opening diameter up and down for solving high aspect ratio hole in the prior art is big.
In order to achieve the above objects and other related objects, the present invention provides a kind of preparation method of high aspect ratio hole, bag
Include following steps：
Conforma lamination is formed on substrate；
Etch the conforma lamination formation hole；
Wherein, the conforma lamination at least includes two layers of conformal layer with different levels of doping, positioned at the conformal of bottom
The III-V element doping concentration of layer is higher than the conformal layer positioned at top layer.
Alternatively, the conforma lamination includes two layers or more than two layers boron phosphorous silicate glass film；From top layer to bottom boron phosphorus silicon
The boron of glass-film and/or the doping concentration of phosphorus increase successively.
Alternatively, the III-V element doping concentration increasing degree of adjacent two conformal layer is 20-100%.
Alternatively, the conforma lamination is formed using the method successive sedimentation of chemical deposition；Successive sedimentation forms the guarantor
During shape lamination, the successive sedimentation in same reaction cavity.
Alternatively, the conforma lamination includes bottom boron phosphorous silicate glass film and on the bottom boron phosphorous silicate glass film
Top layer boron phosphorous silicate glass film；Wherein, the thickness of the bottom boron phosphorous silicate glass film is 300-600nm, and the doping concentration of boron is
2-4wt%, the doping concentration of phosphorus is 2-5wt%；The thickness of the top layer boron phosphorous silicate glass film is 400-800nm, the doping of boron
Concentration is 1-3wt%, and the doping concentration of phosphorus is 2-4wt%.
Alternatively, the conforma lamination includes bottom boron phosphorous silicate glass film, on the bottom boron phosphorous silicate glass film
Middle level boron phosphorous silicate glass film, and the top layer boron phosphorous silicate glass film on the middle level boron phosphorous silicate glass film；Wherein, institute
The thickness for stating bottom boron phosphorous silicate glass film is 200-400nm, and the doping concentration of boron is 2.5-3.5wt%, and the doping concentration of phosphorus is
2.5-5.5wt%；The thickness of the middle level boron phosphorous silicate glass film is 200-400nm, and the doping concentration of boron is 2-3wt%, phosphorus
Doping concentration is 2.5-5wt%；The thickness of the top layer boron phosphorous silicate glass film is 300-600nm, and the doping concentration of boron is 1-
3wt%, the doping concentration of phosphorus is 2-4wt%.
Alternatively, the aspect ratio of described hole is more than or equal to 10, and the bottom of described hole and the bore dia ratio at top are
60%-100%.
In order to achieve the above objects and other related objects, the present invention also provides a kind of preparation side of array of capacitors structure
Method, comprises the following steps：
Multiple described holes of array arrangement are formed in conforma lamination using the preparation method of above-mentioned high aspect ratio hole；
The bottom electrode of capacitor, the side wall of the bottom electrode covering described hole and bottom are formed in described hole；
Remove the conforma lamination around the bottom electrode, and the filled dielectric material around the bottom electrode；And
The Top electrode of capacitor is formed on the dielectric material, so that array of capacitors structure is made.
In order to achieve the above objects and other related objects, the present invention also provides a kind of semiconductor memory device junction structure, including：
Substrate, including array region and the outer peripheral areas for surrounding the array region；
Array of capacitors structure, is arranged on the array region of the substrate, and the array of capacitors structure includes
The capacitor of multiple array arrangements, each capacitor includes bottom electrode, the dielectric material of the parcel bottom electrode and positioned at institute
Give an account of the Top electrode on electric material, the bottom electrode is cup-like structure, including electrode base and from the electrode base to
The electrode sidewall of upper extension, the draw ratio of the bottom electrode is more than or equal to 10；And
Conforma lamination, in the outer peripheral areas of the substrate；
Wherein, the conforma lamination at least includes two layers of conformal layer with different levels of doping, positioned at the conformal of bottom
The III-V element doping concentration of layer is higher than the conformal layer positioned at top layer, and the difference of the doping concentration controls the bottom electrode
The ratio of base diameter and open top external diameter be 60%-100%.
Alternatively, the thickness range of the conforma lamination is 700-1400nm, the length to define the capacitor.
Alternatively, the upper surface of the array of capacitors structure and the upper surface of the conforma lamination are a continuous surface.
Alternatively, section lead after the semiconductor memory device junction structure also includes one, is formed at the array of capacitors knot
The upper surface of structure and the upper surface for extending to the conforma lamination.
Alternatively, the III-V element doping concentration of the connecting part of adjacent two conformal layer is graded.
As described above, the preparation method and structure of the high aspect ratio hole of the present invention, have the advantages that：
Improve the method that high aspect ratio etches hole the invention provides a kind of concentration difference of utilization multilayer conformal layer, with
Multilayer conformal layer improves the pattern knot of high aspect ratio hole as hard mask by adjusting the doping concentration of multilayer conformal layer
Structure, is conducive to making the pores array with more vertical holes, can improve the effect of successive process intermediate gap filling.Hole top
The diameter ratio of portion and bottom is closer to 1, i.e. hole closer to column, and with more preferable vertical profile, aspect ratio is more than or equal to 10.
For semiconductor storage unit, the present invention utilizes the thickness range and concentration of the conformal layer of the change in concentration of peripheral region
Scope has obtained perforate and the Special controlling of the ratio range of upper perforate under electric capacity hole in the range of the aspect ratio of specific capacitor hole
Effect, the ratio of perforate and upper perforate under the electric capacity hole of electric capacity above ARRAY (array) area is have impact on the conformal layer of peripheral region
Value, this has not expected effect.It makes under conditions of hole aspect ratio scope of the electric capacity to form bottom electrode in ARRAY areas
The ratio in lower oral pore footpath and aperture suitable for reading is worth to control in a certain scope Inner, so as to increase electric capacity yield, improves capacitance structure.
Brief description of the drawings
Fig. 1 is shown as the flow chart of the preparation method for the high aspect ratio hole that the present invention is provided.
Fig. 2 is shown as the schematic diagram for the high aspect ratio pore space structure that the present invention is provided.
Fig. 3 is shown as the preparation process schematic diagram of the high aspect ratio hole of the offer of the embodiment of the present invention one.
Fig. 4 is shown as the preparation process schematic diagram of the high aspect ratio hole of the offer of the embodiment of the present invention two.
Fig. 5 is shown as the semiconductor memory device junction structure schematic diagram of the offer of the embodiment of the present invention three.
Component label instructions
100,301,401,501 substrates
200,502 conforma laminations
302,402 bottom boron phosphorous silicate glass films
303,404 top layer boron phosphorous silicate glass films
403 middle level boron phosphorous silicate glass films
300,304,405 holes
503 array of capacitors structures
5031 bottom electrodes
5032 dielectric materials
5033 Top electrodes
5034 polysilicons
Section lead after 504
S1~S2 steps
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.It should be noted that, in the case where not conflicting, following examples and implementation
Feature in example can be mutually combined.
It should be noted that the diagram provided in following examples only illustrates the basic structure of the present invention in a schematic way
Think, then in schema only display with relevant component in the present invention rather than according to component count, shape and the size during actual implement
Draw, it is actual when implementing, and kenel, quantity and the ratio of each component can be a kind of random change, and its assembly layout kenel
It is likely more complexity.
In order to solve to etch in the prior art to be formed high aspect ratio hole the difference of opening diameter up and down it is big the problems such as, this hair
A kind of bright concentration difference there is provided utilization multilayer conformal layer improves the method that high aspect ratio etches hole.
Referring to Fig. 1, a kind of preparation method of high aspect ratio hole, comprises the following steps：
S1 forms conforma lamination on substrate, and the conforma lamination at least includes having the conformal of different levels of doping two layers
Layer, the conformal layer positioned at top layer is higher than positioned at the III-V element doping concentration of the conformal layer of bottom；
S2 etches the conforma lamination formation hole.
This method adjusts etch topography, so as to improve by etching conforma lamination using the different levels of doping of each layer
The overall structure of the hole of etching wherein.In order to obtain side wall more vertical high aspect ratio hole, the conforma lamination can
Prolong etching direction and be stepped up doping concentration, so that the aperture of hole upper and lower opening is reached unanimity.Specifically, when described conformal folded
When layer includes two layers or more than two layers boron phosphorous silicate glass film；From top layer to the doping of the boron of bottom boron phosphorous silicate glass film and/or phosphorus
Concentration increases successively.The III-V element doping concentration increasing degree of adjacent two conformal layer can be 20-100%.
In addition, the conforma lamination can be formed using the method successive sedimentation of chemical deposition.Specifically, successive sedimentation is formed
During the conforma lamination, the successive sedimentation in same reaction cavity, to ensure closely to connect between multilayer conformal layer.
The need for according to specific perforate, the gross thickness of the conforma lamination can be 700-1400nm., can using this method
To etch the conforma lamination while forming multiple holes, for example, the high aspect ratio pores array in memory construction can be made.
Specifically, the aspect ratio of etching hole is more than or equal to 10.The diameter ratio of the bottom and top that etch hole can reach 60%-
100%.
Referring to Fig. 2, the high aspect ratio pore space structure that a kind of use above method is obtained, including：
Conforma lamination 200；
And it is inserted perpendicularly into the hole 300 in the conforma lamination 200；
Wherein, the conforma lamination 200 at least includes two layers of conformal layer with different levels of doping, positioned at the guarantor of bottom
The III-V element doping concentration of shape layer is higher than the conformal layer positioned at top layer.
The conforma lamination 200 is generally prepared on the substrate 100 of concrete application, and the substrate 100 can be semiconductor
Substrate or other suitable materials.
Specifically, when the conforma lamination includes two layers or more than two layers boron phosphorous silicate glass film；From top layer to bottom boron
The boron of phosphorous silicate glass film and/or the doping concentration of phosphorus increase successively.The III-V element doping of adjacent two layers boron phosphorous silicate glass film
Concentration increasing degree is 20-100%.The conforma lamination 200 can be formed using the method successive sedimentation of chemical deposition.It is described to protect
The gross thickness of shape lamination 200 can be 700-1400nm.Described hole structure can include it is multiple be inserted perpendicularly into it is described conformal folded
Hole 300 in layer 200.For example, multiple pores arrays being inserted perpendicularly into the conforma lamination are arranged for memory device junction
Among structure.Specifically, the aspect ratio of described hole 300 is more than or equal to 10.The bottom of described hole 300 and the diameter ratio at top
For 60%-100%.
In addition, the present invention also provides a kind of preparation method of array of capacitors structure and including the array of capacitors structure
Semiconductor memory device junction structure, the described method comprises the following steps：
Multiple described holes of array arrangement are formed in conforma lamination using the preparation method of above-mentioned high aspect ratio hole；
The bottom electrode of capacitor is formed in described hole, wherein side wall and the bottom of bottom electrode covering described hole；Remove institute
State the conforma lamination around bottom electrode, and the filled dielectric material around the bottom electrode；And on the dielectric material
The Top electrode of capacitor is formed, so that array of capacitors structure is made.
The semiconductor memory device junction structure, including：
Substrate, including array region and the outer peripheral areas for surrounding the array region；Array of capacitors structure, is arranged at institute
State on the array region of substrate, the array of capacitors structure includes the capacitor of multiple array arrangements, each capacitor
Including bottom electrode, the dielectric material of the parcel bottom electrode and the Top electrode on the dielectric material, the lower electricity
Extremely cup-like structure, including electrode base and the electrode sidewall that is upwardly extended by the electrode base, the length of the bottom electrode
Footpath ratio is more than or equal to 10；And conforma lamination, in the outer peripheral areas of the substrate.
Wherein, the conforma lamination at least includes two layers of conformal layer with different levels of doping, positioned at the conformal of bottom
The III-V element doping concentration of layer is higher than the conformal layer positioned at top layer, and the difference of the doping concentration controls the bottom electrode
The ratio of base diameter and open top external diameter be 60%-100%.
For semiconductor storage unit, such as DRAM device, the present invention makes hole aspect ratio model of the electric capacity to form bottom electrode
The ratio in lower oral pore footpath and aperture suitable for reading is worth to control in a certain scope Inner in ARRAY areas under conditions of enclosing, and improves electric capacity hole
Appearance structure, the effect of successive process intermediate gap filling can be improved, so as to increase electric capacity yield, improve DRAM capacitive junctions
Structure.
Technical scheme is described in detail below by specific example.
Embodiment one
As shown in figure 3, the present embodiment provides a kind of boron-phosphorosilicate glass film preparation height using two layers of various concentrations and thickness
The method and resulting structures of aspect ratio hole.
There is provided a substrate 301 first.
Then, conforma lamination is formed using the method successive sedimentation of chemical deposition on the substrate 301.Specifically, even
When continuous deposition forms the conforma lamination, the successive sedimentation in same reaction cavity, reacting gas is uninterruptedly provided.Wherein,
The conforma lamination includes bottom boron phosphorous silicate glass film 302 and the top layer boron on the bottom boron phosphorous silicate glass film 302
Phosphorous silicate glass film 303.
Preferably, the thickness of the bottom boron phosphorous silicate glass film 302 is 300-600nm, the doping concentration of boron to the present embodiment
For 2-4wt%, the doping concentration of phosphorus is 2-5wt%；The thickness of the top layer boron phosphorous silicate glass film 303 is 400-800nm, boron
Doping concentration is 1-3wt%, and the doping concentration of phosphorus is 2-4wt%.
Then, etch the conforma lamination and form multiple holes 304, to form the pores array of high aspect ratio.
The aspect ratio of hole 304 is more than or equal to 10 obtained by the present embodiment.The bottom of gained hole 304 and the diameter at top
Than for 60%-100%.
Embodiment two
As shown in figure 4, the present embodiment provides a kind of boron-phosphorosilicate glass film preparation profundity using three layers of various concentrations, thickness
Method and resulting structures of the footpath than hole.
There is provided a substrate 401 first.
Then, conforma lamination is formed using the method successive sedimentation of chemical deposition on the substrate 401.Specifically, even
When continuous deposition forms the conforma lamination, the successive sedimentation in same reaction cavity, reacting gas is uninterruptedly provided.Wherein,
The conforma lamination includes bottom boron phosphorous silicate glass film 402, the middle level boron phosphorus on the bottom boron phosphorous silicate glass film 402
Silica glass film 403, and the top layer boron phosphorous silicate glass film 404 on the middle level boron phosphorous silicate glass film 403.
Preferably, the thickness of the bottom boron phosphorous silicate glass film 402 is 200-400nm, the doping concentration of boron to the present embodiment
For 2.5-3.5wt%, the doping concentration of phosphorus is 2.5-5.5wt%；The thickness of the middle level boron phosphorous silicate glass film 403 is 200-
400nm, the doping concentration of boron is 2-3wt%, and the doping concentration of phosphorus is 2.5-5wt%；The top layer boron phosphorous silicate glass film 404
Thickness is 300-600nm, and the doping concentration of boron is 1-3wt%, and the doping concentration of phosphorus is 2-4wt%.
Then, etch the conforma lamination and form multiple holes 405, to form the pores array of high aspect ratio.
The aspect ratio of hole 405 is more than 10-20 obtained by the present embodiment.The bottom of gained hole 405 and the diameter ratio at top
Up to 80%-100%.
It should be noted that embodiment one and two examples that embodiment two is only the present invention, in other realities of the present invention
Apply in example, the conforma lamination can include two layers, three layers or more layer conformal layer (being specially bpsg film), from top layer to bottom
The III-V element doping concentration of conformal layer increases successively, specific doping concentration, the thickness of every layer of conformal layer (being specially bpsg film)
Degree can be adjusted according to the need for actual conditions.
Embodiment three
The semiconductor memory device junction that the present embodiment provides a kind of preparation method of array of capacitors structure and obtained
Structure.It the described method comprises the following steps：
The preparation method of the high aspect ratio hole provided using the present invention, the method as described in embodiment one, embodiment two,
Multiple holes of array arrangement are formed in conforma lamination.
Then, the bottom electrode of capacitor, the side wall of the bottom electrode covering described hole and bottom are formed in described hole
Portion.For example, bottom electrode, the electrode material of use can be formed by electrode materials such as deposited metal, polysilicons in described hole
Can be one or more.The bottom electrode of gained is cup-like structure, including bottom and the side wall that is extended by the bottom up.
Next, removing the conforma lamination around the bottom electrode, and dielectric material is formed around the bottom electrode.Tool
Body, the redundant electrodes material being covered in when depositing the bottom electrode outside hole can be first removed, then again will be conformal folded under it
Layer is removed, and the conforma lamination outside array region can be removed or retained according to actual needs.Remove and be not required to around bottom electrode
After the BPSG laminations wanted, dielectric materials layer can be formed around the bottom electrode of cup-shaped using deposition or other suitable methods,
And between multiple bottom electrodes filled dielectric material, lower electrode surface need to be completely covered dielectric material.
Finally, the Top electrode of capacitor is formed on the dielectric material, so as to complete the making of array of capacitors structure.
Specifically, one layer of electrode material can be deposited on the dielectric materials layer of covering bottom electrode as the Top electrode of capacitor, and is ensured
The Top electrode of capacitor is placed separated by dielectric material with bottom electrode.In the inside of cup-shaped bottom electrode, dielectric materials layer covering cup bottom
Portion and side wall, Top electrode formation cover the cup like bottom formed by dielectric materials layer and side wall, not on dielectric materials layer
Cup-like interior space is filled up, finally polysilicon (poly) is filled up in the concave interior of cup-shaped.Wherein, capacitor lower electrode, on
The forming method and selection of electrode and dielectric material can determine that this is the known technology in this area according to actual needs,
This is not repeated.
The present embodiment method obtain semiconductor memory device junction structure as shown in figure 5, including：
Substrate 501, array of capacitors structure 503 and the conforma lamination 502 being retained in outside array region.
Wherein, substrate 501 includes array region and surrounds the outer peripheral areas of the array region, can be Semiconductor substrate
Or other suitable materials and structure.
Array of capacitors structure 503 is arranged on the array region of substrate 501, including under the capacitor of multiple array arrangements
Electrode 5031, the dielectric material 5032 of the parcel bottom electrode 5031 and the electric capacity on the dielectric material 5032
Device Top electrode 5033.Bottom electrode 5031 is cup-like structure, including bottom and the side wall that is extended by the bottom up, bottom electrode
5031 draw ratio is more than or equal to 10.The inside housed in cup-shaped bottom electrode 5031, the covering cup like bottom of dielectric material 5032
With side wall, Top electrode 5033 covers the cup like bottom formed by dielectric material 5032 and side wall, and polysilicon 5034 is by cup-like interior
Space is filled up.
Conforma lamination 502 is located in the outer peripheral areas of substrate 501；According to the preparation method of foregoing hole, conforma lamination
502 at least include two layers of conformal layer with different levels of doping, positioned at the III-V element doping concentration of the conformal layer of bottom
It is higher than outside the conformal layer positioned at top layer, the base diameter of the difference control bottom electrode 5031 of the doping concentration and open top
The ratio in footpath is 60%-100%.Specifically, the thickness range of the conforma lamination 502 can be 700-1400nm, to fixed
The length of the justice capacitor.The III-V element doping concentration of the connecting part of adjacent two conformal layer is graded.
In the present embodiment, the upper surface of the upper surface of array of capacitors structure 503 and the conforma lamination 502 is continuous for one
Surface.Section lead (BEOL metal line) 504, is formed at upper surface and the extension of the array of capacitors structure 503 after one
To the upper surface of the conforma lamination 502.
Electricity under the preparation method of the high aspect ratio hole provided as a result of the present invention, the capacitor made using hole
The base diameter of pole 5031 is with the ratio of open top external diameter up to 60-100%.This is conducive to making highdensity capacitor battle array
Row, it is to avoid being adhered between multiple capacitor lower electrodes, improve the effect of follow-up gap filling, are conducive to carrying for electric capacity yield
It is high.
In summary, the preparation method of high aspect ratio hole of the invention, using multilayer conformal layer (be specially BPSG) as
Hard mask, the appearance structure of high aspect ratio hole is improved by adjusting the doping concentration of multilayer conformal layer, is conducive to making tool
There is the pores array of more vertical holes.The diameter ratio of hole top and bottom has closer to 1, i.e. hole closer to column
More preferable vertical profile, aspect ratio is more than or equal to 10.
For semiconductor storage unit, the present invention utilizes the thickness range and concentration of the conformal layer of the change in concentration of peripheral region
Scope has obtained perforate and the Special controlling of the ratio range of upper perforate under electric capacity hole in the range of the aspect ratio of specific capacitor hole
Effect, the ratio of perforate and upper perforate under the electric capacity hole of the electric capacity above ARRAY areas is have impact on the bpsg film floor of peripheral region, this
With not expected effect.
So, the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (13)
1. a kind of preparation method of high aspect ratio hole, it is characterised in that comprise the following steps：
Conforma lamination is formed on substrate；And
Etch the conforma lamination formation hole；
Wherein, the conforma lamination at least includes the conformal layer two layers with different levels of doping, positioned at the conformal layer of bottom
III-V element doping concentration is higher than the conformal layer positioned at top layer.
2. the preparation method of high aspect ratio hole according to claim 1, it is characterised in that：The conforma lamination includes two
Layer or more than two layers boron phosphorous silicate glass film；Doping concentration from top layer to the boron of bottom boron phosphorous silicate glass film and/or phosphorus increases successively
Plus.
3. the preparation method of high aspect ratio hole according to claim 1, it is characterised in that：The three or five of adjacent two conformal layer
Race's element doping concentration increasing degree is 20-100%.
4. the preparation method of high aspect ratio hole according to claim 1, it is characterised in that：The conforma lamination useization
The method successive sedimentation for learning deposition is formed；When successive sedimentation forms the conforma lamination, continuously sunk in same reaction cavity
Product.
5. the preparation method of high aspect ratio hole according to claim 1, it is characterised in that：The conforma lamination includes bottom
Layer boron phosphorous silicate glass film and the top layer boron phosphorous silicate glass film on the bottom boron phosphorous silicate glass film；Wherein, the bottom
The thickness of boron phosphorous silicate glass film is 300-600nm, and the doping concentration of boron is 2-4wt%, and the doping concentration of phosphorus is 2-5wt%；Institute
The thickness for stating top layer boron phosphorous silicate glass film is 400-800nm, and the doping concentration of boron is 1-3wt%, and the doping concentration of phosphorus is 2-
4wt%.
6. the preparation method of high aspect ratio hole according to claim 1, it is characterised in that：The conforma lamination includes bottom
Layer boron phosphorous silicate glass film, the middle level boron phosphorous silicate glass film on the bottom boron phosphorous silicate glass film, and in described
Top layer boron phosphorous silicate glass film on layer boron phosphorous silicate glass film；Wherein, the thickness of the bottom boron phosphorous silicate glass film is 200-
400nm, the doping concentration of boron is 2.5-3.5wt%, and the doping concentration of phosphorus is 2.5-5.5wt%；The middle level boron-phosphorosilicate glass
The thickness of film is 200-400nm, and the doping concentration of boron is 2-3wt%, and the doping concentration of phosphorus is 2.5-5wt%；The top layer boron
The thickness of phosphorous silicate glass film is 300-600nm, and the doping concentration of boron is 1-3wt%, and the doping concentration of phosphorus is 2-4wt%.
7. the preparation method of the high aspect ratio hole according to any one of claim 1-6, it is characterised in that：Described hole
Aspect ratio be more than or equal to 10, the bottom of described hole and the bore dia ratio at top are 60%-100%.
8. a kind of preparation method of array of capacitors structure, it is characterised in that comprise the following steps：
Multiple described holes of array arrangement are formed in conforma lamination using the preparation method described in claim 1；
The bottom electrode of capacitor, the side wall of the bottom electrode covering described hole and bottom are formed in described hole；
Remove the conforma lamination around the bottom electrode, and the filled dielectric material around the bottom electrode；And
The Top electrode of capacitor is formed on the dielectric material, so that array of capacitors structure is made.
9. a kind of semiconductor memory device junction structure, it is characterised in that including：
Substrate, including array region and the outer peripheral areas for surrounding the array region；
Array of capacitors structure, is arranged on the array region of the substrate, and the array of capacitors structure includes multiple
The capacitor of array arrangement, each capacitor includes bottom electrode, the dielectric material of the parcel bottom electrode and positioned at being given an account of
Top electrode on electric material, the bottom electrode is cup-like structure, including electrode base and is prolonged upwards by the electrode base
The electrode sidewall stretched, the draw ratio of the bottom electrode is more than or equal to 10；And
Conforma lamination, in the outer peripheral areas of the substrate；
Wherein, the conforma lamination at least includes the conformal layer two layers with different levels of doping, positioned at the conformal layer of bottom
III-V element doping concentration is higher than the conformal layer positioned at top layer, and the difference of the doping concentration controls the bottom of the bottom electrode
The ratio of portion's diameter and open top external diameter is 60%-100%.
10. semiconductor memory device junction structure according to claim 9, it is characterised in that：The thickness model of the conforma lamination
Enclose for 700-1400nm, the length to define the capacitor.
11. semiconductor memory device junction structure according to claim 9, it is characterised in that：The array of capacitors structure
Upper surface and the upper surface of the conforma lamination are a continuous surface.
12. semiconductor memory device junction structure according to claim 11, it is characterised in that：The semiconductor memory device junction
Section lead after structure also includes one, is formed at the upper surface of the array of capacitors structure and extends to the upper table of the conforma lamination
Face.
13. the semiconductor memory device junction structure according to claim any one of 9-12, it is characterised in that：Adjacent two conformal layer
Connecting part III-V element doping concentration be graded.
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| CN201810198475.4A CN108538818A (en) | 2017-05-19 | 2017-05-19 | A kind of preparation method and structure of high aspect ratio hole |
| CN201710361221.5A CN107195620B (en) | 2017-05-19 | 2017-05-19 | A kind of preparation method and structure of high aspect ratio hole |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111490015A (en) * | 2019-01-28 | 2020-08-04 | 美光科技公司 | Method for forming semiconductor structure |
| WO2022166093A1 (en) * | 2021-02-05 | 2022-08-11 | 长鑫存储技术有限公司 | Manufacturing method for semiconductor structure, and semiconductor structure |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110943163B (en) * | 2018-09-21 | 2022-07-05 | 长鑫存储技术有限公司 | Method for improving appearance of capacitor hole |
| CN113517287B (en) * | 2020-04-09 | 2023-12-05 | 中国科学院微电子研究所 | Semiconductor structure and preparation method thereof |
| CN118099141A (en) * | 2022-11-17 | 2024-05-28 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
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| Publication number | Publication date |
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| CN107195620B (en) | 2018-07-06 |
| CN108538818A (en) | 2018-09-14 |
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