US20110142074A1 - Serial communication module with multiple receiver/transmitters - Google Patents

Serial communication module with multiple receiver/transmitters Download PDF

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Publication number
US20110142074A1
US20110142074A1 US12/639,614 US63961409A US2011142074A1 US 20110142074 A1 US20110142074 A1 US 20110142074A1 US 63961409 A US63961409 A US 63961409A US 2011142074 A1 US2011142074 A1 US 2011142074A1
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United States
Prior art keywords
byte
module
slave
accordance
uart
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Abandoned
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US12/639,614
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English (en)
Inventor
William Henry Lueckenbach
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Intelligent Platforms LLC
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GE Fanuc Intelligent Platforms Inc
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Filing date
Publication date
Application filed by GE Fanuc Intelligent Platforms Inc filed Critical GE Fanuc Intelligent Platforms Inc
Priority to US12/639,614 priority Critical patent/US20110142074A1/en
Assigned to GE FANUC INTELLIGENT PLATFORMS, INC. reassignment GE FANUC INTELLIGENT PLATFORMS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LUECKENBACH, WILLIAM HENRY
Priority to EP10194273A priority patent/EP2336896B1/en
Priority to DK10194273.8T priority patent/DK2336896T3/da
Priority to CN2010106160580A priority patent/CN102118223A/zh
Publication of US20110142074A1 publication Critical patent/US20110142074A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40019—Details regarding a bus master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/403—Bus networks with centralised control, e.g. polling

Definitions

  • the embodiments described herein relate generally to serial communications and, more particularly, to serial communications transmitted via a multiport communication module.
  • At least some known communication networks use a 9-bit serial communication protocol to facilitate minimizing load on slave modules by using a ninth bit of each byte as an indicator bit.
  • the ninth bit is set to one for command bytes, and is set to zero for data bytes.
  • some master modules include receiver/transmitters that do not support a 9-bit communication protocol, but rather require use of an 8-bit communication protocol.
  • At least some known communication networks use an 8-bit serial communication protocol, wherein a master module uses a single receiver/transmitter to communicate with the slave modules. For each byte to be transmitted to the slave modules, at least some known master modules set a parity bit to indicate whether the byte is a data byte or a command byte. In at least some known master modules, such a configuration requires multiple commands to configure and/or reconfigure the single receiver/transmitter.
  • a method for implementing serial communications between a master module and at least one slave module in a communications network.
  • the method includes initializing a first receiver/transmitter of the master module to space parity, initializing a second receiver/transmitter of the master module to mark parity, and determining whether a first byte of a message is a command byte or a data byte. If the first byte is a data byte, the first byte is transmitted to the at least one slave module using the first receiver/transmitter. If the first byte is a command byte, the first byte is transmitted to the at least one slave module using the second receiver/transmitter.
  • a serial communication system in another aspect, includes a plurality of slave modules and a master module.
  • the master module includes a first port and a second port, wherein each of the first and second ports are coupled to each of the slave modules.
  • the master module is configured to initialize the first port to space parity, initialize the second port to mark parity, transmit at least one data byte to at least one of the slave modules via the first port, and transmit at least one command byte to at least one of the slave modules via the second port.
  • a master device for use with a serial communication system.
  • the master device includes a multiport communication module and a microprocessor.
  • the multiport communication module includes a first universal asynchronous receiver/transmitter (UART) coupled to a plurality of slave modules via a network, a second UART coupled to the slave modules via the network.
  • the microprocessor is coupled to the first and second UARTs via a bus, and is configured to initialize the first UART to space parity, initialize the second UART to mark parity, transmit at least one data byte within a message to at least one of the slave modules via the first UART, and transmit at least one command byte within the message to at least one of the slave modules via the second UART.
  • FIG. 1 is a schematic block diagram of a serial communication system.
  • FIG. 2 is a flowchart illustrating an exemplary method of implementing serial communications within the serial communication system shown in FIG. 1 .
  • microprocessor refers generally to any programmable system including systems and microcontrollers, reduced instruction set circuits (RISC), application specific integrated circuits (ASIC), programmable logic circuits (PLC), and any other circuit or processor capable of executing the functions described herein.
  • RISC reduced instruction set circuits
  • ASIC application specific integrated circuits
  • PLC programmable logic circuits
  • module refers generally to any device that enables a serial communication via a network.
  • Exemplary devices include computers, microcontrollers, sensors, and the like. The above examples are exemplary only, and thus are not intended to limit in any way the definition and/or meaning of the term module.
  • module may be used interchangeably with the term “node.”
  • the term “network” refers generally to any multidrop network that includes at least one master and one or more slaves.
  • Exemplary multidrop networks include, but are not limited to only including, RS-485 networks and RS-232 networks. However, any suitable network may be used in the embodiments described herein.
  • the term “port” refers generally to a communication port, such as a serial port, that transmits and/or receives data.
  • exemplary communication ports include, but are not limited to only including, universal asynchronous receiver/transmitters (UARTs) and universal synchronous receiver/transmitters (USARTs). However, any suitable communication port may be used in the embodiments described herein.
  • Described in detail herein are exemplary embodiments of methods, systems, and apparatus that facilitate using two ports of a multiport communication module to transmit data over a 9-bit network using 8-bit UARTs.
  • Using two ports facilitates decreasing a delay between transmissions of each byte from a master to a slave. Decreasing such a delay facilitates decreasing overall transmission times of messages within a multidrop network using multiport communication modules.
  • Exemplary technical effects of the embodiments described herein include at least one of: (a) determining a network address of a desired slave module; (b) transmitting the network address to a plurality of slave modules coupled to a master module via a network; (c) initializing a first master module UART to space parity; (d) initializing a second master module UART to mark parity; (e) determining whether a message has been stored for transmission to the desired slave module; (f) if a message is not stored, periodically re-determining whether a message has been stored for transmission or, if a message is stored, determining whether a first byte in the message is a data byte or a command byte; (g) if the first byte is a data byte, transmitting the first byte to the slave module via the first UART or, if the first byte is a command byte, transmitting the first byte to the slave module via the second UART; (h) determining whether the message includes additional bytes; and (i)
  • FIG. 1 is a schematic block diagram of a serial communication system 100 that may be used in, for example, a high-speed communication network to facilitate reducing communication time and minimizing a probability of a message time out error.
  • system 100 includes a plurality of slave modules 102 that each includes a communication port 104 .
  • Exemplary slave modules 102 include sensors, such as temperature and/or pressure sensors, although any suitable device may be used as slave module 102 that includes communication port 104 .
  • port 104 is a universal asynchronous receiver/transmitter (UART), such as an 8-bit UART.
  • System 100 also includes a master module 106 .
  • Exemplary master modules 106 include computers and automation controllers. However, any suitable device may be used as master module 106 .
  • master module 106 includes a microprocessor 108 and a memory 110 coupled to microprocessor 108 via a bus 112 .
  • master module 106 may include more than one microprocessor 108 and/or more than one memory 110 .
  • master module 106 also includes a multiport communication module 114 that includes at least a first communication port 116 and a second communication port 118 .
  • first communication port 116 and second communication port 118 is a UART, such as an 8-bit UART.
  • system 100 includes a network 120 that couples, such as communicatively or operatively couples, master module 106 and each slave module 102 . More specifically, network 120 couples first communication port 116 and second communication port 118 of master module 106 to port 104 of each slave module 102 .
  • Exemplary networks 120 include RS-485 networks. However, any suitable multidrop network may be used as network 120 .
  • FIG. 2 is a flowchart 200 illustrating an exemplary method of implementing serial communications within a system, such as serial communication system 100 (shown in FIG. 1 ).
  • master module 106 determines 202 a network address of a desired slave module 102 .
  • microprocessor 108 determines the network address of the desired slave module 102 in memory 110 .
  • memory 110 may include a lookup table that lists an identifier and a network address for each slave module 102 .
  • master module 106 transmits 204 an address byte to each slave module 102 via network 120 , wherein the address byte includes the network address byte associated with the desired slave module 102 .
  • Master module 106 may transmit the address byte using either first communication port 116 or second communication port 118 .
  • Each slave module 102 receives the address byte and determines whether the network address included within the address byte matches its own network address. Slave modules 102 with non-matching network addresses ignore any future messages or bytes until another address byte is transmitted by master module 106 via network 120 .
  • the desired slave module 102 waits for additional bytes including commands or data.
  • master module 106 initializes 206 first communication port 116 to space parity, and initializes 208 second communication port 118 to mark parity. Specifically, microprocessor 108 initializes first communication port 116 such that a parity bit is set to zero, and initializes second communication port 118 such that a parity bit is set to one. Once first communication port 116 and second communication port 118 are each initialized to its respective parity, master module 106 determines 210 whether there exists a message to be transmitted to the desired slave device 102 . In some embodiments, messages are queued in memory 110 based on, for example, a priority assigned to each message and/or a type of message.
  • microprocessor 108 determines whether memory 110 currently stores a message that is to be transmitted to the desired slave module 102 via network 120 . If no message is stored for transmission to the desired slave module 102 , microprocessor 108 periodically re-determines whether a message has been stored.
  • master module 106 determines 212 whether a first byte of the message is a command byte or a data byte. Specifically, microprocessor 108 detects whether a final bit of the first byte is a zero or a one. If the final bit is a zero, microprocessor 108 detects that the first byte is a data byte. If the final bit is a one, microprocessor 108 detects that the first byte is a command byte.
  • each data byte has a final bit with a value of one
  • each command byte has a final bit with a value of zero.
  • master module 106 is configured to transmit any suitable 8-bit message via first communication port 116 or second communication port 118 using any suitable 9-bit protocol.
  • first communication port 116 may transmit any suitable 8-bit message by adding a ninth bit to the message according to the parity assigned to first communication port 116 , such as space parity.
  • second communication port 118 may transmit any suitable 8-bit message by adding a ninth bit to the message according to the parity assigned to second communication port j 118 , such as mark parity.
  • master module 106 transmits 214 the first byte to the desired slave module 102 via first communication port 116 and network 120 .
  • microprocessor 108 retrieves the first byte from memory 110 and transmits the first byte to slave module port 104 via first communication port 116 and network 120 .
  • master module 106 transmits 216 the first byte to the desired slave module 102 via second communication port 118 and network 120 .
  • microprocessor 108 retrieves the first byte from memory 110 and transmits the first byte to slave module port 104 via second communication port 118 and network 120 .
  • the remaining slave modules 102 in system 100 ignore the first byte.
  • master module 106 determines 218 whether the message is complete. Specifically, microprocessor 108 determines whether memory 110 currently stores additional bytes associated with the message that is to be transmitted to the desired slave module 102 . If no additional bytes are stored for transmission to the desired slave module 102 , microprocessor 108 re-determines 210 whether a message has been stored in memory 110 . In an alternative embodiment, microprocessor 108 re-determines 202 a network address of a different desired slave module 102 . If memory 110 does have additional bytes stored for transmission to the desired slave module 102 , microprocessor 108 re-determines 212 whether the next byte is a data byte or a command byte.
  • serial communication environment is not intended to suggest any limitation as to the scope of use or functionality of any aspect of the embodiments described herein. Moreover, the serial communication environment should not be interpreted as having any dependency or requirement relating to any one or combination of components illustrated in the exemplary operating environment.
  • serial communication systems, environments, and/or configurations examples include, but are not limited to, personal computers, server computers, hand-held or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, mobile telephones, network PCs, minicomputers, mainframe computers, distributed computing environments that include any of the above systems or devices, and the like.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Information Transfer Systems (AREA)
US12/639,614 2009-12-16 2009-12-16 Serial communication module with multiple receiver/transmitters Abandoned US20110142074A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US12/639,614 US20110142074A1 (en) 2009-12-16 2009-12-16 Serial communication module with multiple receiver/transmitters
EP10194273A EP2336896B1 (en) 2009-12-16 2010-12-09 Serial communication module with multiple receiver/transmitters
DK10194273.8T DK2336896T3 (da) 2009-12-16 2010-12-09 Seriekommunikationsmodul med flere modtagere/transmittere
CN2010106160580A CN102118223A (zh) 2009-12-16 2010-12-16 具有多个接收器/发送器的串行通信模块

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US12/639,614 US20110142074A1 (en) 2009-12-16 2009-12-16 Serial communication module with multiple receiver/transmitters

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US20110142074A1 true US20110142074A1 (en) 2011-06-16

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EP (1) EP2336896B1 (zh)
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DK (1) DK2336896T3 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105808493A (zh) * 2015-01-19 2016-07-27 巴赫曼有限公司 带有耦合模块的串行总线系统

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104252282A (zh) * 2013-06-25 2014-12-31 山东巨洋神州信息技术有限公司 一种无线智显系统
CN103402105A (zh) * 2013-07-23 2013-11-20 江苏亿成光电科技有限公司 异步通信的主动式3d眼镜驱动装置
EP3404546B1 (en) * 2017-05-16 2019-09-11 Melexis Technologies NV Device for supervising and initializing ports
JP2019004205A (ja) * 2017-06-12 2019-01-10 株式会社村田製作所 転送装置

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US4455647A (en) * 1982-06-14 1984-06-19 Siemens Corporation Apparatus for establishing multi-address connections
US4538271A (en) * 1983-05-04 1985-08-27 At&T Information Systems Inc. Single parity bit generation circuit
US5128664A (en) * 1986-03-05 1992-07-07 Ampex Corporation Search technique for identifying slave devices connected to a serial bus
US4903262A (en) * 1987-08-14 1990-02-20 General Electric Company Hardware interface and protocol for a mobile radio transceiver
US5140679A (en) * 1988-09-14 1992-08-18 National Semiconductor Corporation Universal asynchronous receiver/transmitter
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105808493A (zh) * 2015-01-19 2016-07-27 巴赫曼有限公司 带有耦合模块的串行总线系统

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EP2336896B1 (en) 2012-08-22
CN102118223A (zh) 2011-07-06
DK2336896T3 (da) 2012-10-29
EP2336896A1 (en) 2011-06-22

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Owner name: GE FANUC INTELLIGENT PLATFORMS, INC., VIRGINIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LUECKENBACH, WILLIAM HENRY;REEL/FRAME:023665/0849

Effective date: 20091211

STCB Information on status: application discontinuation

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