US20110050350A1 - Amplifier circuit - Google Patents
Amplifier circuit Download PDFInfo
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- US20110050350A1 US20110050350A1 US12/872,589 US87258910A US2011050350A1 US 20110050350 A1 US20110050350 A1 US 20110050350A1 US 87258910 A US87258910 A US 87258910A US 2011050350 A1 US2011050350 A1 US 2011050350A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/66—Amplifiers simultaneously generating oscillations of one frequency and amplifying signals of another frequency
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/387—A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/391—Indexing scheme relating to amplifiers the output circuit of an amplifying stage comprising an LC-network
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/402—A series resonance being added in shunt in the output circuit, e.g. base, gate, of an amplifier stage
Definitions
- the present invention relates to an amplifier circuit using a transistor.
- a case is assumed that impedance when viewing a side of a load from a transistor output terminal is short-circuited for even-order harmonics and opened for odd-order harmonics.
- an output in the even-order harmonics includes only a current component while an output in the odd-order harmonics includes only a voltage component. That is, there is no power consumption in a harmonics circuit.
- An amplifier circuit adopting this principle is known as a Class-F amplifier circuit.
- the impedance when viewing the load side from the transistor output terminal is opened for the even-order harmonics and short-circuited for the odd-order harmonics.
- the output in the even-order harmonics includes only the voltage component while the output in the odd-order harmonics includes only a current component. That is, there is no power consumption in the harmonics.
- An amplifier circuit adopting this principle is known as an inverse Class-F amplifier circuit.
- FIG. 1 is a circuit diagram showing a configuration of a conventional amplifier circuit.
- This circuit includes an equivalent circuit of a transistor 1 , a matching circuit 19 , and a load resistor 18 .
- the equivalent circuit of the transistor 1 includes an equivalent output current source 7 , a drain-to-source capacitor 8 , and a drain inductor 9 .
- the drain-to-source capacitor 8 and the drain inductor 9 in the transistor 1 are a parasitic capacitor and a parasitic inductor, respectively.
- the parasitic capacitor and the parasitic inductor in the transistor 1 are not considered, for example, as shown in Patent Literatures 1, 2, and 3, the Class-F and inverse Class-F amplifier circuits can be achieved over any orders up to an infinite order.
- parasitic elements such as the drain-to-source capacitor and the drain inductor.
- a high-frequency region such as a microwave frequency range and a millimeter wave frequency range
- influence of these parasitic elements cannot be ignored, and the efficiency is not improved even if the order of harmonics to be processed is increased in a load circuit.
- Non-Patent Literature 1 a technique is disclosed in which a load conditions in the Class-F amplifier circuit and the inverse Class-F amplifier circuit are achieved up to the third harmonic wave in consideration of the parasitic capacitor and the parasitic inductor in the transistor.
- Patent Literature 1 JP 2003-234626A
- Patent Literature 2 JP 2005-117200A
- Patent Literature 3 JP 2009-130472A
- Non-Patent Literature 1 Y. Y Woo, et al., “Analysis and Experiments for High Efficiency Class-F and inverse Class-F power amplifier”, IEEE Trans. Microwave Theory and Techniques, vol. 54, no. 5, pp. 1969-1974, May 2006.
- each of the n stages comprises a parallel capacitor and a serial inductor; a resonant circuit section provided between the output node of the harmonic wave processing circuit and a ground node (voltage) and comprising (2n+1) resonators which have resonance frequencies different from each other; and a load resistance provided in a back stage of the harmonic wave processing circuit.
- the resonance frequencies of the (2n+1) resonators are coincident with frequencies of (n+1) poles and n zeros formed between the drain output node and the ground node in the transistor when the output node of the harmonic wave processing circuit is short-circuited to the ground node.
- the resonant frequencies of 2n resonators of the (2n+1) resonators are coincident with a frequency (2• 0 ) of second harmonic wave to a frequency of (2n+1) th harmonic wave ((2+1)• 0 ), respectively.
- FIG. 1 is a circuit diagram showing a configuration of a conventional amplifier circuit
- FIG. 2 is a circuit diagram showing a configuration of an amplifier circuit according to a first embodiment of the present invention
- FIG. 3 is a circuit diagram showing an equivalent circuit when viewing from an equivalent output current source in a case that an output terminal 5 is short-circuited;
- FIG. 4 is a circuit diagram showing a configuration of the amplifier circuit according to a second embodiment of the present invention.
- FIG. 5 is a circuit diagram showing a configuration of the amplifier circuit according to a third embodiment of the present invention.
- FIG. 6 is a circuit diagram showing a configuration of a modification of the amplifier circuit according to the third embodiment of the present invention.
- FIG. 2 is a circuit diagram showing a configuration of the amplifier circuit according to the first embodiment of the present invention.
- the amplifier circuit includes a transistor section 1 , a harmonics processing circuit section 2 , a resonant circuit section 3 , and an optional load resistor 18 (R L ).
- the transistor section 1 , the harmonic processing circuit section 2 , the resonant circuit section 3 , and the optional load resistor 18 (R L ) are connected in series in this order.
- the transistor section 1 expresses a transistor by its equivalent circuit.
- the equivalent circuit of the transistor there are an equivalent output current source 7 , a drain-to-source capacitor 8 (Co), and a drain inductor 9 (Lo).
- the drain-to-source capacitor 8 (Co) is a parallel parasitic capacitor for an output node 6 of the equivalent output current source 7 .
- the drain inductor 9 (Lo) is a series parasitic inductor between the equivalent output current source 7 and a drain output node 4 .
- the drain output node 4 is connected to one end of the drain inductor 9 (Lo).
- the other end of the drain inductor 9 (Lo) is connected to one end of the drain-to-source capacitor 8 (Co) and the output node 6 on one end side of the equivalent output current source 7 .
- the other end of the drain-to-source capacitor 8 (Co) and the other end of the equivalent output current source 7 are grounded.
- the harmonics processing circuit section 2 includes an input node 4 , the first and the second capacitors 10 (C 1 ) and 12 (C 2 ), the first and the second inductors 11 (L 1 ) and 13 (L 2 ), and an output node 5 .
- the input node 4 of the harmonics processing circuit section 2 and the drain output node 4 of the transistor section 1 are directly connected together, and thus expressed by the same reference numeral 4 .
- the input node 4 is connected to one end of the first capacitor 10 (C 1 ) and one end of the first inductor 11 (L 1 ).
- the other end of the first inductor 11 (L 1 ) is connected to one end of the second capacitor 12 (C 2 ) and one end of the second inductor (L 2 ).
- the other end of the second inductor 13 (L 2 ) is connected to the output node 5 .
- the respective other ends of the first and the second capacitors 10 (C 1 ) and 12 (C 2 ) are grounded.
- the first capacitor 10 (C 1 ) and the first inductor 11 (L 1 ) operate as a first one-stage inverse-L type ladder circuit.
- the second capacitor 12 (C 2 ) and the second inductor 13 (L 2 ) operate as a second one-stage inverse-L type ladder circuit.
- the second one-stage inverse-L type ladder circuit is connected at the subsequent stage of the first one-stage inverse-L type ladder circuit.
- the resonant circuit section 3 includes an output node 5 and first to fifth resonators 14 - 1 to 14 - 5 . These first to fifth resonators 14 - 1 to 14 - 5 respectively include first to fifth capacitors (Co 1 to Co 5 ) and first to fifth inductors (Lo 1 to Lo 5 ), respectively.
- the output node 5 in the resonant circuit section 3 and the output node 5 in the harmonics processing circuit section 2 are directly connected together and thus expressed by the same reference numeral 5 .
- Respective one ends of the first to the fifth capacitors (C o1 to C o5 ) are connected to the output node 5 .
- the respective other ends of the first to the fifth capacitors (C o1 to C o5 ) are connected to respective one ends of the first to the fifth inductors (L o1 to L o5 ).
- the respective other ends of the first to the fifth inductors (L o1 to L o5 ) are grounded.
- the output node 5 of the harmonics processing circuit section 2 is short-circuited to the ground node. Therefore, if the resonance frequencies are different from each other between these resonators 14 - 1 to 14 - 5 , the short-circuit condition is satisfied in a plurality of desired operation frequencies.
- the load resistor 18 (R L ) is connected between the output node 5 of the harmonics processing circuit section 2 and the ground node.
- An output signal of a base angular frequency ⁇ o can be taken out from the load resistor 18 (R L ).
- (n+1) poles and n zeros are formed between the input node 4 of the transistor section 1 and the ground node.
- the resonance angular frequencies of the resonators are set to respectively coincide with frequencies of the (n+1) poles and the n zeros.
- the resonance angular frequencies of four of the five resonators 14 - 1 to 14 - 5 are set to respectively coincide with the second harmonic wave (2 ⁇ 0 ) to fifth harmonic wave (5 ⁇ 0 ).
- the resonance angular frequency of the remaining one resonator is set to coincide with a pseudo resonance angular frequency due to the parasitic element of the transistor.
- FIG. 2 is an equivalent circuit when viewing a load side from the equivalent output current source 7 of the transistor section 1 in a case that the output node 5 is short-circuited to the ground node.
- the equivalent circuit includes an output node 6 of the equivalent output current source 7 , the first to the third capacitors 8 (C 0 ), 10 (C 1 ), and 12 (C 2 ), and the first to the third inductors 9 (L 0 ), 11 (L 1 ), and 13 (L 2 ).
- the output node 6 is connected to one end of the first capacitor 8 (C 0 ) and one end of the first inductor 9 (L 0 ).
- the other end of the first inductor 9 (L 0 ) is connected to one end of the second capacitor 10 (C 1 ) and one end of the second inductor 11 (L 1 ).
- the other end of the second inductor 11 (L 1 ) is connected to one end of the third capacitor 12 (C 2 ) and one end of the third inductor 13 (L 2 ).
- the respective other ends of the first, the second, and the third capacitors 8 (C 0 ), 10 (C 1 ), and 12 (C 2 ) and the other end of the third inductor 13 (L 2 ) are grounded.
- Input admittance Y(s) in the circuit shown in FIG. 2 is calculated from the following equation (1):
- the circuit in FIG. 2 is a pure reactance one-terminal pair circuit network.
- an admittance characteristic of the pure reactance one-terminal pair circuit network can be expressed by the following equation (2):
- • 1 , • 3 , and • 5 are angular frequencies when a numerator of an admittance function is zero, that is, show poles in an impedance function.
- • 2 and • 4 are angular frequencies when a denominator of the admittance function is zero, that is, represent zeros of the impedance function.
- the Class-F load condition or an inverse Class-F load condition is specified.
- a pole with no relation to the Class-F operation or the inverse Class-F operation is generated by the parasitic elements C 0 and L 0 .
- ⁇ 0 is a fundamental angular frequency
- • 3 3• 0
- ⁇ 1 serves as a pseudo resonance angular frequency due to the transistor parasitic elements.
- Y ⁇ ( s ) M ⁇ ⁇ s + 1 1 M ⁇ ( a - d ) ⁇ s + 1 M ⁇ ( a - d ) d - b - e a - d ⁇ s + 1 ( d - b - e a - d ) ⁇ s K 1 + 1 K 1 K 2 ⁇ s + M ⁇ ⁇ c K 2 ⁇ s ( 3 )
- a pseudo resonance angular frequency ⁇ 1 can be expressed as in the following equation (8) by use of the two zeros and the two poles as design items of the Class-F amplifier and the parasitic capacitor (C 0 ) and the parasitic inductor (L 0 ) in the transistor:
- ⁇ 0 is a fundamental angular frequency
- • s is a pseudo resonance frequency in the equation (2)
- a complete inverse Class-F load circuit can be provided which can perform processing not only on the fourth harmonic wave but also on up to the higher-order harmonics than the fourth harmonics.
- FIG. 4 is a circuit diagram showing a configuration of the amplifier circuit according to a second embodiment of the present invention.
- the configuration of the amplifier circuit in the present embodiment is equivalent to the circuit obtained by adding the following changes to the amplifier circuit according to the first embodiment of the present invention.
- the amplifier circuit in the present embodiment is the one obtained by adding a fundamental frequency impedance matching circuit 19 to the amplifier circuit of the first embodiment and also changing a connection position of the load resistor 18 from an output section of a high-frequency processing circuit section to an output section of the fundamental frequency impedance matching circuit 19 .
- the fundamental frequency impedance matching circuit 19 includes an inductor 20 and a capacitor 21 .
- One end of the inductor 20 is connected to an output node 5 of the high-frequency processing circuit section 2 .
- the other end of the inductor 20 is connected to one end of the capacitor 21 .
- the other end of the capacitor 21 is grounded. That is, in this configuration example, the fundamental frequency impedance matching circuit 19 is a one-stage filter circuit using the inductor and the capacitor.
- a connection portion between the inductor 20 and the capacitor 21 corresponds to the output node of the fundamental frequency impedance matching circuit 19 .
- a load resistor 18 is connected to the connection section between the inductor 20 and the capacitor 21 .
- the configuration example of the above fundamental frequency impedance matching circuit 19 is just one example and thus it may be a multiple-stage filter circuit or a distributed constant circuit.
- FIG. 5 is a circuit diagram showing a configuration of the amplifier circuit according to a third embodiment of the present invention.
- the configuration of the amplifier circuit of the present embodiment is equivalent to a circuit obtained by adding the following changes to the amplifier circuit according to the second embodiment of the present invention.
- the resonant circuit section 3 includes a plurality of resonators 14 - 1 to 14 - 5 in the second embodiment of the present invention
- the resonant circuit section 3 in the present embodiment includes a plurality of tip-open stubs 23 to 27 .
- the plurality of tip-open stubs 23 to 27 correspond to the plurality of resonators 14 - 1 to 14 - 5 and have the same functions as those of the plurality of resonators 14 - 1 to 14 - 5 .
- Respective ends of the plurality of tip-open stubs 23 to 27 are connected to an input node of the resonant circuit section 3 .
- the length of each of the plurality of tip-open stubs 23 to 27 is set to a one-quarter wave length corresponding to a desired resonance frequency. Therefore, the resonant circuit section 3 in the present embodiment operates in the same manner as the resonant circuit section 3 according to the second embodiment of the present invention.
- the plurality of tip-open stubs 23 to 27 may be formed in the same manner as those in conventional technique described in FIG. 3 of the Patent Literature 1, but it is needless to say that they may be formed in a different method as long as they are short-circuited at a connection node with a plurality of desired resonance frequencies.
- the first to third embodiments of the present invention may be combined in any combination within a technically consistence range.
- the existence of the fundamental frequency impedance matching circuit 19 is not always necessary and thus can be omitted. That is, the object of the present invention can be achieved even when the resonant circuit section 3 according to the first embodiment of the present invention is replaced with the resonant circuit section 3 according to the third embodiment of the present invention.
- the resonant circuit section 3 includes the five resonators 14 - 1 to 14 - 5 , but the resonant circuit section 3 is only required to include two or more resonators, which provides the same effect as the aforementioned effect.
- FIG. 6 is a circuit diagram of a configuration of an equivalent circuit in which the harmonics processing circuit section 2 in the third embodiment is configured from distributed circuits 31 and 32 .
- a ladder circuit of one stage of the serial inductor L and the parallel capacitor C has a characteristic impedance Z 0 shown in the following equation (9) and is equivalent to a distributed constant circuit of an electrical length •.
- • 0 denotes the fundamental frequency of the amplifier circuit.
- the circuit of the capacitor 10 and the inductor 11 in FIG. 5 is replaced by the distributed circuit 31 in FIG. 6
- the circuit of the capacitor 12 and the inductor 13 in FIG. 5 is replaced by the distributed circuit 32 in FIG. 6 .
- the operation of the amplifier circuit is same between those shown in FIGS. 4 and 6 .
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Abstract
Description
- This patent application claims a priority on convention based on Japanese Patent Application No. 2009-200817 filed on Aug. 31, 2009. The disclosure thereof is incorporated herein by Reference.
- The present invention relates to an amplifier circuit using a transistor.
- A case is assumed that impedance when viewing a side of a load from a transistor output terminal is short-circuited for even-order harmonics and opened for odd-order harmonics. In such a case, an output in the even-order harmonics includes only a current component while an output in the odd-order harmonics includes only a voltage component. That is, there is no power consumption in a harmonics circuit. Moreover, if setting a power factor in a fundamental wave to be −1, 100% power efficiency can be achieved. An amplifier circuit adopting this principle is known as a Class-F amplifier circuit.
- On the contrary, a case is assumed that the impedance when viewing the load side from the transistor output terminal is opened for the even-order harmonics and short-circuited for the odd-order harmonics. In such a case, the output in the even-order harmonics includes only the voltage component while the output in the odd-order harmonics includes only a current component. That is, there is no power consumption in the harmonics. Moreover, if setting a power factor in the fundamental wave to be −1, 100% power efficiency can be achieved. An amplifier circuit adopting this principle is known as an inverse Class-F amplifier circuit.
-
FIG. 1 is a circuit diagram showing a configuration of a conventional amplifier circuit. This circuit includes an equivalent circuit of atransistor 1, amatching circuit 19, and aload resistor 18. The equivalent circuit of thetransistor 1 includes an equivalent outputcurrent source 7, a drain-to-source capacitor 8, and adrain inductor 9. - Here, the drain-to-
source capacitor 8 and thedrain inductor 9 in thetransistor 1 are a parasitic capacitor and a parasitic inductor, respectively. In a case where the parasitic capacitor and the parasitic inductor in thetransistor 1 are not considered, for example, as shown inPatent Literatures - However, in an actual transistor, there are parasitic elements such as the drain-to-source capacitor and the drain inductor. Especially, in a high-frequency region such as a microwave frequency range and a millimeter wave frequency range, influence of these parasitic elements cannot be ignored, and the efficiency is not improved even if the order of harmonics to be processed is increased in a load circuit.
- For this reason, a Class-F amplifier circuit and an inverse Class-F amplifier circuit have been studied in which the parasitic capacitor and the parasitic inductor in a transistor are considered. In
Non-Patent Literature 1, a technique is disclosed in which a load conditions in the Class-F amplifier circuit and the inverse Class-F amplifier circuit are achieved up to the third harmonic wave in consideration of the parasitic capacitor and the parasitic inductor in the transistor. - However, no circuit is known which processes the fourth and the higher order harmonics. Accordingly, in an actual design, a trial design is made under the assumption that there is no parasitic element in a semiconductor element, and then it is necessary to perform experimental readjustment. In this case, it is very difficult to make the adjustment simultaneously in consideration of termination conditions of a large number of harmonics. Even if power efficiency of 100% can be achieved through adoption of the Class-F and inverse Class-F amplifier circuits in principle, the power efficiency in a microwave band has remained at approximately 80%.
- [Patent Literature 1]: JP 2003-234626A
- [Patent Literature 2]: JP 2005-117200A
- [Patent Literature 3]: JP 2009-130472A
- [Non-Patent Literature 1]: Y. Y Woo, et al., “Analysis and Experiments for High Efficiency Class-F and inverse Class-F power amplifier”, IEEE Trans. Microwave Theory and Techniques, vol. 54, no. 5, pp. 1969-1974, May 2006.
- It is a subject matter of the present invention to provide an amplifier circuit satisfying the load condition in a Class F or inverse Class F amplifier circuit over the fourth and the higher order harmonics while using a transistor having a parasitic capacitor and a parasitic inductor, which are not ignorable.
- In an aspect of the present invention, an amplifier circuit operating at a fundamental angular frequency •0, includes: a transistor which is represented by an equivalent circuit which includes: an equivalent output current source, a drain-source capacitor as a parallel parasitic capacitor to an output node of the equivalent output current source, and a drain inductor as a serial parasitic inductor connected between the equivalent output current source and a drain output node; a harmonic wave processing circuit which includes an input node connected with the drain output node; an output node; and a ladder circuit of n (n=1, 2, 3, . . . ) stages provided between the input node and the output node, wherein each of the n stages comprises a parallel capacitor and a serial inductor; a resonant circuit section provided between the output node of the harmonic wave processing circuit and a ground node (voltage) and comprising (2n+1) resonators which have resonance frequencies different from each other; and a load resistance provided in a back stage of the harmonic wave processing circuit. The resonance frequencies of the (2n+1) resonators are coincident with frequencies of (n+1) poles and n zeros formed between the drain output node and the ground node in the transistor when the output node of the harmonic wave processing circuit is short-circuited to the ground node. The resonant frequencies of 2n resonators of the (2n+1) resonators are coincident with a frequency (2•0) of second harmonic wave to a frequency of (2n+1)th harmonic wave ((2+1)•0), respectively.
- According to an amplifier circuit of the present invention, even by use of a transistor having a parasitic capacitor and a parasitic inductor which are not ignorable, a Class-F load condition or an inverse Class-F load condition over fourth and higher-order harmonics can be satisfied.
-
FIG. 1 is a circuit diagram showing a configuration of a conventional amplifier circuit; -
FIG. 2 is a circuit diagram showing a configuration of an amplifier circuit according to a first embodiment of the present invention; -
FIG. 3 is a circuit diagram showing an equivalent circuit when viewing from an equivalent output current source in a case that anoutput terminal 5 is short-circuited; -
FIG. 4 is a circuit diagram showing a configuration of the amplifier circuit according to a second embodiment of the present invention; -
FIG. 5 is a circuit diagram showing a configuration of the amplifier circuit according to a third embodiment of the present invention; and -
FIG. 6 is a circuit diagram showing a configuration of a modification of the amplifier circuit according to the third embodiment of the present invention. - Hereinafter, an amplifier circuit according to the present invention will be described in detail with reference to the attached drawings.
-
FIG. 2 is a circuit diagram showing a configuration of the amplifier circuit according to the first embodiment of the present invention. The amplifier circuit includes atransistor section 1, a harmonicsprocessing circuit section 2, aresonant circuit section 3, and an optional load resistor 18 (RL). - The
transistor section 1, the harmonicprocessing circuit section 2, theresonant circuit section 3, and the optional load resistor 18 (RL) are connected in series in this order. - The
transistor section 1 will be described below. Thetransistor section 1 expresses a transistor by its equivalent circuit. In the equivalent circuit of the transistor, there are an equivalent outputcurrent source 7, a drain-to-source capacitor 8 (Co), and a drain inductor 9 (Lo). Here, the drain-to-source capacitor 8 (Co) is a parallel parasitic capacitor for anoutput node 6 of the equivalent outputcurrent source 7. The drain inductor 9 (Lo) is a series parasitic inductor between the equivalent outputcurrent source 7 and adrain output node 4. - The connection relation between components of the
transistor section 1 will be described below. Thedrain output node 4 is connected to one end of the drain inductor 9 (Lo). The other end of the drain inductor 9 (Lo) is connected to one end of the drain-to-source capacitor 8 (Co) and theoutput node 6 on one end side of the equivalent outputcurrent source 7. The other end of the drain-to-source capacitor 8 (Co) and the other end of the equivalent outputcurrent source 7 are grounded. - The harmonics
processing circuit section 2 will be described below. The harmonicsprocessing circuit section 2 includes aninput node 4, the first and the second capacitors 10 (C1) and 12 (C2), the first and the second inductors 11 (L1) and 13 (L2), and anoutput node 5. Theinput node 4 of the harmonicsprocessing circuit section 2 and thedrain output node 4 of thetransistor section 1 are directly connected together, and thus expressed by thesame reference numeral 4. - The connection relation between components in the harmonics
processing circuit section 2 will be described below. Theinput node 4 is connected to one end of the first capacitor 10 (C1) and one end of the first inductor 11 (L1). The other end of the first inductor 11 (L1) is connected to one end of the second capacitor 12 (C2) and one end of the second inductor (L2). The other end of the second inductor 13 (L2) is connected to theoutput node 5. The respective other ends of the first and the second capacitors 10 (C1) and 12 (C2) are grounded. - In other words, the first capacitor 10 (C1) and the first inductor 11 (L1) operate as a first one-stage inverse-L type ladder circuit. Similarly, the second capacitor 12 (C2) and the second inductor 13 (L2) operate as a second one-stage inverse-L type ladder circuit. In the harmonics
processing circuit section 2, the second one-stage inverse-L type ladder circuit is connected at the subsequent stage of the first one-stage inverse-L type ladder circuit. - The
resonant circuit section 3 will be described below. Theresonant circuit section 3 includes anoutput node 5 and first to fifth resonators 14-1 to 14-5. These first to fifth resonators 14-1 to 14-5 respectively include first to fifth capacitors (Co1 to Co5) and first to fifth inductors (Lo1 to Lo5), respectively. Theoutput node 5 in theresonant circuit section 3 and theoutput node 5 in the harmonicsprocessing circuit section 2 are directly connected together and thus expressed by thesame reference numeral 5. - The connection relation between components in the
resonant circuit section 3 will be described below. Respective one ends of the first to the fifth capacitors (Co1 to Co5) are connected to theoutput node 5. The respective other ends of the first to the fifth capacitors (Co1 to Co5) are connected to respective one ends of the first to the fifth inductors (Lo1 to Lo5). The respective other ends of the first to the fifth inductors (Lo1 to Lo5) are grounded. - In other words, in the
resonant circuit section 3, the five resonators having resonance frequencies determined based on circuits of the capacitor and the inductor connected in series are connected in parallel. Here, the resonance frequencies of the respective five resonators are different from one another. It should be noted that there is possibly a case where zeros or poles derived from parasitic elements of the transistor are coincident with the frequencies cooperation harmonics of the amplifier (degeneracy), but such a case is a rare desirable case. The number of parallel resonators in such a case may be 2n. - One end of the load resistor 18 (RL) is connected to the
output node 5 of theresonant circuit section 3. The other end of the load resistor 18 (RL) is grounded. - Due to zero impedance on resonance in these resonators 14-1 to 14-5, the
output node 5 of the harmonicsprocessing circuit section 2 is short-circuited to the ground node. Therefore, if the resonance frequencies are different from each other between these resonators 14-1 to 14-5, the short-circuit condition is satisfied in a plurality of desired operation frequencies. - As described above, the load resistor 18 (RL) is connected between the
output node 5 of the harmonicsprocessing circuit section 2 and the ground node. An output signal of a base angular frequency ωo can be taken out from the load resistor 18 (RL). When theoutput node 5 of the harmonicsprocessing circuit section 2 is short-circuited to the ground node, (n+1) poles and n zeros are formed between theinput node 4 of thetransistor section 1 and the ground node. Here, the resonance angular frequencies of the resonators are set to respectively coincide with frequencies of the (n+1) poles and the n zeros. At the same time, the resonance angular frequencies of four of the five resonators 14-1 to 14-5 are set to respectively coincide with the second harmonic wave (2ω0) to fifth harmonic wave (5ω0). Moreover, the resonance angular frequency of the remaining one resonator is set to coincide with a pseudo resonance angular frequency due to the parasitic element of the transistor. -
FIG. 2 is an equivalent circuit when viewing a load side from the equivalent outputcurrent source 7 of thetransistor section 1 in a case that theoutput node 5 is short-circuited to the ground node. - The equivalent circuit includes an
output node 6 of the equivalent outputcurrent source 7, the first to the third capacitors 8 (C0), 10 (C1), and 12 (C2), and the first to the third inductors 9 (L0), 11 (L1), and 13 (L2). - The
output node 6 is connected to one end of the first capacitor 8 (C0) and one end of the first inductor 9 (L0). The other end of the first inductor 9 (L0) is connected to one end of the second capacitor 10 (C1) and one end of the second inductor 11 (L1). The other end of the second inductor 11 (L1) is connected to one end of the third capacitor 12 (C2) and one end of the third inductor 13 (L2). The respective other ends of the first, the second, and the third capacitors 8 (C0), 10 (C1), and 12 (C2) and the other end of the third inductor 13 (L2) are grounded. - Input admittance Y(s) in the circuit shown in
FIG. 2 is calculated from the following equation (1): -
- where s=jω.
- On the other hand, the circuit in
FIG. 2 is a pure reactance one-terminal pair circuit network. Typically, an admittance characteristic of the pure reactance one-terminal pair circuit network can be expressed by the following equation (2): -
- where Y(s) in the equation (1) and Y(s) in the equation (2) show admittances of the same circuit.
- In the equation (2), •1, •3, and •5 are angular frequencies when a numerator of an admittance function is zero, that is, show poles in an impedance function. Similarly, in the equation (2), •2 and •4 are angular frequencies when a denominator of the admittance function is zero, that is, represent zeros of the impedance function.
- Moreover, in the equation (2), M=a6/b5.
- By previously setting impedance at each harmonic wave when viewing the load side from the equivalent output
current source 7, to be zero or infinite (pole), that is, setting the admittance to be infinite (corresponding to zero of impedance) or zero (corresponding to an pole of the impedance) based on the equation (2), the Class-F load condition or an inverse Class-F load condition is specified. At the same time, a pole with no relation to the Class-F operation or the inverse Class-F operation is generated by the parasitic elements C0 and L0. Thus, it is possible to provide as an ideal Class-F frequency characteristic or an inverse Class-F frequency characteristic, the frequency characteristic when viewing the load side from the equivalent outputcurrent source 7 in the state in which the parasitic elements of the transistor are considered. - For example, it is assumed that ω0 is a fundamental angular frequency, •2=2•0 and •4=4•0 are zeros, •3=3•0 and •5=5ω0 are poles in the equation (2). In this case, it possible to provide a complete Class-F amplifier circuit which can process up to the fourth harmonic waves while considering influence of the parasitic elements of the transistor. At this time, ω1 serves as a pseudo resonance angular frequency due to the transistor parasitic elements.
- A quotient and a residue equation are obtained by dividing the numerator by the denominator in the third term of the equation (2), and the numerator is divided by the denominator in this residue equation. By repeating this operation, an equation expressed by continued fraction can be obtained, as shown in the following equation (3):
-
- where a, b, c, d, e, K1, and K2 are defined as in the following equations (4) and (5):
-
- By comparing coefficients in the equation (3) and the equation (1), it is possible to provide a complete Class-F load circuit which can perform harmonics processing up to the fourth harmonic wave while the parasitic elements of the transistor are considered. Each of circuit parameters is more specifically obtained as in the following equation (6):
-
- The following equation (7) can be obtained from the equations (6) and (4):
-
- A pseudo resonance angular frequency ω1 can be expressed as in the following equation (8) by use of the two zeros and the two poles as design items of the Class-F amplifier and the parasitic capacitor (C0) and the parasitic inductor (L0) in the transistor:
-
- On the other hand, it is assumed that ω0 is a fundamental angular frequency, •1=2•0 and •3=4•3 are zeros, •2=3•3 and •4=5ω0 are poles in the equation (2). In this case, when •s is a pseudo resonance frequency in the equation (2), it is possible to provide a complete inverse Class-F amplifier circuit processing up to the fourth harmonic wave while the parasitic elements of the transistor are considered. In a case of the inverse Class-F amplifier circuit, a complete inverse Class-F load circuit can be provided which can perform processing not only on the fourth harmonic wave but also on up to the higher-order harmonics than the fourth harmonics.
-
FIG. 4 is a circuit diagram showing a configuration of the amplifier circuit according to a second embodiment of the present invention. The configuration of the amplifier circuit in the present embodiment is equivalent to the circuit obtained by adding the following changes to the amplifier circuit according to the first embodiment of the present invention. Specifically, the amplifier circuit in the present embodiment is the one obtained by adding a fundamental frequencyimpedance matching circuit 19 to the amplifier circuit of the first embodiment and also changing a connection position of theload resistor 18 from an output section of a high-frequency processing circuit section to an output section of the fundamental frequencyimpedance matching circuit 19. - A configuration example of the fundamental frequency
impedance matching circuit 19 will be described below. As shown inFIG. 4 , the fundamental frequencyimpedance matching circuit 19 includes aninductor 20 and acapacitor 21. One end of theinductor 20 is connected to anoutput node 5 of the high-frequencyprocessing circuit section 2. The other end of theinductor 20 is connected to one end of thecapacitor 21. The other end of thecapacitor 21 is grounded. That is, in this configuration example, the fundamental frequencyimpedance matching circuit 19 is a one-stage filter circuit using the inductor and the capacitor. - A connection portion between the
inductor 20 and thecapacitor 21 corresponds to the output node of the fundamental frequencyimpedance matching circuit 19. Aload resistor 18 is connected to the connection section between theinductor 20 and thecapacitor 21. - It should be noted that the configuration example of the above fundamental frequency
impedance matching circuit 19 is just one example and thus it may be a multiple-stage filter circuit or a distributed constant circuit. - The other configurations, connection relation between components, operation, etc. of the amplifier circuit of the present embodiment are the same as those of the first embodiment of the present invention. Thus, more detailed description thereof will be omitted.
- Performing the fundamental frequency impedance matching by the fundamental frequency
impedance matching circuit 19, it is possible to bring a power factor at the fundamental frequency closer to −1. -
FIG. 5 is a circuit diagram showing a configuration of the amplifier circuit according to a third embodiment of the present invention. The configuration of the amplifier circuit of the present embodiment is equivalent to a circuit obtained by adding the following changes to the amplifier circuit according to the second embodiment of the present invention. Specifically, while theresonant circuit section 3 includes a plurality of resonators 14-1 to 14-5 in the second embodiment of the present invention, theresonant circuit section 3 in the present embodiment includes a plurality of tip-open stubs 23 to 27. The plurality of tip-open stubs 23 to 27 correspond to the plurality of resonators 14-1 to 14-5 and have the same functions as those of the plurality of resonators 14-1 to 14-5. - Respective ends of the plurality of tip-
open stubs 23 to 27 are connected to an input node of theresonant circuit section 3. The length of each of the plurality of tip-open stubs 23 to 27 is set to a one-quarter wave length corresponding to a desired resonance frequency. Therefore, theresonant circuit section 3 in the present embodiment operates in the same manner as theresonant circuit section 3 according to the second embodiment of the present invention. The plurality of tip-open stubs 23 to 27 may be formed in the same manner as those in conventional technique described in FIG. 3 of thePatent Literature 1, but it is needless to say that they may be formed in a different method as long as they are short-circuited at a connection node with a plurality of desired resonance frequencies. - Other configuration, connection relation between components, operation, etc. of the amplifier circuit of the present embodiment are the same as those of the second embodiment of the present invention, and therefore more detailed description thereof will be omitted.
- The first to third embodiments of the present invention may be combined in any combination within a technically consistence range. For example, in the amplifier circuit according to the third embodiment of the present invention, the existence of the fundamental frequency
impedance matching circuit 19 is not always necessary and thus can be omitted. That is, the object of the present invention can be achieved even when theresonant circuit section 3 according to the first embodiment of the present invention is replaced with theresonant circuit section 3 according to the third embodiment of the present invention. Moreover, in the description of the first and second embodiments of the present invention, theresonant circuit section 3 includes the five resonators 14-1 to 14-5, but theresonant circuit section 3 is only required to include two or more resonators, which provides the same effect as the aforementioned effect. Moreover, a case that n=2 has been described here, but it is needless to say that n may be any positive integer number (n=1, 2, 3, or the like) and, for example, the number of resonators may be six or seven where n=3 or larger. -
FIG. 6 is a circuit diagram of a configuration of an equivalent circuit in which the harmonicsprocessing circuit section 2 in the third embodiment is configured from distributedcircuits -
- Therefore, the circuit of the
capacitor 10 and theinductor 11 inFIG. 5 is replaced by the distributedcircuit 31 inFIG. 6 , and the circuit of thecapacitor 12 and theinductor 13 inFIG. 5 is replaced by the distributedcircuit 32 inFIG. 6 . The operation of the amplifier circuit is same between those shown inFIGS. 4 and 6 .
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Cited By (5)
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US8947166B2 (en) | 2011-06-28 | 2015-02-03 | Panasonic Intellectual Property Management Co., Ltd. | Radio frequency power amplifier |
EP2752990A4 (en) * | 2011-08-29 | 2015-07-08 | Univ Electro Communications | High-efficiency power amplifier |
CN109936338A (en) * | 2019-05-07 | 2019-06-25 | 成都理工大学 | A kind of five rank of high efficiency is against F power-like amplifier |
EP3051694B1 (en) * | 2015-01-27 | 2019-07-24 | Kabushiki Kaisha Toshiba | High-frequency semiconductor amplifier |
KR102512214B1 (en) * | 2022-05-02 | 2023-03-20 | 비테스코 테크놀로지스 게엠베하 | Filter circuit for preventing short |
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JP5759286B2 (en) * | 2011-06-27 | 2015-08-05 | 住友電気工業株式会社 | Switching circuit |
WO2013073544A1 (en) * | 2011-11-17 | 2013-05-23 | 日本電気株式会社 | Inverse class-f amplification circuit and parasitic circuit compensation method for inverse class-f amplification circuit |
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DE102007060811A1 (en) * | 2007-09-01 | 2009-03-05 | Maquet Gmbh & Co. Kg | Device and method for wireless energy and / or data transmission between a source device and at least one target device |
JP2009130472A (en) * | 2007-11-20 | 2009-06-11 | Univ Of Electro-Communications | Inverse class-f amplifier circuit |
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US6177841B1 (en) * | 1998-09-28 | 2001-01-23 | Mitsubishi Denki Kabushiki Kaisha | High frequency power amplifier |
US7161434B2 (en) * | 2001-11-15 | 2007-01-09 | Filtronic Plc | Amplifier |
US7741907B2 (en) * | 2007-04-12 | 2010-06-22 | Kabushiki Kaisha Toshiba | Class-F power amplifier circuit |
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US8947166B2 (en) | 2011-06-28 | 2015-02-03 | Panasonic Intellectual Property Management Co., Ltd. | Radio frequency power amplifier |
EP2752990A4 (en) * | 2011-08-29 | 2015-07-08 | Univ Electro Communications | High-efficiency power amplifier |
US9257948B2 (en) | 2011-08-29 | 2016-02-09 | The University Of Electro-Communications | High efficiency power amplifier |
EP3051694B1 (en) * | 2015-01-27 | 2019-07-24 | Kabushiki Kaisha Toshiba | High-frequency semiconductor amplifier |
CN109936338A (en) * | 2019-05-07 | 2019-06-25 | 成都理工大学 | A kind of five rank of high efficiency is against F power-like amplifier |
KR102512214B1 (en) * | 2022-05-02 | 2023-03-20 | 비테스코 테크놀로지스 게엠베하 | Filter circuit for preventing short |
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CN102006019A (en) | 2011-04-06 |
US8154348B2 (en) | 2012-04-10 |
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JP5408616B2 (en) | 2014-02-05 |
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