JP4143805B2 - Harmonic processing circuit and amplifier circuit using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a load circuit capable of reducing the number of stubs and a highly efficient amplifier circuit using it. <P>SOLUTION: First stubs respectively have a transmission line length L indicated by L=&lambda;/4m (where m=2, 3, 4,..., n). Of the first stubs T<SB>2</SB>-T<SB>n</SB>, the one having the transmission line length corresponding to m indicated by m=pk (where p is an odd number &ge;3 and k is an integer &ge;2) is omitted. In the example of n=7, the installation of the first stub T<SB>6</SB>is omitted. Even when constituted in such a manner, a characteristic impedance in the load circuit is equivalent to a circuit for which deletion is not performed. Thus, the number of the stubs is reduced. Also, by using a synthetic compensation stub T* instead of a plurality of compensation stubs, the number of the stubs is reduced further. Even when doing so, influence exerted to fundamental waves by residual reactance due to the first stubs can be eliminated. <P>COPYRIGHT: (C)2003,JPO

Description

で表される。（１）式は、ｆ＝ｆ_ｋ，３ｆ_ｋ，５ｆ_ｋ，７ｆ_ｋ…＝ｋｆ_０，３ｋｆ_０，５ｋｆ_０，…において
【数２】

ただし、ｆ＝ｆ_０，５ｆ_０，９ｆ_０，… のとき＋，
ｆ＝ ３ｆ_０，７ｆ_０，１１ｆ_０，…のとき−
となり、従って、このときの入力インピーダンスＺ_ｉｎｋは、
【数３】

となる。さらに、Ｔ_ｋは先端開放であるから、Ｉ_２＝０によりＺ_ｉｎｋ＝０となる。
【００２９】
このことから、第１スタブＴ_kを設けることで、ｋ次高調波以外にも３ｋ次、５ｋ次、７ｋ次、・・・という各高調波におけるＡ点でのインピーダンスが零となることが判る。従来は、各高調波に対応する第１スタブを一本づつ設けていた。つまり、２次高調波に対しＴ₂、３次高調波に対しＴ₃というスタブを設けていた。しかしながら、前記の考察から明らかなように、スタブＴ_ｋがあれば、Ｔ_３ｋ，Ｔ_５ｋ，Ｔ_７ｋ，・・・を設ける必要はない。つまり、Ｔ_３ｋ，Ｔ_５ｋ，Ｔ_７ｋ，・・・を省いても、Ｔｋがそれらの代わりとなり、省く前と同様の負荷インピーダンス特性（奇数次高調波に対し開放、偶数次高調波に対し短絡）を実現できる。具体的には、Ｔ_２によって代替可能なＴ_６，Ｔ_１０，Ｔ_１４，・・・、Ｔ_３によって代替可能なＴ_９，Ｔ_１５，Ｔ_２１，・・・、Ｔ_４によって代替可能なＴ_１２，Ｔ_２０，Ｔ_２８，・・・を省く事ができる。表１に、Ｔ_ｋを設けた場合に省略できるスタブを示す。
【００３０】
【表１】

【００３１】
以上をまとめると、省くことのできる高調波処理スタブは「既に設けられているスタブにおけるｍの値が２以上の整数であるときに、そのｍの奇数倍の高調波に対応するスタブＴ_ｍ」と言える。言い換えれば、この定義に当てはまらない、ｍの値が２の階乗と素数とであるスタブ、具体的には Ｔ_２，Ｔ_３，Ｔ_４，Ｔ_５，Ｔ_７，・・・は、省かれずに残る。そして、それらのみで、所望の負荷インピーダンス特性が得られる。もちろん、どの次数までを考慮してスタブを設けるかは任意の設計事項である。また、省略できるすべてのスタブを省略することは必須ではなく、一部を残存させておくことも理論的には可能である。
【００３２】
このように、本実施形態では、第１スタブの数を従来に比べて削減することができる。したがって、スタブ設置に要する面積を小さくすることができ、さらに、スタブ実装工程が容易となるという利点がある。
【００３３】
本実施形態に係る負荷回路の負荷インピーダンス特性を図６（ｂ）に示す。比較のため、第１スタブを削減していない場合（図１に示す従来技術）の負荷インピーダンスを図６（ａ）に示す。本実施形態の回路においても、削減前の回路と同様に、負荷インピーダンスは、奇数次高調波に対して開放、偶数次高調波に対して短絡となっている。しかも、基本波（１．９ＧＨｚ）に対する負荷インピーダンスは等しい。これにより、本実施形態の回路は、削減前の回路と同様の負荷インピーダンスを有していることが判る。
【００３４】
つぎに、合成補償スタブＴ^＊を用いることができる理由について説明する。前記した第１スタブＴ_２〜Ｔ_ｎ（前記に従って一部のスタブが削減されたもの）の合成入力アドミタンスをＹ_ｉｎＴとする。スタブＴ^＊は、このアドミタンスＹ_ｉｎＴと大きさが等しく逆符号の入力アドミタンスを有している。したがって、この一本のスタブＴ^＊により、第１スタブＴ_２〜Ｔ_ｎが基本波に与える影響（残留リアクタンスの影響）を除去することができる。従来は、第１スタブの一本ごとに一本の補償スタブを設けていた。しかしながら、本実施形態では、前記した理由により、補償スタブの数を削減することができる。よって、本実施形態では、スタブ設置に要する面積をさらに、小さくすることができる。また、本実施形態では、スタブ実装工程をさらに容易とすることができる。
【００３５】
合成補償スタブＴ^＊を得る方法についてさらに具体的に説明する。先端開放の伝送線路（長さｌ、伝搬定数β、特性インピーダンスＺ_０）の入力アドミタンスＹは、
【数４】

で表される。これから、スタブＴ_ｋにおける、基本波に対する入力アドミタンスＹ_ｉｎｋは、以下の通りとなる。すなわち、まず、基本波の伝搬定数βは、β＝β_０＝２π／λ_０となる。さらに、スタブＴ_ｋは、ｋ次高調波（波長λ_ｋ＝λ_０／ｋ）に対する４分の１波長線路であるから、その長さｌは、ｌ＝λ_ｋ／４＝λ_０／４ｋとなる。これらを（４）式に代入すると、
【数５】

となる。
【００３６】
一方、第１スタブＴ_２〜Ｔ_７全体の合成入力アドミタンスをＹ_inTとすると、
【数６】

となる。したがって、合成補償スタブＴ^＊（長さＬ_ｈ）の入力インピーダンスＹ_inhをＹ_inh＝−Ｙ_inTとすることにより、第１スタブが基本波に与える影響を、一本の合成補償スタブによって除去することができる。
【００３７】
つぎに、先端開放の伝送線路により合成補償スタブT^＊を構成する例について説明する。前記（４）および（６）式より、
【数７】

である。すると、長さＬ_ｈは、
【数８】

となる。これを実際に計算すると、
Ｌｈ＝０．３０９５９２５３λ_０≒０．３λ_０
のように求めることができる。
【００３８】
なお、この実施形態では、第１の伝送線路Ｔ１１の出力端子と負荷抵抗Ｒ_０との間に、基本波の波長（λ）の１／４の長さを有する第２伝送線路Ｔ_１２を接続している。このため、この実施形態では、基本波における増幅動作に対して適切な負荷インピーダンスを、伝送線路Ｔ_１２の特性インピーダンスを変化させることにより実現できるという利点がある。しかも、この場合には、伝送線路Ｔ_１２の特性インピーダンスの変化は、高調波のための負荷インピーダンスには一切影響を与えないという利点もある。
【００３９】
【実施例】
本実施形態の負荷回路を、下記条件の増幅用トランジスタＳに適用した。
飽和ドレイン電流：６０ｍＡ
しきい値電圧：−０．９Ｖ
電源電圧：３．４Ｖ
最大発振周波数ｆ_max：７０ＧＨｚ
構成：ヘテロ接合ＦＥＴ
【００４０】
この場合の、ドレイン電流端子における電圧・電流特性を、ハーモニックバランスシミュレータにより計算した。その結果を図７に示す。瞬時電圧と瞬時電流との重なりがほぼ無くなっており、理想的なＦ級動作に近い動作を実現している。このときの付加電力効率（Power-added Efficiency, PAE）を図８に示す。この図から、ＰＡＥはほぼ９０％に達することが判る。なお、この図において、Ｐ_outは、負荷抵抗において得られる出力電力を示している。
【００４１】
次に、本発明の第２実施形態に係る負荷回路を説明する。前記した第１実施形態においては、補償用のスタブとして、合成補償スタブＴ^＊を用いた。しかしながら、第２実施形態では、これに代えて、複数の補償用の第２スタブを設ける構成とした。その回路の例を図９に示す。ここでは、第１スタブＴ_２〜Ｔ_７に対応して、補償用の第２スタブＴ_２ ^＊〜Ｔ_７ ^＊が設けられている。もちろん、省略された第１スタブに対応する第２スタブは省略されている。この構成においても、前記した実施形態と同様に、残留リアクタンスによる、基本波への影響を除去することができる。この場合の動作は、前記した文献１に記載された通りなので、詳細の説明は省略する。また、この実施形態においても、第１スタブＴ_６と第２スタブＴ_６ ^＊とを省略しているので、その分、スタブの数を削減することができる。また、第２実施形態においては、さらに、第２スタブのそれぞれの伝送線路長Ｌ_ｈを、
Ｌ_ｈ＝（２ｍ−１）λ／４ｍ （ただしｍ＝２，３，４，…，ｎ）
という関係を満たすものとした。このように設定すると、伝送線路長Ｌ_ｈ＋Ｌが常にλ／２となるので、インピーダンス補償の設計が容易であるという利点がある。
【００４２】
さらに、第２実施形態においては、複数の第１スタブと複数の第２スタブとが、互いに線対称となる位置に配置されている。このように配置することにより、多数のスタブを、一点（この例では出力端子Ａ）を基準として並列接続することができる。このため、スタブ配置に要する面積を小さくしうるという利点がある。
【００４３】
なお、前記各実施形態の記載は単なる一例に過ぎず、本発明に必須の構成を示したものではない。各部の構成は、本発明の趣旨を達成できるものであれば、上記に限らない。例えば、前記実施形態では、増幅用素子としてトランジスタを用いたが、これに代えて、負性抵抗の２端子増幅素子を用いることもできる。そのような素子の一例は、ガンダイオードである。
【００４４】
【発明の効果】
本発明によれば、スタブ数を減少させることができる負荷回路、および、それを用いた高効率な増幅回路を提供することができる。
【図面の簡単な説明】
【図１】従来の負荷回路を用いた増幅回路を示す図である。
【図２】図１に示す回路を基板上に実装した一例を示す説明図である。
【図３】本発明の第１実施形態に係る負荷回路を示す図である。
【図４】図３に示す負荷回路を用いた増幅回路を示す図である。
【図５】第１実施形態を説明するために用いる２端子回路を示す図である。
【図６】図（ａ）は、従来の負荷回路における負荷インピーダンス特性を示すグラフであり、図（ｂ）は、第１実施形態の負荷回路における負荷インピーダンス特性を示すグラフである。
【図７】本発明の第１実施形態に係る増幅回路を用いた実施例の結果を示す図であり、トランジスタのドレイン端子における電圧・電流特性を示すグラフである。
【図８】本発明の第１実施形態に係る増幅回路を用いた実施例の結果を示す図であり、回路の負荷電力特性を示すグラフである。
【図９】本発明の第２実施形態に係る負荷回路を示す図である。
【符号の説明】
ｆ_０ 基本波の周波数
２ｆ_０，３ｆ_０，４ｆ_０，５ｆ_０，６ｆ_０，７ｆ_０ 高調波の周波数
Ａ 第１伝送線路の出力端子
Ｃ 第１伝送線路の入力端子
Ｃ_１・Ｃ_２ カップリングコンデンサ
Ｓ 増幅用トランジスタ
Ｒ_０ 負荷抵抗
Ｔ^＊ 合成補償スタブ
Ｔ_１１ 第１伝送線路
Ｔ_１２ 第２伝送線路
Ｔ_２〜Ｔ_ｎ 第１スタブ
Ｔ_２ ^＊〜Ｔ_ｎ ^＊ 第２スタブ（補償スタブ）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a harmonic processing circuit and an amplifier circuit using the same.
[0002]
[Prior art]
In recent years, transistors capable of high-speed operation such as HEMT and HBT have been put into practical use. According to these elements, an operating frequency in the 50 to 60 GHz band can be realized. By the way, in these elements, in order to improve a gain, a harmonic may be utilized actively. In this case, it is desirable to suppress power consumption due to harmonics in order to improve power efficiency.
[0003]
For such a purpose, a load circuit capable of realizing a so-called class F amplification operation is desired. In an ideal class F amplification, there is no overlap between the instantaneous current and the instantaneous voltage at the output of the transistor, so that power consumption can be reduced. As load circuits for that purpose, for example, there are those disclosed in Japanese Patent Application Laid-Open No. 2001-111362 (Reference 1) and Japanese Patent No. 2513146 (Reference 2). The load circuit and mounting layout shown in Document 1 are shown in FIGS.
[0004]
The load circuit is one which is connected to the output terminal of the amplifying transistor Q _1. This load circuit includes a first transmission line _{T 11,} the second transmission line _{T 12,} the stub _T 2 through T _7, and a compensation stub _T 2 'through T _7' as main components. The output terminal of the second transmission line T ₁₂ is connected to a load resistance R _0.
[0005]
According to this circuit, since the stubs T _{2 to} T ₇ are provided, with respect to the _{second to seventh} harmonics 2f ₀ , 3f ₀ , 4f ₀ , 5f ₀ , 6f ₀ , 7f _{0 at} the terminal A, Impedance can be made zero. Here, it is the f ₀ the fundamental frequency of the amplification. Further, according to this circuit, since the compensation stubs T ₂ ′ to T ₇ ′ are provided, the residual reactance component in the stubs T _{2 to} T ₇ can be made zero. With these configurations, power efficiency can be improved.
[0006]
However, if this load circuit is to be mounted, it is necessary to provide a large number of stubs in a limited space as shown in FIG. It describes to T ₆ in FIG. Even in this state, not only does the mounting area increase, but the work of configuring the stub in a narrow space becomes complicated. Moreover, the provision of the T ₇ or more stubs will be accompanied by considerable difficulties.
[0007]
[Problems to be solved by the invention]
The present invention has been made in view of the above circumstances. It is an object of the present invention to provide a load circuit that can reduce the number of stubs.
[0008]
[Means for Solving the Problems]
The harmonic processing circuit according to claim 1 is a circuit that is connected between an output terminal of the amplifying transistor and a load resistor, and processes a harmonic appearing at the output terminal of the transistor. In this circuit, the output of the amplifying transistor is input, and the first transmission line having a length ¼ of the fundamental wave wavelength (λ) in the output of the amplifying transistor, and the output of the first transmission line And a plurality of first stubs connected in parallel to each other.
Further, the plurality of first stubs are:
L = λ / 4m (where m = 2, 3, 4,..., N)
Each having a transmission line length L represented by
And,
m ′ = pk (where p is an odd number greater than or equal to 3, and k is m in the first stub currently provided among the m)
Any or all of the first stubs having a transmission line length corresponding to m ′ represented by
The harmonic processing circuit further includes a synthesis compensation stub. The composite compensation stub is connected to the output terminal of the first transmission line, and the admittance of the composite compensation stub with respect to the fundamental wave is equal in magnitude and opposite to the composite input admittance of the first stub. Yes.
[0009]
A harmonic processing circuit according to a second aspect is the one according to the first aspect, further comprising a plurality of second stubs connected in parallel to the output terminal of the first transmission line. The transmission line lengths Lh of these second stubs are set to lengths that satisfy Lh + L = λ / 2.
[0011]
Harmonic processing circuit of claim 2, in those of claim 1, wherein, the synthetic compensation stub are those of the open-end.
[0012]
A harmonic processing circuit according to a third aspect is the one according to the first aspect, wherein the composite compensation stub is a short-circuited tip.
[0015]
The harmonic processing circuit according to claim 4 is the harmonic processing circuit according to any one of claims 1 to 3 , wherein the harmonic processing circuit is connected between an output terminal of the first transmission line and the load resistor, and The configuration further includes a second transmission line having a length of ¼ of the wavelength (λ) of the wave.
[0017]
According to a fifth aspect of the present invention, in the harmonic processing circuit according to any one of the first to fourth aspects, a negative resistance two-terminal amplifying element is used instead of the amplifying transistor.
[0018]
6. The harmonic processing circuit according to claim 6, wherein the harmonic processing circuit is connected between an output terminal of the amplifying transistor and a load resistor, and processes harmonics appearing at the output terminal of the transistor. An input terminal to which the output of the transistor is input, a first transmission line having a length of ¼ of the wavelength (λ) of the fundamental wave in the output of the amplification transistor, and an output terminal of the first transmission line A plurality of first stubs connected in parallel to each other;
The plurality of first stubs are:
L = λ / 4m (where m = 2, 3, 4,..., N)
Each having a transmission line length L represented by:
Further, a composite compensation stub is provided, and the composite compensation stub is connected to an output terminal of the first transmission line, and an admittance of the composite compensation stub with respect to a fundamental wave is equal to a composite input admittance of the first stub. They are equal and have opposite signs.
Harmonic processing circuit of claim 7, wherein, in the pump of Claim 1, in place of the synthetic compensation stub are connected to an output terminal of said first transmission line, and combining the input of said first stub It is configured to have a reactance element that is equal in magnitude to the admittance and has the opposite sign .
[0019]
The amplifier circuit according to claim 8 is configured such that an input terminal of the first transmission line in the harmonic processing circuit according to any one of claims 1 to 7 is connected to an output terminal of the amplification transistor. It has a configuration.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
A load circuit according to a first embodiment of the present invention will be described with reference to the accompanying drawings. First, the configuration of this load circuit will be described with reference to FIG. This load circuit is connected between an output terminal of an amplifying transistor (described later) and a load resistor _R0 . This load circuit includes a first transmission line _{T 11,} the second transmission line _{T 12,} includes a plurality of first stub _T 2 through T _7, and a synthesis compensation stub ^{T *} as main components.
[0021]
Input terminal C of the first transmission line T ₁₁ is connected to the output terminal of the transistor. The length of the first transmission line T ₁₁ has a length of 1/4 the wavelength of the fundamental wave (lambda) at the output of the transistor.
[0022]
Input of the second transmission line T ₁₂ is connected in series with the output terminal A of the first transmission line T _11. The output side of the second transmission line T ₁₂ is connected to the load resistor R _0. The length of the second transmission line _{T 12} is the same as the first transmission line _{T 11.}
[0023]
The plurality of first stubs T _{2 to} T _n (up to T _{7 in the} figure) are connected in parallel to the output terminal A of the first transmission line T ₁₁ . Here, n is an arbitrary positive integer. The transmission line length L of each of these first stubs T _{2 to} T _n is
L = λ / 4m (where m = 2, 3, 4,..., N)
It is said that.
[0024]
Further, in the present embodiment, the plurality of first stubs T _{2 to} T _n are not all provided continuously. That is, in this embodiment,
The first transmission line length corresponding to m ′ represented by “m ′ = pk (where p is an odd number equal to or greater than 3 and k is m in the first stub currently provided among the m). Any or all of the stubs T _{2 to} T _n are omitted. Here, “omitted” means not provided. For example, in the illustrated example, as the case of p = 3 a and k = 2, the stub T ₆ are omitted. Further, k means _k in the stub T _k actually provided as described above. Therefore, the case of providing the T _2, it is meant that omit the T _6. When provided with the T ₃ has a case of p = 3 a and k = 3, it can be omitted stub _{T 9.} The reason why the stub can be omitted will be described later.
[0025]
The combined compensation stub T ^* is connected to the output terminal A of the first transmission line. The admittance of the combined compensation stub T ^* is equal in magnitude to the combined input admittance of the plurality of first stubs T _{2 to} T _n (excluding the omitted stubs) and has an opposite sign. In the illustrated example, such a combined compensation stub T ^* is constituted by a stub having an open end. Further, the combined compensation stub T ^* can be configured by a short-circuited stub. Further, instead of the combined compensation stub T ^* , a reactance element having an admittance having the same magnitude and the opposite sign as the combined input admittance of the first stubs T _{2 to} T _n (excluding the omitted stub) is used. May be. Examples of such reactance elements include a lumped constant inductor L, a lumped constant capacitor C, and a stub loaded with the inductor L or the capacitor C at the tip. In FIG. 3, the symbol Z _L indicates the combined impedance of this load circuit.
[0026]
Next, an example of an amplifier circuit using the load circuit of the present embodiment will be described with reference to FIG. In this example, the input terminal C of the first transmission line T ₁₁ is connected to the output terminal of the amplifying transistor S. Further, coupling capacitors C ₁ and C ₂ for blocking DC are connected between the amplifying transistor S and the load resistor R ₀ . Further, the power supply voltage V _dd is supplied to the transistor S.
[0027]
Next, the operation of the load circuit according to the present embodiment will be described.
First, by providing the first transmission line T _11, the input impedance becomes zero with respect to the fundamental wave f _0. Furthermore, the impedance of the point A in each harmonic can be made zero by the first stub T _m (m = 2, 3, 4,..., N) for each m-th harmonic. These operations are the same as those of the conventional load circuit shown in Document 1.
[0028]
Furthermore, in this embodiment, one or more stubs are omitted from the first stubs T _{2 to} T _n . The operation will be described below. First, the entire first stub (hereinafter referred to as “T _k ”) is considered as a two-terminal pair circuit (four-terminal circuit) as shown in FIG. Then, the F matrix of the first stub T _k has f _k = kf ₀ as the frequency of the k-order harmonic for all frequencies f.
[Expression 1]

It is represented by Equation (1) is expressed as follows when f = f _k , 3f _k , 5f _k , 7f _k ... = Kf ₀ , 3kf ₀ , 5kf ₀ ,.

However, when f = f ₀ , 5f ₀ , 9f ₀ ,.
When f = 3f ₀ , 7f ₀ , 11f ₀ ,.
Therefore, the input impedance _{Zink at} this time is
[Equation 3]

It becomes. Furthermore, since T _k is open at the tip, Z _{2 ink} becomes 0 by I ₂ = 0.
[0029]
From this, it can be seen that by providing the first stub T _k , the impedance at point A in each of the 3k, 5k, 7k,... Harmonics other than the kth harmonic becomes zero. . Conventionally, one first stub corresponding to each harmonic is provided one by one. That is, a stub of T _{2 for} the second harmonic and T ₃ for the third harmonic is provided. However, as is clear from the above consideration, if there is a stub T _k , it is not necessary to provide T _3k , T _5k , T _7k,. In other words, even if T _3k , T _5k , T _7k ,... _Are omitted, Tk replaces them, and the load impedance characteristics are the same as before (open to odd harmonics, short to even harmonics). ) Can be realized. Specifically, _T 6 can be replaced by _{T 2, T 10, T 14} , ···, T 9 can be replaced by _{T 3, T 15, T 21} , ···, fungible T by _{T 4 12} , T ₂₀ , T ₂₈ ,... Can be omitted. Table 1 shows stubs that can be omitted when _Tk is provided.
[0030]
[Table 1]

[0031]
In summary, the harmonic processing stub that can be omitted is “a stub T _m corresponding to a harmonic that is an odd multiple of m when the value of m in an existing stub is an integer greater than or equal to 2”. It can be said. In other words, stubs where the value of m is a factorial of 2 and a prime number, specifically T ₂ , T ₃ , T ₄ , T ₅ , T ₇ ,. Remains. And only with them, a desired load impedance characteristic is obtained. Of course, up to which order the stub is provided is an arbitrary design matter. Moreover, it is not essential to omit all stubs that can be omitted, and it is theoretically possible to leave a part of them.
[0032]
Thus, in the present embodiment, the number of first stubs can be reduced as compared to the conventional case. Therefore, the area required for stub installation can be reduced, and the stub mounting process is facilitated.
[0033]
FIG. 6B shows the load impedance characteristics of the load circuit according to the present embodiment. For comparison, the load impedance when the first stub is not reduced (prior art shown in FIG. 1) is shown in FIG. Also in the circuit of the present embodiment, the load impedance is open to the odd-order harmonics and short-circuited to the even-order harmonics, as in the circuit before reduction. Moreover, the load impedance for the fundamental wave (1.9 GHz) is equal. Thereby, it turns out that the circuit of this embodiment has the same load impedance as the circuit before reduction.
[0034]
Next, the reason why the combined compensation stub T ^* can be used will be described. _Let Y _inT be the combined input admittance of the first stubs T _{2 to} T _n described above (in which some stubs are reduced according to the above). The stub T ^* has an input admittance that is equal in magnitude and opposite to the admittance Y _inT . Therefore, the influence of the first stubs T _{2 to} T _n on the fundamental wave (the influence of residual reactance) can be removed by this single stub T ^* . Conventionally, one compensation stub is provided for each first stub. However, in the present embodiment, the number of compensation stubs can be reduced for the reasons described above. Therefore, in this embodiment, the area required for stub installation can be further reduced. In this embodiment, the stub mounting process can be further facilitated.
[0035]
A method for obtaining the combined compensation stub T ^* will be described more specifically. The input admittance Y of a transmission line (length l, propagation constant β, characteristic impedance Z ₀ ) with an open end is
[Expression 4]

It is represented by From this, the input admittance Y _ink for the fundamental wave in the stub T _k is as follows. That is, first, the fundamental wave propagation constant β is β = β ₀ = 2π / λ ₀ . Furthermore, since the stub T _k is a quarter wavelength line with respect to the _k -order harmonic (wavelength λ _k = λ ₀ / k), its length l is 1 = λ _k / 4 = λ ₀ / 4k. Become. Substituting these into equation (4) gives
[Equation 5]

It becomes.
[0036]
On the other hand, if the combined input admittance of the entire first stubs T _{2 to} T ₇ is Y _inT ,
[Formula 6]

It becomes. Therefore, by setting the input impedance Y _inh of the combined compensation stub T ^* (length L _h ) to Y _inh = −Y _inT , the influence of the first stub on the fundamental wave is removed by a single combined compensation stub. be able to.
[0037]
Next, an example in which the composite compensation stub T ^* is configured by a transmission line having an open end will be described. From the equations (4) and (6),
[Expression 7]

It is. Then, the length L _h is
[Equation 8]

It becomes. When this is actually calculated,
Lh = 0.039959253λ ₀ ≈0.3λ ₀
Can be obtained as follows.
[0038]
In this embodiment, between the output terminal and the load resistance R ₀ of the first transmission line T11, connect the second transmission line T ₁₂ having a length of 1/4 the wavelength of the fundamental wave (lambda) is doing. Therefore, in this embodiment, the proper load impedance for the amplifier operating in the fundamental wave, there is an advantage that can be realized by changing the characteristic impedance of the transmission line T _12. Moreover, in this case, change in the characteristic impedance of the transmission line T ₁₂ is the load impedance for the harmonic is also an advantage that no influence at all.
[0039]
【Example】
The load circuit of the present embodiment was applied to the amplifying transistor S under the following conditions.
Saturated drain current: 60 mA
Threshold voltage: -0.9V
Power supply voltage: 3.4V
Maximum oscillation frequency f _max : 70 GHz
Configuration: Heterojunction FET
[0040]
In this case, the voltage / current characteristics at the drain current terminal were calculated using a harmonic balance simulator. The result is shown in FIG. The overlap between the instantaneous voltage and the instantaneous current is almost eliminated, and an operation close to an ideal class F operation is realized. FIG. 8 shows the added power efficiency (PAE) at this time. From this figure, it can be seen that PAE reaches almost 90%. In this figure, P _out indicates the output power obtained at the load resistance.
[0041]
Next, a load circuit according to a second embodiment of the present invention will be described. In the first embodiment described above, the combined compensation stub T ^* is used as the compensation stub. However, in the second embodiment, instead of this, a plurality of compensation second stubs are provided. An example of the circuit is shown in FIG. Here, second stubs T ₂ ^{* to} T ₇ ^* for compensation are provided corresponding to the first stubs T _{2 to} T ₇ . Of course, the second stub corresponding to the omitted first stub is omitted. Also in this configuration, the influence on the fundamental wave due to the residual reactance can be removed as in the above-described embodiment. Since the operation in this case is as described in the above-mentioned document 1, detailed description is omitted. Also in this embodiment, since the first stub T ₆ and the second stub T ₆ ^* are omitted, the number of stubs can be reduced accordingly. In the second embodiment, each transmission line length L _h of the second stub is further set to
L _h = (2m−1) λ / 4m (where m = 2, 3, 4,..., N)
It was assumed that the relationship was satisfied. With this setting, the transmission line length L _h + L is always λ / 2, which has the advantage that the impedance compensation design is easy.
[0042]
Further, in the second embodiment, the plurality of first stubs and the plurality of second stubs are arranged at positions that are line-symmetric with each other. By arranging in this way, a large number of stubs can be connected in parallel with one point (in this example, the output terminal A) as a reference. For this reason, there exists an advantage that the area required for stub arrangement | positioning can be made small.
[0043]
Note that the description of each of the embodiments is merely an example, and does not indicate a configuration essential to the present invention. The configuration of each part is not limited to the above as long as the gist of the present invention can be achieved. For example, in the above embodiment, a transistor is used as the amplifying element, but a two-terminal amplifying element having a negative resistance may be used instead. An example of such a device is a Gunn diode.
[0044]
【The invention's effect】
According to the present invention, it is possible to provide a load circuit capable of reducing the number of stubs and a highly efficient amplifier circuit using the load circuit.
[Brief description of the drawings]
FIG. 1 is a diagram showing an amplifier circuit using a conventional load circuit.
FIG. 2 is an explanatory diagram showing an example in which the circuit shown in FIG. 1 is mounted on a substrate.
FIG. 3 is a diagram showing a load circuit according to the first embodiment of the present invention.
4 is a diagram showing an amplifier circuit using the load circuit shown in FIG. 3. FIG.
FIG. 5 is a diagram showing a two-terminal circuit used for explaining the first embodiment.
FIG. 6A is a graph showing the load impedance characteristic in the conventional load circuit, and FIG. 6B is a graph showing the load impedance characteristic in the load circuit of the first embodiment.
FIG. 7 is a graph showing the results of an example using the amplifier circuit according to the first embodiment of the present invention, and is a graph showing the voltage / current characteristics at the drain terminal of a transistor.
FIG. 8 is a diagram showing the results of an example using the amplifier circuit according to the first embodiment of the present invention, and is a graph showing the load power characteristics of the circuit.
FIG. 9 is a diagram showing a load circuit according to a second embodiment of the present invention.
[Explanation of symbols]
f ₀ fundamental wave frequency 2f ₀ , 3f ₀ , 4f ₀ , 5f ₀ , 6f ₀ , 7f ₀ harmonic frequency A first transmission line output terminal C first transmission line input terminal C ₁ · C ₂ coupling Capacitor S Amplifying transistor R ₀ Load resistor T ^* Composite compensation stub T ₁₁ First transmission line T ₁₂ Second transmission line T _{2 to} T _n First stub T ₂ ^{* to} T _n ^* Second stub (compensation stub)

Claims (8)

A circuit connected between an output terminal of an amplifying transistor and a load resistor for processing harmonics appearing at the output terminal of the transistor, wherein the output of the amplifying transistor is input, and the amplification And a plurality of first stubs connected in parallel to the output terminal of the first transmission line. And
The plurality of first stubs are:
L = λ / 4m (where m = 2, 3, 4,..., N)
Each having a transmission line length L represented by
And,
m ′ = pk (where p is an odd number greater than or equal to 3, and k is m in the first stub currently provided among the m)
The installation of any or all of the first stubs having a transmission line length corresponding to m ′ represented by
Further, a composite compensation stub is provided, and the composite compensation stub is connected to an output terminal of the first transmission line. A harmonic processing circuit having equal and opposite signs.   The harmonic processing circuit according to claim 1, wherein the combined compensation stub is open at the tip.   The harmonic processing circuit according to claim 1, wherein the composite compensation stub is a short-circuited tip. A second transmission line connected between the output terminal of the first transmission line and the load resistor and having a length of ¼ of the wavelength (λ) of the fundamental wave; The harmonic processing circuit according to any one of claims 1 to 3 . Wherein instead of amplifying transistor, the harmonic processing circuit of any one of claims 1-4, characterized in that the negative resistance two-terminal amplification element is used. A circuit for processing harmonics appearing at the output terminal of the transistor, connected between the output terminal of the transistor for amplification and a load resistor, and an input terminal to which the output of the transistor for amplification is input; A first transmission line having a length of ¼ of the fundamental wavelength (λ) at the output of the amplifying transistor, and a plurality of first stubs connected in parallel to the output terminal of the first transmission line; And
The plurality of first stubs are:
L = λ / 4m (where m = 2, 3, 4,..., N)
Each having a transmission line length L represented by:
Further, a composite compensation stub is provided, and the composite compensation stub is connected to an output terminal of the first transmission line, and an admittance of the composite compensation stub with respect to a fundamental wave is equal to a composite input admittance of the first stub. A harmonic processing circuit having equal and opposite signs. Instead of the composite compensation stub, a reactance element connected to the output terminal of the first transmission line and having the same magnitude and the opposite sign as the composite input admittance of the first stub is provided. The harmonic processing circuit according to claim 1 . Amplifier circuit having an input terminal of said first transmission line in the harmonic processing circuit according to any one of claims 1 to 7, characterized in that it is connected to an output terminal of the amplifying transistor.

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