US20100182073A1 - Semiconductor Component with Annularly-Closed Contacting - Google Patents

Semiconductor Component with Annularly-Closed Contacting Download PDF

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Publication number
US20100182073A1
US20100182073A1 US12/664,328 US66432808A US2010182073A1 US 20100182073 A1 US20100182073 A1 US 20100182073A1 US 66432808 A US66432808 A US 66432808A US 2010182073 A1 US2010182073 A1 US 2010182073A1
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United States
Prior art keywords
electrodes
semiconductor component
component according
disposed
electrode
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Abandoned
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US12/664,328
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English (en)
Inventor
Ingo Daumiller
Ertugrul Soenmez
Mike Kunze
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Microgan GmbH
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Microgan GmbH
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Assigned to MICROGAN GMBH reassignment MICROGAN GMBH ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DAUMILLER, INGO, KUNZE, MIKE, SOENMEZ, ERTUGRUL
Publication of US20100182073A1 publication Critical patent/US20100182073A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/482—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes for individual devices provided for in groups H10D8/00 - H10D48/00, e.g. for power transistors
    • H10W20/484—Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes

Definitions

  • the invention relates to a semiconductor component by means of which large currents can be conducted with low resistance in the case of a small surface.
  • the invention relates in addition to a method for producing a semiconductor component, a semiconductor component according to the invention preferably being produced.
  • FIG. 1 shows a semiconductor component according to the state of the art.
  • Two electrodes 1 and 2 are hereby disposed on a substrate 4 . If a voltage 3 is applied between the electrodes 1 and 2 , then a current 5 flows through the substrate 4 . The current 5 hereby flows laterally from the electrode 2 to the electrode 1 parallel to the substrate surface.
  • the substrate 4 here is a conductive layer or a semiconductor.
  • the electrodes 1 and 2 are divided over their entire width into a plurality of narrower individual components ( 1 a , 1 b , 1 c , 2 a , 2 b ) which are then connected in parallel via a so-called bus ( 6 , 7 ). Such an arrangement is shown in FIG. 2 .
  • individual components 1 a , 1 b , 1 c extend hereby from a bus 6 perpendicularly to a longitudinal direction of the bus and engage one in the other with individual components 2 a and 2 b of the electrode 2 which extend from the bus 7 perpendicularly to the longitudinal direction thereof.
  • the undesired series resistance and also the maximum current carrying capacity of the electrodes 1 and 2 can be adjusted.
  • current which is fed into the corresponding electrode via the point 8 or 9 furthest away from the associated bus 6 or 7 , experiences the greatest series resistance.
  • the buses 6 and 7 guide the current which flows through the individual components 2 a , 2 b or 1 a , 1 b , 1 c together.
  • the current carrying capacity of the buses 6 and 7 must respectively be so great that it corresponds to the sum of the current carrying capacities of the individual components 1 a , 1 b , 1 c or 2 a , 2 b .
  • the current carrying capacity of the buses 6 and 7 can be increased for example by increasing the width of the buses.
  • the buses 6 and 7 therewith increase the surface area of the total component without this surface area contributing to the supply of current.
  • the additional spatial requirement hereby increases therefore with the current strength and the number of individual components to be supplied by the bus.
  • the dotted regions 10 a , 10 b in FIG. 2 represent the surface area used for active structures.
  • the component can be connected via bonding wires at bonding spots 11 and 12 .
  • the bonding spots 11 and 12 must also be designed in the size thereof such that their current carrying capacity corresponds to the current carrying capacity of the buses 6 or 7 contacted by them. In the case of the bonding spot 12 , the current carrying capacity thereof must therefore correspond to the sum of the current carrying capacities of the buses 6 and 6 a .
  • increasing the bonding spots likewise increases the spatial requirement on the semiconductor disc, which is associated with increased costs. In turn, the spatial requirement increases in addition with the current which is intended to be conductable through the component to be connected.
  • a further problem in the arrangement shown in FIG. 2 is that, when the voltage applied between two electrodes 1 a , 1 b , 1 c and 2 a , 2 b in the semiconductor exceeds its critical electrical field strength, an electrical breakdown takes place which leads to destruction of the component. Such a breakdown begins in the component at that place at which the highest field excessive rise in the electrical field is present. In the shown arrangement, this is the case respectively at the ends of the component strips 1 a , 1 b , 1 c , 2 a , 2 b . The corresponding points, in the shown arrangement, are therefore particularly susceptible to destruction by an electrical breakdown.
  • a semiconductor component according to the invention has a substrate on which at least one oblong first electrode and at least one, preferably oblong, second electrode are disposed. Further correspondingly disposed electrodes with further polarities are possible.
  • the substrate is preferably a conductive layer or a semiconductor layer.
  • At least one, preferably all of the electrodes have an oblong form. This means that they extend along a line and, in one or two directions perpendicular to this line, have an essentially constant or only slightly varying extension over the length of the line.
  • the electrodes are now closed in the longitudinal direction thereof, this means that the mentioned line, along which the electrodes extend, is a closed line for each electrode. Closed hereby means that the line or the electrodes merge into each other along their longitudinal direction, i.e. have no beginning and no end. The electrodes are therefore configured such that their surfaces surround a free region not covered by the corresponding electrode.
  • the electrodes can be closed respectively in the mentioned manner annularly, circularly, elliptically, rectangularly, squarely, triangularly, polygonally or in another manner.
  • the electrode then hereby extends along the edges of the corresponding shape.
  • the electrodes are preferably disposed in their longitudinal direction parallel to the substrate and parallel to each other.
  • a voltage can preferably be applied between the electrodes such that the at least one first electrode has a first polarity or pole and the at least second electrode has a second polarity or pole and/or such that the electrodes have at least two different functions in the semiconductor component.
  • Parallelism implies here that the shortest spacing of the objects parallel to each other is constant and/or is the same on the total extension or length.
  • polarity or pole preferably the sign of the potential on the corresponding electrode or also the relative potential of the electrodes to each other. Two electrodes, the potential of which has the same sign but different values, have therefore different polarities in this sense.
  • function is used here analogously.
  • the function of the corresponding electrode in the component is a transistor, then the functions of the electrodes can be for example drain, source and gate or emitter, collector and base.
  • the polarity or function for example for the one electrode can be the positive pole and, for the other, the negative pole. The same applies for other components.
  • the electrodes can be configured inter alia to form a semiconductor which is non-blocking as ohmic contact or blocking as Schottky contact.
  • the electrodes are disposed in a common plane. It is also preferred if the substrate is essentially extended in a planar manner, preferably in one plane. This means that two surfaces of the substrate situated one opposite the other are significantly larger than the other surfaces of the substrate. The electrodes then extend preferably in one or more planes which are situated parallel to those planes in which the substrate extends in a planar manner.
  • the electrodes are disposed concentrically about common points, such as for example a common centre.
  • the closed arrangement of the electrodes according to the invention it is possible due to the closed arrangement of the electrodes according to the invention to contact these at any point and thereby to half the undesired series resistance within the electrode relative to an unclosed arrangement.
  • the resistance is halved in that, from each point of the electrode to a contacting externally, for example via a bus, there are two paths along the electrode which are connected to each other in parallel. The conductances of the two paths are added therefore to form a common conductance which is greater than the conductance of the individual paths.
  • the conductance hereby is the inverse resistance.
  • first electrodes are now connected by a common bus and/or several or all of the second electrodes are connected by a common bus.
  • Possible further electrodes with further polarities can be connected analogously by further buses.
  • At least one of the buses is disposed in a plane which is parallel to that plane in which the substrate is extended in a planar manner and in which neither the substrate nor the electrodes are disposed.
  • at least one of the buses preferably all of the buses, is disposed on a side of the electrode orientated away from the substrate.
  • the electrodes can therefore be disposed on the substrate in a common plane and then, above the electrodes, the bus or buses.
  • the bus or buses are not disposed directly on the electrodes but at a spacing from the latter.
  • At least one insulating layer is hereby disposed preferably between the buses and the electrodes. It is then preferred if at least one via contact is disposed between at least one of the buses and the electrodes connected by the corresponding bus, via which via contact the electrodes are connected electrically to the bus contacting them. The via contact therefore extends across the spacing between the electrodes and the buses.
  • the via contacts can extend in particular through holes in the insulating layer. Such holes or openings can be filled for this purpose with a conductive material, such as e.g. metal.
  • the insulating layer can have or comprise a dielectric and/or polymers.
  • the via contacts can be configured in the most varied of ways. They can be oblong and they can have inter alia a cuboid or cylindrical shape.
  • the structure of the insulating layers and via contacts can also be more complicated.
  • An insulating layer can firstly be applied for example on the electrodes, said layer having openings above the electrodes.
  • One or more metal layers can be applied on this insulating layer which extends also into the openings and contacts the electrodes through them.
  • a separate metal layer or a separate region of the metal layer can be provided here for each polarity.
  • At least one further insulating layer and also at least one further metal layer which has separate regions for different polarities can be applied correspondingly on the metal layers at least in regions, corresponding to what was described above for the other layers.
  • the buses can be disposed in different planes or in a common plane. Since the electrodes are extended longitudinally, it is possible to dispose a plurality of buses such that all the electrodes extend in portions below each bus, the via contacts however being disposed only between a given bus and the electrodes contacted by said bus. The other electrodes extend without electrical contact to this bus along between the substrate and the bus. Preferably, at least one insulating layer is disposed between the electrodes and those buses which do not contact these electrodes.
  • the buses are extended in a planar manner in the plane of their arrangement. They can hereby extend in a planar manner over a part of the surface area of the substrate. It is thereby advantageous to make the surface area of the buses as large as possible. It is therefore preferred if the buses together cover the surface of the substrate in large parts, preferably essentially completely.
  • the surface area of one or more supply buses as a bonding spot which serves to connect the semiconductor component via bonding wires.
  • the contacting can be effected by means of bonding wires without additional semiconductor surface area being required for this purpose.
  • the active surface can be used doubled by the active component.
  • the supply bus therefore requires no additional semiconductor disc surface area.
  • the via contacts extend longitudinally parallel to those electrodes which are connected by them to a bus.
  • the via contacts can hereby extend along the electrodes in that region in which the electrodes extend below the buses contacting them.
  • the semiconductor component preferably has at least one transistor and/or one diode or is a transistor or a diode.
  • a transistor is preferably a field effect transistor.
  • semiconductor materials preferably those which contain or comprise at least one nitride of a main group III element. These materials are therefore inter alia GaN, AlN, InN, GaAlN, GaInN, AlInN and AlInGaN. Those can be particularly resistant to high temperatures, preferably greater than or equal to 100° C., particularly preferred greater than or equal to 300° C., particularly preferred greater than or equal to 500° C., particularly preferred greater than or equal to 700° C.
  • FIG. 1 a section through a lateral component according to the state of the art
  • FIG. 2 a semiconductor component according to the state of the art
  • FIG. 3 a semiconductor component corresponding to the present invention
  • FIG. 4 a section through a semiconductor component corresponding to the present invention
  • FIG. 5 a plan view on a semiconductor component according to the invention.
  • FIG. 3 shows a plan view on a semiconductor component according to the invention having a first electrode 1 and a second electrode 2 which are disposed on a common substrate 4 .
  • the electrodes 1 and 2 are oblong, annularly closed and disposed concentrically about a common centre.
  • the first and the second electrode are closed in their longitudinal direction.
  • the electrodes 1 and 2 extend parallel to the surface of the substrate 4 on which they are disposed in a common plane, and also at a spacing from each other and parallel to each other.
  • the electrode 1 is hereby contacted by a contact 31 at a point 33 .
  • the electrode 2 is contacted via a contact 32 at a point 34 .
  • the first electrode When applying a voltage, the first electrode then has a first polarity and the second electrode a second polarity different from the first. If now a current is fed for example into the electrode 1 at that point situated opposite the contacting point 33 relative to the centre, then this current can flow along both semicircles of the electrode to the contacting point 33 . Such a current therefore experiences half the resistance relative to a current which would flow only through a semicircle of the electrode. The same applies for the electrode 2 . The undesired series resistance is therefore halved by the closed arrangement of the electrodes 1 and 2 .
  • FIG. 4 shows a section through a semiconductor component according to the invention with a large number of electrodes 1 a , 1 b , 1 c , which have a first polarity when a voltage is applied, and also with a large number of electrodes 2 a , 2 b which have a second polarity when a voltage is applied.
  • the electrodes are disposed in one plane on a common substrate 4 . On that side orientated away from the substrate 4 , the electrodes 1 a , 1 b and 1 c are contacted by a bus 6 .
  • the electrodes 2 a and 2 b are contacted by a bus 7 which is disposed in a plane in which the electrodes 1 and 2 are not disposed.
  • This plane is parallel to the substrate 4 and to the plane of the electrodes 1 and 2 .
  • the contacts 6 and 7 are disposed here in one plane. It should be noted that the illustrated component in the plane perpendicular to the drawing plane, as shown in FIG. 5 , is annularly closed so that also the parts of the electrodes 1 a and 1 b disposed below the bus 7 are contacted by the bus 6 .
  • the buses 6 and 7 are not disposed directly on the electrodes 1 a , 1 b , 1 c and 2 a , 2 b . Rather an insulating layer 43 is disposed between the electrodes and the buses 6 and 7 .
  • the electrical connection between the electrodes 2 a and 2 b to the bus 7 is hereby achieved by the via contacts 42 a or 42 b penetrating the insulating layer 43 .
  • the electrodes 1 a , 1 b and 1 c are contacted with the bus 6 through via contacts 41 a , 41 b or 41 c .
  • the via contacts 41 a , 41 b , 41 c and 42 a , 42 b can hereby have an oblong configuration in the direction perpendicular to the drawing plane.
  • the insulating material 43 is disposed respectively between the electrodes 1 a , 1 b , 1 c and the adjacent electrodes 2 a , 2 b . Furthermore, the insulating material 43 is disposed between the plane of the electrodes 1 , 2 and the buses 6 , 7 which is penetrated however by the via contacts 41 a , 41 b , 41 c , 42 a , 42 b.
  • FIG. 5 shows a plan view on a semiconductor component, as is shown in FIG. 4 .
  • the electrodes 1 a , 1 b and 1 c and also 2 a , 2 b are hereby disposed annularly-closed concentrically.
  • the buses 6 and 7 are configured as essentially semicircular surfaces with an extension parallel to the substrate, which completely cover the semicircular surface of the substrate 4 covered by the electrodes apart from a narrow gap for insulating.
  • the planar buses 6 and 7 here serve in addition as bonding spots for contacting the semiconductor component by means of bonding wires.
  • the electrodes 1 a , 1 b , 1 c are hereby connected to the bus 6 via oblong via contacts 41 a , 41 b , 41 c which extend parallel to the electrodes.
  • the electrodes 2 a , 2 b are connected to the bus 7 via oblong via contacts 42 a , 42 b which extend parallel to the electrodes.
  • Respectively one bonding spot 11 or 12 can be disposed on or at the buses 6 and 7 .
  • the substrate 4 , the electrodes 1 and 2 and/or the via contacts 41 a , 41 b , 41 c , 42 a , 42 b can have or comprise nitride of a main group III element.

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
US12/664,328 2007-06-18 2008-06-16 Semiconductor Component with Annularly-Closed Contacting Abandoned US20100182073A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102007028458.8 2007-06-18
DE102007028458 2007-06-18
PCT/EP2008/004839 WO2008155086A1 (de) 2007-06-18 2008-06-16 Halbleiterbauelement mit ringförmig geschlossener kontaktierung

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Publication Number Publication Date
US20100182073A1 true US20100182073A1 (en) 2010-07-22

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US12/664,328 Abandoned US20100182073A1 (en) 2007-06-18 2008-06-16 Semiconductor Component with Annularly-Closed Contacting
US12/664,318 Active 2028-12-15 US8748944B2 (en) 2007-06-18 2008-06-16 Electric circuit with vertical contacts

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US12/664,318 Active 2028-12-15 US8748944B2 (en) 2007-06-18 2008-06-16 Electric circuit with vertical contacts

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US (2) US20100182073A1 (enExample)
EP (2) EP2165363B1 (enExample)
JP (2) JP2010530619A (enExample)
WO (2) WO2008155085A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9281417B1 (en) 2015-02-20 2016-03-08 Vishay General Semiconductor Llc GaN-based schottky diode having large bond pads and reduced contact resistance
US9377759B2 (en) 2010-09-08 2016-06-28 Dai Nippon Printing Co., Ltd. Illumination device, projection apparatus and projection-type image display apparatus

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130013189A (ko) 2011-07-27 2013-02-06 삼성전자주식회사 파워 반도체 소자

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4058822A (en) * 1975-05-30 1977-11-15 Sharp Kabushiki Kaisha High voltage, low on-resistance diffusion-self-alignment metal oxide semiconductor device and manufacture thereof
US5633525A (en) * 1994-11-11 1997-05-27 Fuji Electric Co., Ltd. Lateral field effect transistor
US20020135019A1 (en) * 2001-03-22 2002-09-26 Matsushita Electric Industrial Co., Ltd. High breakdown voltage semiconductor device
US6525383B1 (en) * 1997-02-14 2003-02-25 Siemens Aktiengesellschaft Power MOSFET
US20050140896A1 (en) * 2003-12-29 2005-06-30 Lg.Philips Lcd Co., Ltd. In-plane switching mode liquid crystal display device and method of fabricating the same
US20060043501A1 (en) * 2004-09-02 2006-03-02 Kabushiki Kaisha Toshiba Nitride semiconductor device
US20070278614A1 (en) * 2006-06-05 2007-12-06 Collins David S Lateral passive device having dual annular electrodes

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4290077A (en) * 1979-05-30 1981-09-15 Xerox Corporation High voltage MOSFET with inter-device isolation structure
JPS5934666A (ja) * 1982-08-20 1984-02-25 Matsushita Electronics Corp 半導体集積回路装置
US4977108A (en) * 1987-12-02 1990-12-11 Advanced Micro Devices, Inc. Method of making self-aligned, planarized contacts for semiconductor devices
US5283558A (en) * 1989-10-16 1994-02-01 Chan James K Low-cost devices for touch control
CA2046554A1 (en) 1990-07-10 1992-01-11 Masahiro Kugishima Basic cell and arrangement structure thereof
JP3074003B2 (ja) * 1990-08-21 2000-08-07 株式会社日立製作所 半導体集積回路装置
JPH065842A (ja) * 1992-06-16 1994-01-14 Fujitsu Ltd 半導体装置
JPH06209015A (ja) * 1992-10-26 1994-07-26 Kobe Steel Ltd ダイヤモンド接合型電界効果トランジスタ及びその製造方法
US6150722A (en) * 1994-11-02 2000-11-21 Texas Instruments Incorporated Ldmos transistor with thick copper interconnect
US5468984A (en) * 1994-11-02 1995-11-21 Texas Instruments Incorporated ESD protection structure using LDMOS diodes with thick copper interconnect
JPH10125782A (ja) * 1996-10-15 1998-05-15 Sony Corp 半導体装置の製造方法
US6140687A (en) * 1996-11-28 2000-10-31 Matsushita Electric Industrial Co., Ltd. High frequency ring gate MOSFET
JP3377727B2 (ja) * 1997-08-20 2003-02-17 沖電気工業株式会社 半導体デバイスのコンタクト電極形成方法およびフォトトランジスタのコンタクト電極形成方法
DE19746620A1 (de) * 1997-10-22 1999-05-06 Siemens Ag Halbleiterdiode
EP0923126A1 (en) * 1997-12-05 1999-06-16 STMicroelectronics S.r.l. Integrated electronic device comprising a mechanical stress protection structure
US6265779B1 (en) * 1998-08-11 2001-07-24 International Business Machines Corporation Method and material for integration of fuorine-containing low-k dielectrics
US6078100A (en) * 1999-01-13 2000-06-20 Micron Technology, Inc. Utilization of die repattern layers for die internal connections
JP2000286254A (ja) * 1999-03-31 2000-10-13 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6624484B2 (en) * 2001-07-31 2003-09-23 Nokia Corporation IGFET and tuning circuit
US7932603B2 (en) * 2001-12-13 2011-04-26 Megica Corporation Chip structure and process for forming the same
US6673698B1 (en) * 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
US6972464B2 (en) * 2002-10-08 2005-12-06 Great Wall Semiconductor Corporation Power MOSFET
JP4175877B2 (ja) * 2002-11-29 2008-11-05 株式会社半導体エネルギー研究所 半導体装置及びその作製方法
US7067865B2 (en) * 2003-06-06 2006-06-27 Macronix International Co., Ltd. High density chalcogenide memory cells
JP4155888B2 (ja) * 2003-07-09 2008-09-24 シャープ株式会社 環状型ゲート電極を備えたトランジスタ
JP2005109145A (ja) * 2003-09-30 2005-04-21 Toshiba Corp 半導体装置
US7183653B2 (en) * 2003-12-17 2007-02-27 Intel Corporation Via including multiple electrical paths
US7550781B2 (en) * 2004-02-12 2009-06-23 International Rectifier Corporation Integrated III-nitride power devices
JP5116251B2 (ja) * 2005-05-20 2013-01-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7582556B2 (en) * 2005-06-24 2009-09-01 Megica Corporation Circuitry component and method for forming the same
TWI339419B (en) * 2005-12-05 2011-03-21 Megica Corp Semiconductor chip
JP2007180143A (ja) * 2005-12-27 2007-07-12 Toshiba Corp 窒化物半導体素子
US7453151B2 (en) * 2006-07-27 2008-11-18 International Business Machines Corporation Methods for lateral current carrying capability improvement in semiconductor devices
US7662722B2 (en) * 2007-01-24 2010-02-16 International Business Machines Corporation Air gap under on-chip passive device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4058822A (en) * 1975-05-30 1977-11-15 Sharp Kabushiki Kaisha High voltage, low on-resistance diffusion-self-alignment metal oxide semiconductor device and manufacture thereof
US5633525A (en) * 1994-11-11 1997-05-27 Fuji Electric Co., Ltd. Lateral field effect transistor
US6525383B1 (en) * 1997-02-14 2003-02-25 Siemens Aktiengesellschaft Power MOSFET
US20020135019A1 (en) * 2001-03-22 2002-09-26 Matsushita Electric Industrial Co., Ltd. High breakdown voltage semiconductor device
US20050140896A1 (en) * 2003-12-29 2005-06-30 Lg.Philips Lcd Co., Ltd. In-plane switching mode liquid crystal display device and method of fabricating the same
US20060043501A1 (en) * 2004-09-02 2006-03-02 Kabushiki Kaisha Toshiba Nitride semiconductor device
US20070278614A1 (en) * 2006-06-05 2007-12-06 Collins David S Lateral passive device having dual annular electrodes

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9377759B2 (en) 2010-09-08 2016-06-28 Dai Nippon Printing Co., Ltd. Illumination device, projection apparatus and projection-type image display apparatus
US10146183B2 (en) 2010-09-08 2018-12-04 Dai Nippon Printing Co., Ltd. Illumination device, projection apparatus and projection-type image display apparatus
US10948878B2 (en) 2010-09-08 2021-03-16 Dai Nippon Printing Co., Ltd. Illumination device, projection apparatus and projection-type image display apparatus
US9281417B1 (en) 2015-02-20 2016-03-08 Vishay General Semiconductor Llc GaN-based schottky diode having large bond pads and reduced contact resistance

Also Published As

Publication number Publication date
JP2010530620A (ja) 2010-09-09
WO2008155085A8 (de) 2009-07-30
US20100230727A1 (en) 2010-09-16
EP2162912B1 (de) 2019-12-04
WO2008155086A1 (de) 2008-12-24
JP5586025B2 (ja) 2014-09-10
EP2165363A1 (de) 2010-03-24
JP2010530619A (ja) 2010-09-09
WO2008155085A1 (de) 2008-12-24
EP2162912A1 (de) 2010-03-17
EP2165363B1 (de) 2020-07-29
US8748944B2 (en) 2014-06-10

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