US20090154253A1 - semiconductor device - Google Patents
semiconductor device Download PDFInfo
- Publication number
- US20090154253A1 US20090154253A1 US12/270,346 US27034608A US2009154253A1 US 20090154253 A1 US20090154253 A1 US 20090154253A1 US 27034608 A US27034608 A US 27034608A US 2009154253 A1 US2009154253 A1 US 2009154253A1
- Authority
- US
- United States
- Prior art keywords
- well
- type semiconductor
- misfets
- data
- erasing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/02—Structural aspects of erasable programmable read-only memories
- G11C2216/10—Floating gate memory cells with a single polysilicon layer
Definitions
- the present invention relates to a semiconductor device and manufacturing technology thereof, in particular, to a technology effective when applied to a semiconductor device having a non-volatile memory such as electric erasable programmable read only memory (which will hereinafter be called “flash memory”, simply).
- flash memory electric erasable programmable read only memory
- Patent Document 1 discloses an EEPROM device fabricated on a single conductive layer formed on a semiconductor substrate, while being insulated via an insulation layer; wherein the EEPROM device is a single level poly EEPROM device whose area per bit can be reduced.
- Patent Document 2 discloses a technology capable of improving a long-term data holding performance in a nonvolatile memory device formed by a single layer poly-flash technology.
- Patent Document 1 Japanese Unexamined Patent Publication No. 2001-185633
- Patent Document 2 Japanese Unexamined Patent Publication No. 2001-257324
- the present inventors have investigated a technology of forming a nonvolatile memory by only the manufacturing steps of a complementary MISFET without adding another step thereto. During the investigation, they have found the problems as described below.
- An object of the present invention is to provide a nonvolatile memory showing less element deterioration and good data retaining properties.
- Another object of the present invention is to provide a technology capable of downsizing the module having a nonvolatile memory mounted therein.
- a semiconductor device equipped with a nonvolatile memory cell, which comprises:
- a first conductivity type semiconductor isolation layer formed over a main surface of a semiconductor substrate
- a first conductivity type third well formed in the semiconductor isolation layer and separating the first well and the second well;
- a first gate electrode extending over the first well and the second well via a first gate insulating film
- a data writing MISFET and a data reading MISFET each formed in the first well and using the first gate electrode as a gate electrode
- the present invention makes it possible to manufacture a nonvolatile memory showing less element deterioration and good data retaining properties.
- the present invention also makes it possible to downsize a module having a nonvolatile memory mounted therein.
- FIG. 1 is a fragmentary plan view illustrating a manufacturing method of a semiconductor device according to Embodiment 1 of the present invention
- FIG. 2 is a fragmentary cross-sectional view illustrating a manufacturing method of the semiconductor device according to Embodiment 1 of the present invention
- FIG. 3 is a fragmentary plan view of the semiconductor device during its manufacturing step following that of FIG. 1 ;
- FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during its manufacturing step following that of FIG. 2 ;
- FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during its manufacturing step following that of FIG. 4 ;
- FIG. 6 is a fragmentary plan view of the semiconductor device during its manufacturing step following that of FIG. 3 ;
- FIG. 7 is a fragmentary cross-sectional view of the semiconductor device during its manufacturing step following that of FIG. 4 ;
- FIG. 8 is a fragmentary cross-sectional view illustrating an enlarged A-A′ cross-section of FIG. 7 ;
- FIG. 9 is a fragmentary cross-sectional view illustrating an enlarged B-B′ cross-section of FIG. 7 ;
- FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during its manufacturing step following that of FIG. 7 ;
- FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during its manufacturing step following that of FIG. 12 ;
- FIG. 14 is a fragmentary plan view of the semiconductor device according to Embodiment 1 of the present invention.
- FIG. 15 is a fragmentary cross-sectional view illustrating the data writing operation of a nonvolatile memory of the semiconductor device according to Embodiment 1 of the present invention.
- FIG. 16 is a fragmentary cross-sectional view illustrating the data erasing operation of the nonvolatile memory of the semiconductor device according to Embodiment 1 of the present invention.
- FIG. 17 is a fragmentary cross-sectional view illustrating the data reading operation of the nonvolatile memory of the semiconductor device according to Embodiment 1 of the present invention.
- FIG. 18 is a fragmentary cross-sectional view illustrating the data erasing operation of a nonvolatile memory of a semiconductor device according to Embodiment 2 of the present invention.
- FIG. 19 is a fragmentary cross-sectional view illustrating the data writing operation of a nonvolatile memory of a semiconductor device according to Embodiment 3 of the present invention.
- FIG. 22 is a schematic view illustrating the timing of voltage application when erasing of data is carried out in the nonvolatile memory of the semiconductor device according to Embodiment 5 of the present invention.
- FIG. 23 is a schematic view illustrating the timing of voltage application when erasing of data is carried out in the nonvolatile memory of the semiconductor device according to Embodiment 5 of the present invention.
- FIG. 24 is a schematic view illustrating the timing of voltage application when erasing of data is carried out in the nonvolatile memory of the semiconductor device according to Embodiment 5 of the present invention.
- the semiconductor device according to Embodiment 1 has a nonvolatile memory. The manufacturing steps of the semiconductor device of Embodiment 1 will next be described with reference to FIGS. 1 to 13 .
- a portion marked with A and A′ is a cross-section taken along a line A-A′ in the corresponding plan view; a portion marked with B and B′ is a cross-section taken along a line B-B′ in the corresponding plan view, and a portion marked with C and C′ is a cross-section of a part (a region in which an n channel type MISFET (Metal Insulator Semiconductor Field Effect Transistor) is to be formed) of a peripheral circuit region.
- MISFET Metal Insulator Semiconductor Field Effect Transistor
- An X decoder circuit, Y decoder circuit, sense amplifier circuit, input/output circuit, logic circuit and the like are formed using an n channel MISFET constituting the peripheral circuit. Not only these circuits but also logic circuits such as microprocessor and CPU may be formed.
- an element isolation trench 2 is formed in an element isolation region on the main surface of a semiconductor substrate (which will hereinafter be called “substrate” simply) made of, for example, p type single crystal silicon.
- This element isolation trench 2 is formed, for example, by dry etching the main surface of the substrate 1 to form a trench, depositing an insulating film such as silicon oxide film over the substrate 1 including the inside of this trench by CVD (Chemical Vapor Deposition), and polishing and removing an unnecessary portion of the insulating film outside of the trench by chemical mechanical polishing (CMP) to leave the insulating film inside of the trench.
- CVD Chemical Vapor Deposition
- CMP chemical mechanical polishing
- the resulting substrate 1 is heat treated to diffuse these impurities into the substrate 1 , whereby p wells (first well, second well) 4 and n well (third well) 5 are formed over the main surface of the substrate 1 .
- the substrate 1 is thermally oxidized to form a gate insulating film (first gate insulating film) 6 made of, for example, silicon oxide and having a film thickness of about 13.5 nm on the surface of each of the p wells 4 and n well 5 .
- a gate insulating film 6 made of, for example, silicon oxide and having a film thickness of about 13.5 nm on the surface of each of the p wells 4 and n well 5 .
- an insulating film made of a silicon oxide film is deposited, for example, by CVD over the polycrystalline silicon film.
- an n conductivity type impurity has been implanted into the polycrystalline silicon film.
- the insulating film in the peripheral circuit region is then removed by dry etching with a photoresist film (not illustrated) patterned by photolithography.
- An insulating film made of a silicon oxide film or the like having a film thickness of about 10 nm or greater is deposited, for example, by CVD over the substrate 1 .
- the insulating film on the substrate 1 is patterned.
- the polycrystalline silicon film is patterned to form gate electrodes (first gate electrodes) 7 A, 7 B, 7 C.
- the insulating films over the gate electrodes 7 A, 7 B, 7 C serve as a cap insulating film 8 .
- Lightly doped n type semiconductor regions NMa, NMb, NMc are formed by ion implantation of P or As as an n type impurity into a part of the p wells 4 and n well 5 , while lightly doped p type semiconductor regions PMa, PMb are formed by ion implantation of boron as a p type impurity into a part of the p wells 4 .
- These lightly doped n type semiconductor regions NMa, NMb, NMc and lightly doped p type semiconductor regions PMa, PMb are regions with a lower impurity concentration than n type semiconductor regions 14 A, 14 B, 14 C and p type semiconductor regions 15 A, 15 B which will be described later.
- the silicon oxide film and cap insulating film 8 are anisotropically etched to form sidewall spacers 12 over the sidewalls of the gate electrodes 7 A, 7 B, 7 C and the cap insulating film 9 .
- the cap film 8 is removed from the peripheral circuit region, whereby the surface of the gate electrode 7 C is exposed. This is because the thickness of the cap insulating film 8 in the memory cell region is thicker than that of the cap film 8 in the peripheral circuit region and etching stops at a position where the surface of the gate electrode 7 C in the peripheral circuit region is exposed.
- P or As is ion-implanted as an n type impurity into a part of the p wells 4 and n well 5 to form n type semiconductor regions 14 A, 14 B, 14 C, while boron is ion-implanted as a p type impurity into a part of the p wells 4 to form p type semiconductor regions 15 A, 15 B.
- n type impurity As illustrated in FIGS. 6 and 7 , P or As is ion-implanted as an n type impurity into a part of the p wells 4 and n well 5 to form n type semiconductor regions 14 A, 14 B, 14 C
- boron is ion-implanted as a p type impurity into a part of the p wells 4 to form p type semiconductor regions 15 A, 15 B.
- the description on the lightly doped n type semiconductor regions NMa, NMb, NMc and lightly doped p type semiconductor regions PMa, PMb is omitted in order to simplify the description and highly doped n type semiconductor regions 14 A, 14 B, 14 C and highly doped p type semiconductor regions 15 A, 15 B which will be described later will be illustrated as typical examples.
- a nonvolatile memory element having the gate electrodes 7 A, 7 B as a floating gate and the p type semiconductor region 15 A as a control gate is formed.
- FIG. 7 An enlarged view of FIG. 7 is shown in each of FIGS. 8 to 10 .
- a region which will be a control gate of the nonvolatile memory element is a region subjected to ion implantation for forming the lightly doped p type semiconductor region PMa and highly doped p type semiconductor region 15 A.
- a feeder portion of the p wells 4 is a region subjected to ion implantation for forming the lightly doped p type semiconductor region PMa and highly doped p type semiconductor region 15 B.
- a feeder portion of the n well 5 is a region subjected to ion implantation for forming the lightly doped n type semiconductor region NMa and highly doped n type semiconductor region 14 A.
- the source and drain regions of the data writing and erasing MISFETs Qw 1 ,Qw 2 and data reading MISFETs Qr 1 ,Qr 2 are each composed of the lightly doped n type semiconductor region NMb and highly doped n type semiconductor region 14 B.
- Descriptions on feeder portions of the p well 4 and n well 5 are similar to those on the feeder portion of the p well 4 and n well 5 in FIG. 8 .
- the source and drain regions of the n channel MISFET in the peripheral circuit region are each composed of the lightly doped n type semiconductor region NMb and highly doped n type semiconductor region 14 B.
- FIGS. 8 to 10 the lightly doped n type semiconductor regions NMa, NMb, NMc are thus illustrated in detail.
- the other diagrams do not include them in order to simplify the description but include only n type semiconductor regions 14 A, 14 B, 14 C and p type semiconductor regions 15 A, 15 B.
- a silicide layer 18 is then formed.
- This silicide layer 18 is formed in the following manner. First, a Co (cobalt) film is deposited over the substrate 1 , for example, by sputtering. The substrate 1 is heat treated to cause a silicide reaction on the interface between the Co film and gate electrode 7 C in the peripheral circuit region and on the interface between the Co film and substrate 1 . The unreacted Co film is then removed by etching, whereby a silicide (CoSi 2 ) layer 18 is formed on the surfaces of the gate electrode 7 C and source and drain (n type semiconductor region 14 ). In the memory cell region, the silicide layer 18 is formed on the surface of the n type semiconductor region 14 .
- the cap insulating film 8 remains on the surfaces of the gate electrodes 7 A, 7 B, no silicide layer 18 is formed thereon.
- Co cobalt
- Ti titanium
- W tungsten
- Ni nickel
- a silicon nitride film 19 is deposited over the substrate 1 by plasma CVD so as to cover the gate electrodes 7 A, 7 B, 7 C, cap insulating film 8 and sidewall spacers 12 .
- the silicon nitride film 19 functions to prevent the contact holes from reaching the substrate even if the contact holes are formed over the element isolation trench owing to misalignment. It also functions to prevent the etching of the surface of the silicide layer 18 by overetching. In short, the silicon nitride film 19 functions as an etching stopper.
- a silicon oxide film 20 is then deposited over the substrate 1 , for example, by CVD, and the surface of the silicon oxide film 20 is planarized by chemical mechanical polishing.
- the silicon oxide film 20 and silicon nitride film 19 are dry etched, whereby contact holes reaching the n type semiconductor regions 14 A, 14 B, 14 C and p type semiconductor regions 15 A, 15 B, respectively are formed.
- the silicon nitride film 19 serves as an etching stopper film when the silicon oxide film 20 is etched. Plugs 22 A to 22 E are then formed inside of the contact holes.
- the plug 22 A reaches the silicide layer 18 over the n type semiconductor region 14 A
- the plug 22 B reaches the silicide layer 18 over the n type semiconductor region 14 B
- the plug 22 C reaches the silicide layer 18 over the n type semiconductor region 14 C
- the plug 22 D reaches the silicide layer 18 over the p type semiconductor region 15 A
- the plug 22 E reaches the silicide layer 18 over the p type semiconductor region 15 B.
- the plugs 22 A to 22 E are formed, for example, by depositing a Ti (titanium) film and TiN (titanium nitride) film over the silicon oxide film 20 including the inside of the contact holes by sputtering, depositing a TiN film and, as a metal film, a W (tungsten) film by CVD and then, removing the W film, TiN film and Ti film outside the contact holes by chemical mechanical polishing.
- a nonvolatile memory can be formed by the manufacturing steps of a complementary MISFET without adding thereto another step.
- a plurality of interconnects 23 are formed over the silicon oxide film 20 and plugs 22 A to 22 E.
- the interconnects 23 are formed, for example, by depositing a Ti film, Al (aluminum) alloy film and TiN film successively over the silicon oxide film 20 by sputtering, and patterning these Ti film, Al alloy film and TiN film by dry etching with a photoresist film as a mask.
- the number of interconnect layers to be stacked may be increased further by repeating steps similar to those employed for the formation of the silicon oxide film 20 and interconnects 23 .
- FIG. 14 is a fragmentary plan view of the memory cell region and FIGS. 15 to 17 are cross-sections taken along a line D-D′ in FIG. 14 .
- the interconnects 23 are not illustrated in order to facilitate the understanding of the description.
- writing of data is carried out by applying 9V to the n well 5 (n type semiconductor isolation region 3 ), 0V to the p type semiconductor regions 15 B (the p wells 4 having the MISFETs Qw 1 , Qw 2 , Qr 1 , Qr 2 formed thereover), 9V (first voltage), that is, a forward voltage, to the p type semiconductor regions 15 A (the p wells 4 having the capacitive elements C 1 ,C 2 formed thereover), 7V (second voltage) to one of the source and drain (n type semiconductor regions 14 B) of the data writing and erasing MISFETs Qw 1 ,Qw 2 , and 0V to the other one, and setting the source and drain (n type semiconductor regions 14 B) of the data reading MISFETs Qr 1 ,Qr 2 at open potential.
- channel hot electrons e ⁇
- Erasing of data is carried out, as illustrated in FIG. 16 , by applying 9V to the n well 5 (the n type semiconductor isolation region 3 ), 9V to the p type semiconductor regions 15 B (the p wells 4 having the MISFETs Qw 1 , Qw 2 , Qr 1 , Qr 2 formed thereover), and ⁇ 9V, that is, a reverse voltage, to the p type semiconductor regions 15 A (the p wells 4 having the capacitive elements C 1 ,C 2 formed thereover), and setting the source and drain (n type semiconductor regions 14 B) of the data writing and erasing MISFETs Qw 1 ,Qw 2 and data reading MISFETs Qr 1 ,Qr 2 at open potential.
- the capacitive electrodes (gate electrodes 7 A, 7 B) of the capacitive elements C 1 ,C 2 have a greater area than the capacitive electrodes (gate electrodes 7 A, 7 B) forming a gate capacitance of the MISFETs Qw 1 ,Qw 2 (refer to FIG. 14 ) so that the capacitance of the capacitive elements C 1 ,C 2 becomes greater than the gate capacitance (formed between the gate electrodes 7 A, 7 B and the channel of MISFETs Qw 1 ,Qw 2 ) of the MISFETEs Qw 1 ,Qw 2 .
- the voltage to be applied to the gate capacitance of the MISFETs Qw 1 ,Qw 2 therefore becomes greater than the voltage to be applied to the capacitive elements C 1 ,C 2 , whereby in the data writing and erasing MISFETs Qw 1 ,Qw 2 and data reading MISFETs Qr 1 ,Qr 2 , electrons (e ⁇ ) are emitted to the p well 4 from the gate electrode 7 A by FN tunneling.
- deterioration of an element which will otherwise occur owing to the concentration of an electric field at the end portion of the drain (n type semiconductor region 14 B) can be prevented. Since the deterioration of an element can be prevented, leakage of charges can also be prevented.
- Reading of data is carried out, as illustrated in FIG. 17 , by applying 3V to the n well 5 (the n type semiconductor isolation region 3 ), 0V to the p type semiconductor regions 15 B (the p wells 4 having the MISFETs Qw 1 , Qw 2 , Qr 1 , Qr 2 formed thereover), and 3V to the p type semiconductor regions 15 A (the p wells 4 having the capacitive elements C 1 ,C 2 formed thereover), setting the source and drain (n type semiconductor regions 14 B) of the data writing and erasing MISFETs Qw 1 ,Qw 2 at open potential, and applying 1V to one of the source and drain (n type semiconductor region 14 B) of the data reading MISFETs Qr 1 ,Qr 2 and 0V to the other one.
- the data reading MISFETs Qr 1 ,Qr 2 are turned ON.
- the data writing and erasing MISFETs (Qw 1 ,Qw 2 ) and data reading MISFETs (Qr 1 ,Qr 2 ) are formed, respectively.
- the nonvolatile memory as described in Embodiment 1 can be used, for example, as a fuse circuit by accumulating voltage control data (picture quality control data) in an LCD (Liquid Crystal Display) driver.
- the module can be downsized compared with that of an OTPROM type fuse circuit which requires a memory capacity corresponding to the rewriting frequency, because data rewriting can be carried out according to need.
- the downsizing of the module leads to a reduction in the manufacturing cost of the module.
- Nonvolatile memory Another use of the nonvolatile memory according to Embodiment 1 is relief of a defective memory cell of DRAM (Dynamic Random Access Memory) having a redundant configuration.
- the memory cell becomes a unit information cell and by a plurality of the gathered information cells, an electrical programming circuit for nonvolatile memory element is formed.
- the plurality of unit information cells becomes a memory circuit of a relief information for a circuit to be relieved. This makes it possible to enhance the reliability of defect relief.
- a fuse programming circuit for storing relief information in accordance with the fused state of a fuse element may be disposed as another relief information memory circuit for the above-described circuit to be relieved. It is possible to raise a relief efficiency by using a fuse programming circuit for the relief of a defect detected at the stage of a wafer, while using the above-described electrical programming circuit for the relief of a defect detected after burn-in.
- the above-described relief circuit may be a memory cell of a microcomputer with built-in DRAM or a memory cell of a microcomputer with built-in SRAM. It may constitute a relief circuit of an LCD driver.
- FIG. 18 illustrates a cross-section taken along a line D-D′ of FIG. 14 in Embodiment 1.
- the nonvolatile memory of Embodiment 2 has almost a similar structure to that of the nonvolatile memory according to Embodiment 1.
- the writing and reading operations of data in the nonvolatile memory of Embodiment 2 are similar to those of the nonvolatile memory of Embodiment 1.
- erasing of data is carried out by applying 9V to the n well 5 (n type semiconductor isolation region 3 ), 0V is applied to the p type semiconductor regions 15 B (the p wells 4 having MISFETs Qw 1 , Qw 2 , Qr 1 , Qr 2 formed thereover), ⁇ 9V to the p type semiconductor regions 15 A (the p wells 4 having the capacitive elements C 1 ,C 2 formed thereover), and 7V to the drain (n type semiconductor region 14 B) of the data writing and erasing MISFETs Qw 1 ,Qw 2 , and setting the source (n type semiconductor regions 14 B) at open potential and the source and drain (n type semiconductor regions 14 B) of the data reading MISFET Qr 1 ,Qr 2 at open potential.
- an electric field concentration occurs at the end portion of the gate electrode 7 A so that the gate insulating film 6 is formed with a film thickness (for example, about 13.5 nm) thick enough to endure the electric field concentration, whereby element deterioration of the data writing and erasing MISFETs Qw 1 ,Qw 2 can be prevented.
- Embodiment 2 brings about similar advantages to those available by Embodiment 1.
- FIG. 19 illustrates the cross-section taken along a line D-D′ of FIG. 14 in Embodiment 1.
- the nonvolatile memory of Embodiment 3 has almost a similar structure to that of the nonvolatile memory of Embodiment 1.
- the data erasing and reading operations in the nonvolatile memory of Embodiment 3 are similar to those of the nonvolatile memory of Embodiment 1.
- writing of data is carried out by applying 9V to the n well 5 (n type semiconductor isolation region 3 ), ⁇ 9V to the p type semiconductor regions 15 B (the p wells 4 having the MISFETs Qw 1 , Qw 2 , Qr 1 , Qr 2 formed thereover), and 9V to the p type semiconductor regions 15 A (the p wells 4 having the capacitive elements C 1 ,C 2 formed thereover), and setting the source and drain (n type semiconductor regions 14 B) of the data writing and erasing MISFETs Qw 1 ,Qw 2 and data reading MISFETs Qr 1 ,Qr 2 at open potential.
- FIG. 20 is a fragmentary cross-sectional view of the memory cell portion of a semiconductor device according to Embodiment 4. It corresponds to the cross-section taken along a line A-A′ of each plan view illustrated in Embodiment 1.
- the p well 4 and n well 5 When the junction breakdown voltage between the p well 4 and n well 5 becomes insufficient owing to miniaturization of a semiconductor element or interconnect, the p well 4 and n well 5 may be separated from each other as illustrated in FIG. 20 . By this, the junction breakdown voltage between the p well 4 and n well 5 can be improved. When a space between two p wells 4 is sufficiently wide, the n well 5 may be omitted.
- FIG. 21 illustrates a cross-section taken along a line D-D′ in FIG. 14 in Embodiment 1.
- the nonvolatile memory of Embodiment 5 has almost a similar structure to that of the nonvolatile memory of Embodiment 1.
- erasing of data is carried out by applying 9V to the n well 5 (n type semiconductor isolation region 3 ), 9V to the p type semiconductor regions 15 B (the p wells 4 having the MISFETs Qw 1 , Qw 2 , Qr 1 , Qr 2 formed therein), ⁇ 9V to the p type semiconductor regions 15 A (the p wells 4 having the capacitive elements C 1 ,C 2 formed thereover), and 9V to the source and drain of the data writing and erasing MISFETs Qw 1 ,Qw 2 and the source and drain (n type semiconductor regions 14 B) of the data reading MISFETs Qr 1 ,Qr 2 .
- Embodiment 5 To set the drain of the data writing and erasing MISFETs Qw 1 ,Qw 2 at open potential as in Embodiment 1 when erasing of data is carried out, another control MISFET becomes necessary, which disturbs downsizing of a semiconductor device. In this Embodiment 5, therefore, a similar operation condition to that of Embodiment 1 is available by applying 9V to the source and drain of the data writing and erasing MISFETs Qw 1 ,Qw 2 and the source and drain of the data reading MISFETs Qr 1 ,Qr 2 .
- the impurity concentration is adjusted to be high so as to facilitate generation of hot electrons and the junction breakdown voltage is suppressed to about 7V or less, which is lower than the voltage (9V or less) causing no gate breakage as described in Embodiment 1.
- 9V is therefore applied to the drain of the MISFETs Qw 1 ,Qw 2 prior to the application of 9V to the p well 4 .
- application of a voltage to the drain of the MISFETs Qw 1 ,Qw 2 may be started before application of a voltage to the p well 4 is started.
- the voltage of the drain is adjusted to 4V or 5V prior to an increase of it to 9V.
- application of a voltage to the p well 4 may be started.
- only a timing of voltage application is different and a change in the voltage of the p well 4 must be similar to that in the voltage of the drain of the MISFETs Qw 1 ,Qw 2 . This makes it possible to suppress the potential difference V 1 between them so as not to exceed the junction breakdown voltage, that is, about 7V.
- a reduction in the voltage of the p well 4 may be followed by a reduction in the drain voltage of the MISFETs Qw 1 ,Qw 2 and a voltage change at this time may be caused in the reverse order from the procedure for voltage increase.
- the voltage of the source and drain of the data reading MISFETs Qr 1 ,Qr 2 may be adjusted to 0V when writing of data is carried out.
- the voltage of the source and drain of the data writing and erasing MISFETs Qw 1 ,Qw 2 may be adjusted to 0V when reading is carried out.
- a semiconductor device including a MISFET having a breakdown voltage as high as about 20V or greater as an LCD driver
- the semiconductor device according to the present invention can be applied to, for example, a semiconductor device having a nonvolatile memory.
Abstract
Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to a p type semiconductor region, and −9V to another p type semiconductor region and setting the source and drain of data writing and erasing MISFETs and data reading MISFETs at open potential to emit electrons from a gate electrode to a p well by FN tunneling. At this time, by applying a negative voltage to the p well having a capacitive element formed thereover and applying a positive voltage to the p well having the MISFETs formed thereover, a potential difference necessary for data erasing operation can be secured at a voltage low enough not to cause gate breakage.
Description
- This application is a continuation of U.S. application Ser. No. 11/925,106, filed Oct. 26, 2007, which, in turn, is a continuation of U.S. application Ser. No. 11/206,968, filed Aug. 19, 2005 (now U.S. Pat. No. 7,313,026), and, which application claims priority from Japanese patent application No. 2004-261751 filed on Sep. 9, 2004, the contents of which are hereby incorporated by reference into this application.
- The present invention relates to a semiconductor device and manufacturing technology thereof, in particular, to a technology effective when applied to a semiconductor device having a non-volatile memory such as electric erasable programmable read only memory (which will hereinafter be called “flash memory”, simply).
- In Japanese Unexamined Patent Publication No. 2001-185633 (Patent Document 1), disclosed is an EEPROM device fabricated on a single conductive layer formed on a semiconductor substrate, while being insulated via an insulation layer; wherein the EEPROM device is a single level poly EEPROM device whose area per bit can be reduced.
- In Japanese Unexamined Patent Publication No. 2001-257324 (Patent Document 2), disclosed is a technology capable of improving a long-term data holding performance in a nonvolatile memory device formed by a single layer poly-flash technology.
- The present inventors have investigated a technology of forming a nonvolatile memory by only the manufacturing steps of a complementary MISFET without adding another step thereto. During the investigation, they have found the problems as described below.
- When a fuse circuit is formed using the above-described nonvolatile memory, data are erased electrically at a drain end by FN (Fowler-Nordheim) tunneling. This causes electric field concentration in the drain end and inevitably accelerates element deterioration.
- When an OTPROM (One Time Programmable Read Only Memory) type fuse circuit is formed using a nonvolatile memory, a memory capacity corresponding to the rewriting frequency must be required because it does not practically carry out rewrite operation, and the module size inevitably becomes large. In addition, a manufacturing cost of the module inevitably increases with a rise in the memory capacity and an increase in the module size.
- An object of the present invention is to provide a nonvolatile memory showing less element deterioration and good data retaining properties.
- Another object of the present invention is to provide a technology capable of downsizing the module having a nonvolatile memory mounted therein.
- The above-described and other objects and novel features of the present invention will be apparent from the description herein and accompanying drawings.
- Of the inventions disclosed by the present application, typical ones will next be summarized.
- In the present invention, there is thus provided a semiconductor device, equipped with a nonvolatile memory cell, which comprises:
- a first conductivity type semiconductor isolation layer formed over a main surface of a semiconductor substrate;
- a second conductivity type first well and a second conductivity type second well, each formed in the semiconductor isolation layer;
- a first conductivity type third well formed in the semiconductor isolation layer and separating the first well and the second well;
- a first gate electrode extending over the first well and the second well via a first gate insulating film; and
- a data writing MISFET and a data reading MISFET, each formed in the first well and using the first gate electrode as a gate electrode,
- wherein a first voltage in a forward direction is applied to the second well when writing of data to the nonvolatile memory cell is carried out, and
- wherein a first voltage in a reverse direction is applied to the second well when erasing of data from the nonvolatile memory cell is carried out.
- Advantages available by the typical inventions, of the inventions disclosed by the present application, will next be described.
- The present invention makes it possible to manufacture a nonvolatile memory showing less element deterioration and good data retaining properties.
- The present invention also makes it possible to downsize a module having a nonvolatile memory mounted therein.
-
FIG. 1 is a fragmentary plan view illustrating a manufacturing method of a semiconductor device according toEmbodiment 1 of the present invention; -
FIG. 2 is a fragmentary cross-sectional view illustrating a manufacturing method of the semiconductor device according toEmbodiment 1 of the present invention; -
FIG. 3 is a fragmentary plan view of the semiconductor device during its manufacturing step following that ofFIG. 1 ; -
FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during its manufacturing step following that ofFIG. 2 ; -
FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during its manufacturing step following that ofFIG. 4 ; -
FIG. 6 is a fragmentary plan view of the semiconductor device during its manufacturing step following that ofFIG. 3 ; -
FIG. 7 is a fragmentary cross-sectional view of the semiconductor device during its manufacturing step following that ofFIG. 4 ; -
FIG. 8 is a fragmentary cross-sectional view illustrating an enlarged A-A′ cross-section ofFIG. 7 ; -
FIG. 9 is a fragmentary cross-sectional view illustrating an enlarged B-B′ cross-section ofFIG. 7 ; -
FIG. 10 is a fragmentary cross-sectional view illustrating an enlarged C-C′ cross-section ofFIG. 7 ; -
FIG. 11 is a fragmentary plan view of the semiconductor device during its manufacturing step following that ofFIG. 6 ; -
FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during its manufacturing step following that ofFIG. 7 ; -
FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during its manufacturing step following that ofFIG. 12 ; -
FIG. 14 is a fragmentary plan view of the semiconductor device according toEmbodiment 1 of the present invention; -
FIG. 15 is a fragmentary cross-sectional view illustrating the data writing operation of a nonvolatile memory of the semiconductor device according toEmbodiment 1 of the present invention; -
FIG. 16 is a fragmentary cross-sectional view illustrating the data erasing operation of the nonvolatile memory of the semiconductor device according toEmbodiment 1 of the present invention; -
FIG. 17 is a fragmentary cross-sectional view illustrating the data reading operation of the nonvolatile memory of the semiconductor device according toEmbodiment 1 of the present invention; -
FIG. 18 is a fragmentary cross-sectional view illustrating the data erasing operation of a nonvolatile memory of a semiconductor device according toEmbodiment 2 of the present invention; -
FIG. 19 is a fragmentary cross-sectional view illustrating the data writing operation of a nonvolatile memory of a semiconductor device according toEmbodiment 3 of the present invention; -
FIG. 20 is a fragmentary cross-sectional view of a semiconductor device according toEmbodiment 4 of the present invention; -
FIG. 21 is a fragmentary cross-sectional view illustrating the data erasing operation of a nonvolatile memory of a semiconductor device according toEmbodiment 5 of the present invention; -
FIG. 22 is a schematic view illustrating the timing of voltage application when erasing of data is carried out in the nonvolatile memory of the semiconductor device according toEmbodiment 5 of the present invention; -
FIG. 23 is a schematic view illustrating the timing of voltage application when erasing of data is carried out in the nonvolatile memory of the semiconductor device according toEmbodiment 5 of the present invention; and -
FIG. 24 is a schematic view illustrating the timing of voltage application when erasing of data is carried out in the nonvolatile memory of the semiconductor device according toEmbodiment 5 of the present invention. - Embodiments of the present invention will hereinafter be described in full detail based on accompanying drawings. In all the drawings for describing the below-described embodiments, elements having like function will be identified by like reference numerals and overlapping descriptions will be omitted.
- The semiconductor device according to Embodiment 1 has a nonvolatile memory. The manufacturing steps of the semiconductor device of
Embodiment 1 will next be described with reference toFIGS. 1 to 13 . -
FIGS. 1 , 3, 6 and 11 are each a fragmentary plan view of a memory cell region of the semiconductor device ofEmbodiment 1 during its manufacturing step, whileFIGS. 2 , 4, 5, 7-10, 12 and 13 are each a fragmentary cross-sectional view illustrating the manufacturing step of the semiconductor device ofEmbodiment 1. In each cross-sectional view, a portion marked with A and A′ is a cross-section taken along a line A-A′ in the corresponding plan view; a portion marked with B and B′ is a cross-section taken along a line B-B′ in the corresponding plan view, and a portion marked with C and C′ is a cross-section of a part (a region in which an n channel type MISFET (Metal Insulator Semiconductor Field Effect Transistor) is to be formed) of a peripheral circuit region. Each plan view includes only main conductive layers constituting the nonvolatile memory cell and connection regions of them and an insulating film formed between conductive layers is omitted in principle. An X decoder circuit, Y decoder circuit, sense amplifier circuit, input/output circuit, logic circuit and the like are formed using an n channel MISFET constituting the peripheral circuit. Not only these circuits but also logic circuits such as microprocessor and CPU may be formed. - As illustrated in
FIGS. 1 and 2 , anelement isolation trench 2 is formed in an element isolation region on the main surface of a semiconductor substrate (which will hereinafter be called “substrate” simply) made of, for example, p type single crystal silicon. Thiselement isolation trench 2 is formed, for example, by dry etching the main surface of thesubstrate 1 to form a trench, depositing an insulating film such as silicon oxide film over thesubstrate 1 including the inside of this trench by CVD (Chemical Vapor Deposition), and polishing and removing an unnecessary portion of the insulating film outside of the trench by chemical mechanical polishing (CMP) to leave the insulating film inside of the trench. By forming thiselement isolation trench 2, an active region having a periphery defined by theelement isolation trench 2 is formed over the main surface of thesemiconductor substrate 1 of the memory array. - After ion implantation of an n type (first conductivity type) impurity (for example, P (phosphorus) or As (arsenic)) into a part of the
substrate 1, the resultingsubstrate 1 is heat treated to diffuse the impurity into thesubstrate 1, whereby an n type semiconductor separation region (semiconductor isolation layer) 3 is formed. - After implantation of an n type impurity (for example, P) into a part of the
substrate 1 and implantation of a p type (second conductivity type) impurity (for example, B (boron)) into another part of the substrate, the resultingsubstrate 1 is heat treated to diffuse these impurities into thesubstrate 1, whereby p wells (first well, second well) 4 and n well (third well) 5 are formed over the main surface of thesubstrate 1. - As illustrated in
FIGS. 3 and 4 , thesubstrate 1 is thermally oxidized to form a gate insulating film (first gate insulating film) 6 made of, for example, silicon oxide and having a film thickness of about 13.5 nm on the surface of each of thep wells 4 andn well 5. After formation of a polycrystalline silicon film over thegate insulating film 6, for example, by CVD, an insulating film made of a silicon oxide film is deposited, for example, by CVD over the polycrystalline silicon film. Prior to the formation of the insulating film, an n conductivity type impurity has been implanted into the polycrystalline silicon film. The insulating film in the peripheral circuit region is then removed by dry etching with a photoresist film (not illustrated) patterned by photolithography. An insulating film made of a silicon oxide film or the like having a film thickness of about 10 nm or greater is deposited, for example, by CVD over thesubstrate 1. - By dry etching with a photoresist film (not illustrated) patterned by photolithography, the insulating film on the
substrate 1 is patterned. By dry etching with the remaining insulating film as a mask, the polycrystalline silicon film is patterned to form gate electrodes (first gate electrodes) 7A, 7B, 7C. The insulating films over thegate electrodes cap insulating film 8. - Lightly doped n type semiconductor regions NMa, NMb, NMc are formed by ion implantation of P or As as an n type impurity into a part of the
p wells 4 and n well 5, while lightly doped p type semiconductor regions PMa, PMb are formed by ion implantation of boron as a p type impurity into a part of thep wells 4. These lightly doped n type semiconductor regions NMa, NMb, NMc and lightly doped p type semiconductor regions PMa, PMb are regions with a lower impurity concentration than ntype semiconductor regions type semiconductor regions - As illustrated in
FIG. 5 , after deposition of a silicon oxide film over thesubstrate 1 by CVD, the silicon oxide film and cap insulatingfilm 8 are anisotropically etched to formsidewall spacers 12 over the sidewalls of thegate electrodes sidewall spacers 12 are formed from the silicon oxide film, thecap film 8 is removed from the peripheral circuit region, whereby the surface of thegate electrode 7C is exposed. This is because the thickness of thecap insulating film 8 in the memory cell region is thicker than that of thecap film 8 in the peripheral circuit region and etching stops at a position where the surface of thegate electrode 7C in the peripheral circuit region is exposed. - As illustrated in
FIGS. 6 and 7 , P or As is ion-implanted as an n type impurity into a part of thep wells 4 and n well 5 to form ntype semiconductor regions p wells 4 to form ptype semiconductor regions FIG. 6 (exceptFIGS. 8 to 10 ), the description on the lightly doped n type semiconductor regions NMa, NMb, NMc and lightly doped p type semiconductor regions PMa, PMb is omitted in order to simplify the description and highly doped ntype semiconductor regions type semiconductor regions type semiconductor region 14B as a source and drain, data reading MISFETs Qr1,Qr2 having the ntype semiconductor region 14B as a source and drain, capacitive elements C1,C2 having thegate electrodes gate insulating film 6 as a capacitive insulating film are formed in the memory cell region, while an n channel MISFET (first MISFET) having the ntype semiconductor region 14C as a source and drain is formed in the peripheral circuit region. In the memory cell region, a nonvolatile memory element having thegate electrodes type semiconductor region 15A as a control gate is formed. - An enlarged view of
FIG. 7 is shown in each ofFIGS. 8 to 10 . - As illustrated in
FIG. 8 , a region which will be a control gate of the nonvolatile memory element is a region subjected to ion implantation for forming the lightly doped p type semiconductor region PMa and highly doped ptype semiconductor region 15A. A feeder portion of thep wells 4 is a region subjected to ion implantation for forming the lightly doped p type semiconductor region PMa and highly doped ptype semiconductor region 15B. Similarly, a feeder portion of then well 5 is a region subjected to ion implantation for forming the lightly doped n type semiconductor region NMa and highly doped ntype semiconductor region 14A. - As illustrated in
FIG. 9 , the source and drain regions of the data writing and erasing MISFETs Qw1,Qw2 and data reading MISFETs Qr1,Qr2 are each composed of the lightly doped n type semiconductor region NMb and highly doped ntype semiconductor region 14B. Descriptions on feeder portions of the p well 4 and n well 5 are similar to those on the feeder portion of the p well 4 and n well 5 inFIG. 8 . - As illustrated in
FIG. 10 , the source and drain regions of the n channel MISFET in the peripheral circuit region are each composed of the lightly doped n type semiconductor region NMb and highly doped ntype semiconductor region 14B. - The impurity concentration of the lightly doped n type semiconductor region NMb of the data writing and erasing MISFETs Qw1,Qw2 can be made higher than that of the lightly doped n type semiconductor regions NMa,NMc. When the lightly doped n type semiconductor region NMb has such a higher impurity concentration, a generation amount of hot electrons during writing operation of the MISFETs Qw1,Qw2 can be increased, which makes it possible to speed up the writing operation of the memory cell.
- In
FIGS. 8 to 10 , the lightly doped n type semiconductor regions NMa, NMb, NMc are thus illustrated in detail. The other diagrams (such asFIG. 7 ) do not include them in order to simplify the description but include only ntype semiconductor regions type semiconductor regions - A
silicide layer 18 is then formed. Thissilicide layer 18 is formed in the following manner. First, a Co (cobalt) film is deposited over thesubstrate 1, for example, by sputtering. Thesubstrate 1 is heat treated to cause a silicide reaction on the interface between the Co film andgate electrode 7C in the peripheral circuit region and on the interface between the Co film andsubstrate 1. The unreacted Co film is then removed by etching, whereby a silicide (CoSi2)layer 18 is formed on the surfaces of thegate electrode 7C and source and drain (n type semiconductor region 14). In the memory cell region, thesilicide layer 18 is formed on the surface of the n type semiconductor region 14. Since thecap insulating film 8 remains on the surfaces of thegate electrodes silicide layer 18 is formed thereon. InEmbodiment 1, Co (cobalt) is used as a material for thesilicide layer 18, but without limitation to it, Ti (titanium), W (tungsten), Ni (nickel) or the like can also be used. - As illustrated in
FIGS. 11 and 12 , asilicon nitride film 19 is deposited over thesubstrate 1 by plasma CVD so as to cover thegate electrodes film 8 andsidewall spacers 12. When an interlayer insulating film is formed over thesubstrate 1 and then contact holes extending down to the ntype semiconductor regions type semiconductor regions silicon nitride film 19 and the silicon oxide film embedded in the element isolation trench, the silicon nitride film functions to prevent the contact holes from reaching the substrate even if the contact holes are formed over the element isolation trench owing to misalignment. It also functions to prevent the etching of the surface of thesilicide layer 18 by overetching. In short, thesilicon nitride film 19 functions as an etching stopper. - A
silicon oxide film 20 is then deposited over thesubstrate 1, for example, by CVD, and the surface of thesilicon oxide film 20 is planarized by chemical mechanical polishing. With a photoresist film as a mask, thesilicon oxide film 20 andsilicon nitride film 19 are dry etched, whereby contact holes reaching the ntype semiconductor regions type semiconductor regions silicon nitride film 19 serves as an etching stopper film when thesilicon oxide film 20 is etched.Plugs 22A to 22E are then formed inside of the contact holes. Theplug 22A reaches thesilicide layer 18 over the ntype semiconductor region 14A, theplug 22B reaches thesilicide layer 18 over the ntype semiconductor region 14B, theplug 22C reaches thesilicide layer 18 over the ntype semiconductor region 14C, theplug 22D reaches thesilicide layer 18 over the ptype semiconductor region 15A, and theplug 22E reaches thesilicide layer 18 over the ptype semiconductor region 15B. Theplugs 22A to 22E are formed, for example, by depositing a Ti (titanium) film and TiN (titanium nitride) film over thesilicon oxide film 20 including the inside of the contact holes by sputtering, depositing a TiN film and, as a metal film, a W (tungsten) film by CVD and then, removing the W film, TiN film and Ti film outside the contact holes by chemical mechanical polishing. - According to the manufacturing method of the semiconductor device of
Embodiment 1, a nonvolatile memory can be formed by the manufacturing steps of a complementary MISFET without adding thereto another step. - As illustrated in
FIG. 13 , a plurality ofinterconnects 23 are formed over thesilicon oxide film 20 and plugs 22A to 22E. Theinterconnects 23 are formed, for example, by depositing a Ti film, Al (aluminum) alloy film and TiN film successively over thesilicon oxide film 20 by sputtering, and patterning these Ti film, Al alloy film and TiN film by dry etching with a photoresist film as a mask. The number of interconnect layers to be stacked may be increased further by repeating steps similar to those employed for the formation of thesilicon oxide film 20 and interconnects 23. - Writing, erasing and reading operations in the nonvolatile memory in
Embodiment 1 will be described with reference toFIGS. 14 to 17 .FIG. 14 is a fragmentary plan view of the memory cell region andFIGS. 15 to 17 are cross-sections taken along a line D-D′ inFIG. 14 . InFIGS. 14 to 17 , theinterconnects 23 are not illustrated in order to facilitate the understanding of the description. - As illustrated in
FIG. 15 , writing of data is carried out by applying 9V to the n well 5 (n type semiconductor isolation region 3), 0V to the ptype semiconductor regions 15B (thep wells 4 having the MISFETs Qw1, Qw2, Qr1, Qr2 formed thereover), 9V (first voltage), that is, a forward voltage, to the ptype semiconductor regions 15A (thep wells 4 having the capacitive elements C1,C2 formed thereover), 7V (second voltage) to one of the source and drain (ntype semiconductor regions 14B) of the data writing and erasing MISFETs Qw1,Qw2, and 0V to the other one, and setting the source and drain (ntype semiconductor regions 14B) of the data reading MISFETs Qr1,Qr2 at open potential. By this, channel hot electrons (e−) are injected into thegate electrode 7A in the data writing and erasing MISFETs Qw1,Qw2, whereby writing of data is carried out. - Erasing of data is carried out, as illustrated in
FIG. 16 , by applying 9V to the n well 5 (the n type semiconductor isolation region 3), 9V to the ptype semiconductor regions 15B (thep wells 4 having the MISFETs Qw1, Qw2, Qr1, Qr2 formed thereover), and −9V, that is, a reverse voltage, to the ptype semiconductor regions 15A (thep wells 4 having the capacitive elements C1,C2 formed thereover), and setting the source and drain (ntype semiconductor regions 14B) of the data writing and erasing MISFETs Qw1,Qw2 and data reading MISFETs Qr1,Qr2 at open potential. The capacitive electrodes (gate electrodes gate electrodes FIG. 14 ) so that the capacitance of the capacitive elements C1,C2 becomes greater than the gate capacitance (formed between thegate electrodes gate electrode 7A by FN tunneling. As a result, deterioration of an element, which will otherwise occur owing to the concentration of an electric field at the end portion of the drain (ntype semiconductor region 14B) can be prevented. Since the deterioration of an element can be prevented, leakage of charges can also be prevented. This makes it possible to prevent the deterioration of data retaining properties of the nonvolatile memory. In addition, by applying a negative (reverse) voltage to the p well 4 over which the capacitive elements C1,C2 are formed and applying a positive (forward) voltage to the p well 4 over which the MISFETs Qw1, Qw2, Qr1, Qr2 are formed, it becomes possible to maintain a potential difference (18V) necessary for data erasing operation at a voltage (9V or less) not causing gate breakage. - Reading of data is carried out, as illustrated in
FIG. 17 , by applying 3V to the n well 5 (the n type semiconductor isolation region 3), 0V to the ptype semiconductor regions 15B (thep wells 4 having the MISFETs Qw1, Qw2, Qr1, Qr2 formed thereover), and 3V to the ptype semiconductor regions 15A (thep wells 4 having the capacitive elements C1,C2 formed thereover), setting the source and drain (ntype semiconductor regions 14B) of the data writing and erasing MISFETs Qw1,Qw2 at open potential, and applying 1V to one of the source and drain (ntype semiconductor region 14B) of the data reading MISFETs Qr1,Qr2 and 0V to the other one. By this, the data reading MISFETs Qr1,Qr2 are turned ON. - In
Embodiment 1, the data writing and erasing MISFETs (Qw1,Qw2) and data reading MISFETs (Qr1,Qr2) are formed, respectively. Alternatively, it is also possible to omit one of them and perform all of the data writing, data erasing and data reading operations by one MISFET. - The nonvolatile memory as described in
Embodiment 1 can be used, for example, as a fuse circuit by accumulating voltage control data (picture quality control data) in an LCD (Liquid Crystal Display) driver. In this case, the module can be downsized compared with that of an OTPROM type fuse circuit which requires a memory capacity corresponding to the rewriting frequency, because data rewriting can be carried out according to need. In addition, the downsizing of the module leads to a reduction in the manufacturing cost of the module. - Another use of the nonvolatile memory according to
Embodiment 1 is relief of a defective memory cell of DRAM (Dynamic Random Access Memory) having a redundant configuration. At this time, the memory cell becomes a unit information cell and by a plurality of the gathered information cells, an electrical programming circuit for nonvolatile memory element is formed. The plurality of unit information cells becomes a memory circuit of a relief information for a circuit to be relieved. This makes it possible to enhance the reliability of defect relief. - A fuse programming circuit for storing relief information in accordance with the fused state of a fuse element may be disposed as another relief information memory circuit for the above-described circuit to be relieved. It is possible to raise a relief efficiency by using a fuse programming circuit for the relief of a defect detected at the stage of a wafer, while using the above-described electrical programming circuit for the relief of a defect detected after burn-in.
- The above-described relief circuit may be a memory cell of a microcomputer with built-in DRAM or a memory cell of a microcomputer with built-in SRAM. It may constitute a relief circuit of an LCD driver.
- Writing, erasing and reading operations in a nonvolatile memory according to
Embodiment 2 will next be described with reference toFIG. 18 . -
FIG. 18 illustrates a cross-section taken along a line D-D′ ofFIG. 14 inEmbodiment 1. As illustrated inFIG. 18 , the nonvolatile memory ofEmbodiment 2 has almost a similar structure to that of the nonvolatile memory according toEmbodiment 1. - The writing and reading operations of data in the nonvolatile memory of
Embodiment 2 are similar to those of the nonvolatile memory ofEmbodiment 1. As illustrated inFIG. 18 , erasing of data is carried out by applying 9V to the n well 5 (n type semiconductor isolation region 3), 0V is applied to the ptype semiconductor regions 15B (thep wells 4 having MISFETs Qw1, Qw2, Qr1, Qr2 formed thereover), −9V to the ptype semiconductor regions 15A (thep wells 4 having the capacitive elements C1,C2 formed thereover), and 7V to the drain (ntype semiconductor region 14B) of the data writing and erasing MISFETs Qw1,Qw2, and setting the source (ntype semiconductor regions 14B) at open potential and the source and drain (ntype semiconductor regions 14B) of the data reading MISFET Qr1,Qr2 at open potential. At this time, in the data writing and erasing MISFETs Qw1,Qw2, electric field concentration at the end portion of thegate electrode 7A occurs so that electrons (e−) can be emitted from thegate electrode 7A even at a voltage (7V) lower than that (9V) at the data erasing operation inEmbodiment 1. In the data writing and erasing MISFETs Qw1,Qw2, electrons (e−) are emitted from the end portion of thegate electrode 7A to the drain (ntype semiconductor region 14B) of the data writing and erasing MISFETs Qw1,Qw2. - In the data writing and erasing MISFETs Qw1,Qw2, an electric field concentration occurs at the end portion of the
gate electrode 7A so that thegate insulating film 6 is formed with a film thickness (for example, about 13.5 nm) thick enough to endure the electric field concentration, whereby element deterioration of the data writing and erasing MISFETs Qw1,Qw2 can be prevented. - This
Embodiment 2 brings about similar advantages to those available byEmbodiment 1. - Data writing, erasing and reading operations in a nonvolatile memory according to
Embodiment 3 will next be described with reference toFIG. 19 . -
FIG. 19 illustrates the cross-section taken along a line D-D′ ofFIG. 14 inEmbodiment 1. As illustrated inFIG. 19 , the nonvolatile memory ofEmbodiment 3 has almost a similar structure to that of the nonvolatile memory ofEmbodiment 1. - The data erasing and reading operations in the nonvolatile memory of
Embodiment 3 are similar to those of the nonvolatile memory ofEmbodiment 1. As illustrated inFIG. 19 , writing of data is carried out by applying 9V to the n well 5 (n type semiconductor isolation region 3), −9V to the ptype semiconductor regions 15B (thep wells 4 having the MISFETs Qw1, Qw2, Qr1, Qr2 formed thereover), and 9V to the ptype semiconductor regions 15A (thep wells 4 having the capacitive elements C1,C2 formed thereover), and setting the source and drain (ntype semiconductor regions 14B) of the data writing and erasing MISFETs Qw1,Qw2 and data reading MISFETs Qr1,Qr2 at open potential. By this, in the data writing and erasing MISFETs Qw1,Qw2 and data reading MISFET Qr1,lQr2, electrons (e−) are injected into thegate electrode 7A all over the channel by the FN tunneling and data writing is carried out. - In the above-described
Embodiment 3, similar advantages to those obtained inEmbodiment 1 are available. -
FIG. 20 is a fragmentary cross-sectional view of the memory cell portion of a semiconductor device according toEmbodiment 4. It corresponds to the cross-section taken along a line A-A′ of each plan view illustrated inEmbodiment 1. - When the junction breakdown voltage between the p well 4 and n well 5 becomes insufficient owing to miniaturization of a semiconductor element or interconnect, the p well 4 and n well 5 may be separated from each other as illustrated in
FIG. 20 . By this, the junction breakdown voltage between the p well 4 and n well 5 can be improved. When a space between twop wells 4 is sufficiently wide, the n well 5 may be omitted. - Similar advantages to those of
Embodiment 1 are available by the above-describedEmbodiment 4. - The data erasing operation in a nonvolatile memory according to
Embodiment 5 will next be described. -
FIG. 21 illustrates a cross-section taken along a line D-D′ inFIG. 14 inEmbodiment 1. As illustrated inFIG. 21 , the nonvolatile memory ofEmbodiment 5 has almost a similar structure to that of the nonvolatile memory ofEmbodiment 1. - In the nonvolatile memory according to
Embodiment 5, erasing of data is carried out by applying 9V to the n well 5 (n type semiconductor isolation region 3), 9V to the ptype semiconductor regions 15B (thep wells 4 having the MISFETs Qw1, Qw2, Qr1, Qr2 formed therein), −9V to the ptype semiconductor regions 15A (thep wells 4 having the capacitive elements C1,C2 formed thereover), and 9V to the source and drain of the data writing and erasing MISFETs Qw1,Qw2 and the source and drain (ntype semiconductor regions 14B) of the data reading MISFETs Qr1,Qr2. To set the drain of the data writing and erasing MISFETs Qw1,Qw2 at open potential as inEmbodiment 1 when erasing of data is carried out, another control MISFET becomes necessary, which disturbs downsizing of a semiconductor device. In thisEmbodiment 5, therefore, a similar operation condition to that ofEmbodiment 1 is available by applying 9V to the source and drain of the data writing and erasing MISFETs Qw1,Qw2 and the source and drain of the data reading MISFETs Qr1,Qr2. - In the channel region of the data writing and erasing MISFETs QW1,Qw2, the impurity concentration is adjusted to be high so as to facilitate generation of hot electrons and the junction breakdown voltage is suppressed to about 7V or less, which is lower than the voltage (9V or less) causing no gate breakage as described in
Embodiment 1. As illustrated inFIG. 22 , 9V is therefore applied to the drain of the MISFETs Qw1,Qw2 prior to the application of 9V to thep well 4. When the voltage of thep well 4 is reduced to 0V prior to a reduction of the drain voltage of the MISFETs Qw1,Qw2 to 0V, the potential difference V1 between them exceeds the junction breakdown voltage, leading to junction breakage. In the example shown inEmbodiment 5, therefore, a potential difference between them is suppressed so as not to exceed about 7V by applying, at a timing as illustrated inFIGS. 23 and 24 , a voltage to thep wells 4 over which the MISFETs Qw1, Qw2, Qr1, Qr2 have been formed and the drains (ntype semiconductor regions 14B) of the data writing and erasing MISFETs Qw1,Qw2 when erasing of data is carried out. - For example, as illustrated in
FIG. 23 , application of a voltage to the drain of the MISFETs Qw1,Qw2 is started before the application of a voltage to thep well 4 is started. At this time, these voltages are not increased drastically but gradually so that the potential difference V1 between them does not exceed the junction breakdown voltage, that is, about 7V. By reducing the voltage of the p well 4 to 0V prior to a reduction in the drain voltage of the MISFETs Qw1,Qw2 to 0V. By avoiding a drastic change in their voltage, it is possible to avoid a potential difference between them from exceeding about 7V. - As illustrated in
FIG. 24 , application of a voltage to the drain of the MISFETs Qw1,Qw2 may be started before application of a voltage to thep well 4 is started. The voltage of the drain is adjusted to 4V or 5V prior to an increase of it to 9V. During this period, application of a voltage to the p well 4 may be started. At this time, only a timing of voltage application is different and a change in the voltage of the p well 4 must be similar to that in the voltage of the drain of the MISFETs Qw1,Qw2. This makes it possible to suppress the potential difference V1 between them so as not to exceed the junction breakdown voltage, that is, about 7V. When the drain voltage of the MISFETs Qw1,Qw2 and the voltage of the p well 4 are reduced to 0V, a reduction in the voltage of the p well 4 may be followed by a reduction in the drain voltage of the MISFETs Qw1,Qw2 and a voltage change at this time may be caused in the reverse order from the procedure for voltage increase. - Similar advantages to those of
Embodiment 1 are also available in the above-describedEmbodiment 5. - The inventions made by the present inventors were described specifically based on some embodiments. It should however be borne in mind that the invention is not limited to or by them but can be modified to an extent not departing from its scope.
- For example, in
Embodiment 1, the voltage of the source and drain of the data reading MISFETs Qr1,Qr2 may be adjusted to 0V when writing of data is carried out. The voltage of the source and drain of the data writing and erasing MISFETs Qw1,Qw2 may be adjusted to 0V when reading is carried out. In a semiconductor device including a MISFET having a breakdown voltage as high as about 20V or greater, as an LCD driver, it is also possible to apply 0V to the n well 5, 0V to the ptype semiconductor region 15B, and −18V to the ptype semiconductor region 15A while setting the source and drain of the data writing and erasing MISFETs Qw1,Qw2 and data reading MISFETs Qr1,Qr2 at 0V or open potential. - The semiconductor device according to the present invention can be applied to, for example, a semiconductor device having a nonvolatile memory.
Claims (5)
1. A semiconductor device equipped with a memory cell having a data writing element and a capacitive element, comprising:
a first well of a second conductivity type formed in a semiconductor substrate of the second conductivity type;
a second well of the second conductivity type formed in the semiconductor substrate; and
a first conductive film extending over the first well and the second well via a first insulating film;
wherein a semiconductor isolation layer of a first conductivity type is formed in the semiconductor substrate,
wherein the first and second wells are formed in the semiconductor isolation layer and are separated from each other,
wherein the data writing element is arranged in the first well,
wherein the capacitive element is arranged in the second well,
wherein the data writing element includes the first insulating film, the first conductive film and a first impurity region of the first conductivity type formed in the first well,
wherein the capacitive element includes the first insulating film, the first conductive film and a second impurity region of the second conductivity type formed in the second well,
wherein the planar size of the first conductive film of the capacitive element is larger than the planar size of the first conductive film of the data writing element,
wherein the first conductive film is adapted to be used as a charging storage film of the memory cell, and
wherein the second impurity region is adapted to be used as a control gate of the memory cell,
wherein the memory cell is adapted to use Fowler-Nordheim tunneling for a writing operation or an erasing operation of the memory cell, and
wherein information on at least one of voltage control of an LCD driver and relief of a RAM is recorded in the memory cell.
2. A semiconductor device according to claim 1 ,
wherein a third well of the first conductivity type is formed in the semiconductor isolation layer and is formed between the first well and the second well.
3. A semiconductor device according to claim 1 ,
wherein the first conductivity type is n-type, and
wherein the second conductivity type is p-type.
4. A semiconductor device according to claim 1 ,
wherein the first conductive film is formed of a polysilicon film.
5. A semiconductor device according to claim 1 ,
wherein the memory cell is an EEPROM (Electrically Erasable and Programmable Read Only Memory).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/270,346 US20090154253A1 (en) | 2004-09-09 | 2008-11-13 | semiconductor device |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004-261751 | 2004-09-09 | ||
JP2004261751A JP4881552B2 (en) | 2004-09-09 | 2004-09-09 | Semiconductor device |
US11/206,968 US7313026B2 (en) | 2004-09-09 | 2005-08-19 | Semiconductor device |
US11/925,106 US7466599B2 (en) | 2004-09-09 | 2007-10-26 | Semiconductor device |
US12/270,346 US20090154253A1 (en) | 2004-09-09 | 2008-11-13 | semiconductor device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/925,106 Continuation US7466599B2 (en) | 2004-09-09 | 2007-10-26 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
US20090154253A1 true US20090154253A1 (en) | 2009-06-18 |
Family
ID=35996040
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/206,968 Active 2025-11-10 US7313026B2 (en) | 2004-09-09 | 2005-08-19 | Semiconductor device |
US11/925,106 Active US7466599B2 (en) | 2004-09-09 | 2007-10-26 | Semiconductor device |
US12/270,346 Abandoned US20090154253A1 (en) | 2004-09-09 | 2008-11-13 | semiconductor device |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/206,968 Active 2025-11-10 US7313026B2 (en) | 2004-09-09 | 2005-08-19 | Semiconductor device |
US11/925,106 Active US7466599B2 (en) | 2004-09-09 | 2007-10-26 | Semiconductor device |
Country Status (4)
Country | Link |
---|---|
US (3) | US7313026B2 (en) |
JP (1) | JP4881552B2 (en) |
KR (1) | KR101067093B1 (en) |
TW (1) | TWI424532B (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090225601A1 (en) * | 2008-03-07 | 2009-09-10 | United Microelectronics Corp. | Storage unit of single-conductor non-volatile memory cell and method of erasing the same |
US20090283812A1 (en) * | 2008-05-16 | 2009-11-19 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor memory device and manufacturing method thereof |
US8975127B2 (en) | 2007-06-11 | 2015-03-10 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
CN107195629A (en) * | 2011-07-26 | 2017-09-22 | 瑞萨电子株式会社 | Semiconductor devices |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100604871B1 (en) * | 2004-06-17 | 2006-07-31 | 삼성전자주식회사 | Complementary non-volatile memory device, methods of operating and manufacturing the same and logic device and semiconductor device comprising the same |
JP4800109B2 (en) * | 2005-09-13 | 2011-10-26 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP2007123830A (en) * | 2005-09-29 | 2007-05-17 | Matsushita Electric Ind Co Ltd | Non-volatile semiconductor memory device |
KR100735753B1 (en) * | 2005-10-04 | 2007-07-06 | 삼성전자주식회사 | Flash memory device having a shared bit line and fabrication method thereof |
JP4901325B2 (en) | 2006-06-22 | 2012-03-21 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP5228195B2 (en) * | 2007-04-20 | 2013-07-03 | インターチップ株式会社 | Nonvolatile memory built-in shift register |
JP5280716B2 (en) * | 2007-06-11 | 2013-09-04 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
TWI358067B (en) * | 2007-12-19 | 2012-02-11 | Powerchip Technology Corp | Integrated circuits and discharge circuits |
JP2010087357A (en) * | 2008-10-01 | 2010-04-15 | Toshiba Corp | Nonvolatile semiconductor storage device |
US10046141B2 (en) | 2008-12-30 | 2018-08-14 | Biosense Webster, Inc. | Deflectable sheath introducer |
KR20110047819A (en) * | 2009-10-30 | 2011-05-09 | 주식회사 하이닉스반도체 | Unit block circuit in a semiconductor device |
AU2011226074B2 (en) * | 2010-03-10 | 2015-01-22 | Vivoryon Therapeutics N.V. | Heterocyclic inhibitors of glutaminyl cyclase (QC, EC 2.3.2.5) |
US8958245B2 (en) | 2010-06-17 | 2015-02-17 | Ememory Technology Inc. | Logic-based multiple time programming memory cell compatible with generic CMOS processes |
US9042174B2 (en) | 2010-06-17 | 2015-05-26 | Ememory Technology Inc. | Non-volatile memory cell |
JP2013102119A (en) * | 2011-11-07 | 2013-05-23 | Ememory Technology Inc | Non-volatile memory cell |
US9361982B2 (en) * | 2014-02-04 | 2016-06-07 | Stmicroelectronics S.R.L. | Embedded non-volatile memory with single polysilicon layer memory cells programmable through band-to-band tunneling-induced hot electron and erasable through fowler-nordheim tunneling |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6845042B2 (en) * | 2003-02-05 | 2005-01-18 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory, fabrication method for the same, semiconductor integrated circuits and systems |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3083547B2 (en) | 1990-07-12 | 2000-09-04 | 株式会社日立製作所 | Semiconductor integrated circuit device |
DE4311358C2 (en) * | 1992-04-07 | 1999-07-22 | Mitsubishi Electric Corp | Non-volatile semiconductor memory device and operating method for a non-volatile semiconductor memory device and method for programming information into a non-volatile semiconductor memory device |
JPH07240473A (en) * | 1994-03-01 | 1995-09-12 | Fujitsu Ltd | Semiconductor memory and its fabrication |
US6965142B2 (en) * | 1995-03-07 | 2005-11-15 | Impinj, Inc. | Floating-gate semiconductor structures |
US5892709A (en) * | 1997-05-09 | 1999-04-06 | Motorola, Inc. | Single level gate nonvolatile memory device and method for accessing the same |
JP4212178B2 (en) * | 1999-03-12 | 2009-01-21 | 株式会社東芝 | Manufacturing method of semiconductor integrated circuit |
WO2000060672A1 (en) * | 1999-03-31 | 2000-10-12 | Koninklijke Philips Electronics N.V. | Semiconductor device comprising a non-volatile memory cell |
JP2001185633A (en) * | 1999-12-15 | 2001-07-06 | Texas Instr Inc <Ti> | Eeprom device |
JP4072300B2 (en) | 1999-12-22 | 2008-04-09 | 日本特殊陶業株式会社 | Wiring board with ceramic laminated structure |
JP4530464B2 (en) * | 2000-03-09 | 2010-08-25 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit |
US6284603B1 (en) * | 2000-07-12 | 2001-09-04 | Chartered Semiconductor Manufacturing Inc. | Flash memory cell structure with improved channel punch-through characteristics |
JP4923321B2 (en) | 2000-09-12 | 2012-04-25 | ソニー株式会社 | Method of operating nonvolatile semiconductor memory device |
US6788574B1 (en) * | 2001-12-06 | 2004-09-07 | Virage Logic Corporation | Electrically-alterable non-volatile memory cell |
FR2838554B1 (en) * | 2002-04-15 | 2004-07-09 | St Microelectronics Sa | NON-VOLATILE, PROGRAMMABLE AND ELECTRICALLY ERASABLE MEMORY CONDUCTOR WITH A SINGLE LAYER OF GRID MATERIAL, AND CORRESPONDING MEMORY PLAN |
WO2003096432A1 (en) | 2002-05-09 | 2003-11-20 | Impinj, Inc. | Pseudo-nonvolatile direct-tunneling floating-gate device |
JP3957561B2 (en) * | 2002-05-24 | 2007-08-15 | 株式会社リコー | Semiconductor device |
JP4601287B2 (en) | 2002-12-26 | 2010-12-22 | ルネサスエレクトロニクス株式会社 | Nonvolatile semiconductor memory device |
-
2004
- 2004-09-09 JP JP2004261751A patent/JP4881552B2/en not_active Expired - Fee Related
-
2005
- 2005-05-24 TW TW094116894A patent/TWI424532B/en active
- 2005-08-19 US US11/206,968 patent/US7313026B2/en active Active
- 2005-08-19 KR KR1020050076135A patent/KR101067093B1/en active IP Right Grant
-
2007
- 2007-10-26 US US11/925,106 patent/US7466599B2/en active Active
-
2008
- 2008-11-13 US US12/270,346 patent/US20090154253A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6845042B2 (en) * | 2003-02-05 | 2005-01-18 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory, fabrication method for the same, semiconductor integrated circuits and systems |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8975127B2 (en) | 2007-06-11 | 2015-03-10 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US9184126B2 (en) | 2007-06-11 | 2015-11-10 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US9601433B2 (en) | 2007-06-11 | 2017-03-21 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US9812317B2 (en) | 2007-06-11 | 2017-11-07 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US10096467B2 (en) | 2007-06-11 | 2018-10-09 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US20090225601A1 (en) * | 2008-03-07 | 2009-09-10 | United Microelectronics Corp. | Storage unit of single-conductor non-volatile memory cell and method of erasing the same |
US7639536B2 (en) * | 2008-03-07 | 2009-12-29 | United Microelectronics Corp. | Storage unit of single-conductor non-volatile memory cell and method of erasing the same |
US20090283812A1 (en) * | 2008-05-16 | 2009-11-19 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor memory device and manufacturing method thereof |
US8188535B2 (en) | 2008-05-16 | 2012-05-29 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor memory device and manufacturing method thereof |
US8872251B2 (en) | 2008-05-16 | 2014-10-28 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor memory device and manufacturing method thereof |
CN107195629A (en) * | 2011-07-26 | 2017-09-22 | 瑞萨电子株式会社 | Semiconductor devices |
Also Published As
Publication number | Publication date |
---|---|
US7466599B2 (en) | 2008-12-16 |
JP2006080247A (en) | 2006-03-23 |
TWI424532B (en) | 2014-01-21 |
US20080056011A1 (en) | 2008-03-06 |
KR20060053161A (en) | 2006-05-19 |
TW200610101A (en) | 2006-03-16 |
KR101067093B1 (en) | 2011-09-22 |
US7313026B2 (en) | 2007-12-25 |
US20060050566A1 (en) | 2006-03-09 |
JP4881552B2 (en) | 2012-02-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7466599B2 (en) | Semiconductor device | |
US8344444B2 (en) | Semiconductor device having a nonvolatile memory cell with a cap insulating film formed over a selection gate electrode | |
US8497547B2 (en) | Semiconductor device and a method of manufacturing the same | |
JP5985293B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
US7547599B2 (en) | Multi-state memory cell | |
US7241695B2 (en) | Semiconductor device having nano-pillars and method therefor | |
US20020171112A1 (en) | Non-volatile semiconductor memory device having memory cell array suitable for high density and high integration | |
US20020033501A1 (en) | Nonvolatile semiconductor memory and method of fabricating the same | |
US20160064507A1 (en) | Semiconductor device and method of manufacturing same | |
US20050239245A1 (en) | Nonvolatile semiconductor memory and method of operating the same | |
US20110001180A1 (en) | Nonvolatile semiconductor memory device | |
KR20030081622A (en) | Non-volitile memory device and method thereof | |
CN105655339B (en) | Semiconductor device and method for manufacturing the same | |
JP2626523B2 (en) | Nonvolatile semiconductor memory device and method of manufacturing the same | |
CN107240548B (en) | Semiconductor device and method for manufacturing the same | |
US8451641B2 (en) | Memory array no common source region and method of fabricating the same | |
US7960779B2 (en) | Nonvolatile semiconductor memory and manufacturing method thereof | |
JP2007534157A (en) | Self-aligned charge separation structure NROM flash memory | |
US7220651B2 (en) | Transistor and method for manufacturing the same | |
US6716698B1 (en) | Virtual ground silicide bit line process for floating gate flash memory | |
US20220157964A1 (en) | Semiconductor device | |
JP2005340297A (en) | Semiconductor device and its manufacturing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO PAY ISSUE FEE |