CN1669155A - Pseudo-nonvolatile direct-tunneling floating-gate device - Google Patents
Pseudo-nonvolatile direct-tunneling floating-gate device Download PDFInfo
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
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Abstract
A semiconductor device is provided that uses a floating gate to store analog- and digital-valued information for periods of time measured in milliseconds to hours. Charge is added to and/or removed from the floating gate by means of direct electron tunneling through the surrounding insulator, with the insulator typically being thin enough such that appreciable tunneling occurs with an insulator voltage smaller than the difference in electron affinities between the semiconductor and the insulator and/or between the floating gate and the insulator. The stored information is refreshed or updated as needed. In many applications, the stored information can be refreshed without interrupting normal circuit operation. Adding and removing charge to or from the floating gate may be performed using separate circuit inputs, to tailor the performance and response of the floating-gate device. There is no need to use a control gate in the floating-gate structures disclosed herein.
Description
The general introduction of related application
Present application for patent is the U.S. patent application case the 10/143rd of applying on May 9th, 2002 with the name of inventor John D.Hyde and Yanjun Ma, No. 557 the part application case that continues, U.S. patent application case the 10/143rd, No. 557 name is called " Metal dielectric semiconductor floatinggate variable capacitor ", and itself and the application's case are conveyed jointly.
Technical field
The present invention relates to a kind of method and apparatus that is stored in the electric charge on the floating boom semiconductor device floating boom that is used to regulate.More particularly, the present invention relates to use a direct tunnelling (direct-tunneling) mechanism to regulate the last stored charge of analog-and digital-value pseudo-nonvolatile floating boom (PNVFG) MOSFET.
Background technology
There are many kinds to be used for the semiconductor device of stored information at present.Storage is divided into two classes usually: long-term or short-term.Long-term storage devices comprises read-only memory (ROM), programmable read-only memory (prom), EPROM (EPROM), Electrically Erasable Read Only Memory (EEPROM), flash non-volatile memory (Flash NVM), ferroelectric RAM (FRAM), magnetoresistive RAM (MRAM), silicon-oxide-nitride--oxide-silicon (SONOS) memory and many other memories.In many those long-term storage devices, institute's canned data comprises the electric charge in some electric charge holding region territories that are stored in semiconductor device.Long term memory has low relatively leak rate usually, so it keeps readable in the time of about several years.Short term memory device is finer and close and be easier to wipe and rewrite than long-term storage devices usually, but has the high relatively shortcoming of leak rate usually.Those devices comprise known dynamic random access memory (DRAM), switch capacitor circuit and capacitive trimming circuit and version thereof.Because those devices can be lost its stored charge in the number microsecond usually to several milliseconds markers, so need often to upgrade, renewal frequency makes it can keep stored information in time at least.Semiconductor design those skilled in the art know many circuit that are used to refresh.
Existing many last methods that is used for the non-volatile storage electric charge at floating-gate MOS FET (mos field effect transistor).Those methods need be used usually than the high voltage of those normal operation CMOS (complementary metal oxide semiconductors (CMOS)) logic required voltages, and/or it adopts asymmetric electric charge control, wherein a kind of technology is used for adding electric charge to floating boom, and a kind of different technology (having corresponding different structure and/or different capacity requirement) is used for removing electric charge from floating boom.In most methods, when being in the change state, can not read electric charge stored charge value on the floating boom.
Go to Fig. 1, it is a typical art methods of this device of illustration in simplified form.Floating-gate MOS FET10 is formed on the p-substrate 12 of semiconductor wafer.Wherein be formed with n-trap 14, and in this n-trap, be formed with source area 16 and the drain region 18 that constitutes by the p+ material.On the passage 20 between source area 16 and the drain region 18, be insulator layer 21 such as silica (or silicon nitride or silicon oxynitride or other know insulating material) for example, this layer can form by growth or deposition.Form an electric charge on the insulator 21 and keep layer 22 or " floating boom ", it can keep electric charge, is generally an insulated electric conductor, for example metal or heavily doped polysilicon.Usually apply a further insulator layer 24 and structural top one conductive control grid 26 is arranged usually.Control gate 26 is structured in the second layer of a heavily doped polysilicon usually.Add electric charge and/or be to use (FN) tunnelling of Fu Le-Nuo Dehan (Fowler-Nordheim) to floating-gate MOS FET from its common method that removes electric charge.Fig. 2 A, 2B and 2C are for showing the electron energy band figure of semiconductor, insulator and grid.Fig. 2 A shows that the insulator two ends do not apply a state of voltage.As shown in Fig. 2 A, the pure SiO thick relatively and leakage rate is low
2Insulator 27 forms a potential barrier 28, and the doped region 32 of floating boom 30 with semiconductor substrate separated.In FN tunnelling shown in Fig. 2 B, the voltage that puts on insulator 28 two ends makes electronics with the potential barrier 28 between quantum mechanics mechanism tunnelling semiconductor 32 and the insulator 27, enters the conductive strips of insulator 27, and is transported to floating boom 30 thus.Equally, the voltage of an opposite polarity makes electronics be delivered to semiconductor 32 from floating boom 30 by insulator 27.The FN tunnelling is filled perhaps electric charge and is accumulated on the floating boom 30 or from it and remove.
Use Fu Le-Nuo Dehan tunnelling transfer charge to have some shortcoming.At first, its voltage that requires to use surpasses normal cmos circuit operation applied voltage usually.Therefore, need to use charge pump or extra power supply.The second, this control gate needs second layer polysilicon usually.Compare with single polysilicon CMOS process commonly used, cost and complexity that this extra polysilicon layer is made device increase.The 3rd, need high relatively electric field owing to implement Fu Le-Nuo Dehan tunnelling insulator, so insulator can engender damage, causing electric charge to leak usually increases.This damage is usually expressed as the leakage current (SILC) that stress causes, and is that most EEPROM or Flash nonvolatile memory life-span are limited (for example, in present commercially available prod about 10
5Individual circulation) reason place.
One alternative form of Fu Le-Nuo Dehan tunnelling is a direct Tunneling.In direct Tunneling shown in Fig. 2 C, insulator 27 is enough thin, though when the voltage at insulator 27 two ends less than the electron affinity between semiconductor 32 and the insulator 27 (for example, for silicon-SiO
2The barrier layer is 3.2 volts) time also tangible tunnelling can appear.Compare Fu Le-Nuo Dehan tunnelling, using a remarkable advantage of direct Tunneling is that insulator stress and SILC reduce because of the insulator electric field weakens.Another remarkable advantage is the voltage that direct Tunneling does not need obviously to exceed normal logic-CMOS operation required voltage.The reason that present direct Tunneling is not widely used in electronic application is, insulator tends to by writing or wipe the identical direct Tunneling mechanism leaks electrons that insulator uses, and thereby electric charge can not be kept for a long time (certainly several milliseconds to perhaps a few hours or a couple of days) on floating boom.For memory application, some people hangs down refresh rate DRAM by using control gate and refresh circuit to come reality to make one, and effective retention time of having improved the direct Tunneling insulator.The others has then revised insulator and/or floating boom, increases by one and leaks and stop the barrier layer, postpones or reduces leakage.Owing to need on floating boom, arrange a control gate or need special CMOS to handle to increase to leak to stop the barrier layer, thereby those methods all can not be used for standard list-many logic CMOS.Second reason that direct Tunneling is not widely used in electronic application is, floating boom usually and nonvolatile memory interrelate, and common optimization of nonvolatile memory is used to store numerical data, the subsidiary situation of one is, no matter nonvolatile memory device is to use FN or direct Tunneling or another mechanism to write or wipe floating boom, its most number average does not allow read and write simultaneously or reads and wipe.Therefore, the cmos circuit designer can not utilize direct Tunneling floating boom circuit usually.
The floating-gate memory device of a kind of and general single polysilicon logic-cmos technology compatibility need be provided, and the CMOS processing that does not need the dual poly control gate and need not improve uses the direct Tunneling method to be used for adding electric charge and/or removing electric charge from it to floating boom simultaneously.The floating-gate memory device that also needs to provide a kind of read and write simultaneously and/or read and wipe is so that use such floating boom circuit in simulation and/or Design of Digital Circuit.
Summary of the invention
The invention provides a kind of semiconductor device, this device uses a floating boom to store analog-and digital-value information, and measure to a few hours with several milliseconds memory time.Electric charge is added into floating boom by the insulator around the direct electron tunnelling and/or removes in floating boom, wherein this insulator usually enough approaches, and makes between insulator voltages is less than semiconductor and insulator and/or also obvious tunnelling can occur during the electron affinity between floating boom and the insulator.Optionally refresh or upgrade institute's canned data.In many application, need not to interrupt the normal circuit operation when refreshing stored information.Can utilize different circuit inputs to implement to the floating boom interpolation or from wherein removing electric charge, with the performance and the response of customization floating-gate device.Need not use control gate in the floating gate structure disclosed herein.
Description of drawings
Those accompanying drawings are all included this specification in and are constituted the part of this specification, and it shows one or more embodiment of the present invention, and are used from explanation principle of the present invention and form of implementation with detailed description one.
Wherein:
Fig. 1 is the side cross-sectional, view according to the dual poly CMOS floating-gate MOS FET of prior art.
The electron energy band figure of Fig. 2 A, 2B and 2C shows difference between the electronics FN tunnelling of passing an insulating barrier and the direct Tunneling.
Fig. 2 D, 2E and 2F are based on the various types of semiconductor storage device device charge decay of the electric charge curve chart to the time.
Fig. 3 A, 3B and 3C are the electron energy band figure of electronics direct Tunneling one thin dielectric layer.
Electrical schematic diagram shown in Fig. 4 A, 4B, 4C and the 4D shows four kinds of basic circuit structures that are used for floating boom charging and/or discharge according to the embodiment of the invention by direct Tunneling one capacitor.
Fig. 5 A, 5B, 5C, 5D, 5E, 5F and 5G are schematic diagram and the corresponding side cross-sectional, view according to several forms in many possibility forms of implementation of the embodiment of the invention one tunnel capacitor.
Electrical schematic diagram shown in Fig. 6 A, 6B, 6C, 6D and the 6E shows the circuit of some embodiment according to the present invention, wherein a pFET read transistor itself be used for carrying out direct Tunneling move charge and/or discharge himself one of floating boom or both.
Electrical schematic diagram shown in Fig. 7 A, 7B, 7C, 7D and the 7E shows the circuit of some embodiment according to the present invention, wherein a nFET read transistor itself be used for carrying out direct Tunneling move charge and/or discharge himself one of floating boom or both.
Electrical schematic diagram shown in Fig. 8 A, 8B, 8C and the 8D shows the some embodiment of the present invention, and wherein one or more MOSFET, capacitor or other insulation devices can be connected to a floating boom.
Fig. 9 is the characteristic semilog diagram of current-voltage (I-V) of Fig. 5 C circuit.
Figure 10 is the vertical view of Fig. 5 D circuit arrangement.
Figure 11 is Fig. 5 D and the characteristic semilog diagram of Figure 10 circuit I-V.
Figure 12 A, 12B and 12C are respectively electrical schematic diagram, side cross-sectional, view and the vertical views of Fig. 6 B circuit arrangement, and this circuit uses a single pMOS tunnel capacitor and one or four ends to read the PNVFG device that pFET forms an embodiment of the invention.
Figure 13 A, 13B and 13C are respectively electrical schematic diagram, side cross-sectional, view and the vertical views of Fig. 4 C circuit arrangement, and this circuit uses and is respectively applied for electron tunneling to floating boom and leave a pMOS of floating boom and a nMOS tunnel capacitor and g four ends and read the PNVFG device that pFET forms an another embodiment of the present invention.
Figure 14 A, 14B and 14C are respectively electrical schematic diagram, side cross-sectional, view and the vertical views of Fig. 7 C circuit arrangement, and this circuit uses a single pMOS tunnel capacitor and one or four ends to read the PNVFG device that nFET forms one embodiment of the invention.
Figure 15 A, 15B and 15C are respectively electrical schematic diagram, side cross-sectional, view and the vertical views of a circuit arrangement, and this circuit use one is read PNVFG device that pFET form one embodiment of the invention via channel hot electron injection (CHEI) to four ends that floating boom adds electronics from the single pMOS tunnel capacitor and that floating boom removes electronics.
Figure 16 A, 16B and 16C are respectively electrical schematic diagram, side cross-sectional, view and the vertical views of a circuit arrangement, and this circuit use one is read PNVFG device that pFET form one embodiment of the invention via ionization by collision hot electron injection (IHEI) to four ends that floating boom adds electronics from the single pMOS tunnel capacitor and that floating boom removes electronics.
Figure 17 A and 17B are respectively the electrical schematic diagrams that the electrical schematic diagram and according to one embodiment of the invention one PNVFG voltage variable capacitor is used to upgrade the refresh circuit of capacitor floating gate charge.
Embodiment
In this article, various embodiments of the present invention are to set forth under the linguistic context of pseudo-nonvolatile direct-tunneling floating-gate semiconductor device.It will be understood by one of ordinary skill in the art that the following content that elaborates of the present invention only is used to describe purpose and does not desire to be limited by any way.The those skilled in the art who benefits from this disclosure can easily expect other embodiment of the present invention.To elaborate the embodiment of the invention that is illustrated as in the accompanying drawing now.To use the identical identical or similar portions of reference marker representative at whole accompanying drawing and in hereinafter elaborating.
For the purpose of clear, do not show and set forth all conventional features of form of implementation described herein.Certainly, should be appreciated that, in the research and development of any actual form of implementation, must make numerous needles to the decision-making of form of implementation to reach researcher's specific objective, for example, meet and application and commercial relative restrictions condition, and those specific objectives will be different different because of form of implementation difference and researcher.And, should be appreciated that this research work may be complicated and consuming time, but remain a conventional design task for the those skilled in the art who benefits from this disclosure.
The invention relates to a kind of pseudo-nonvolatile semiconductor device that is used on a floating boom, storing the analog or digital value information with form of electrical charges.According to the present invention, use direct Tunneling (opposite with Fu Le-Nuo Dehan tunnelling) is transferred to floating boom with electric charge and/or it is removed from floating boom.For direct Tunneling occurring, insulator must be enough thin, so that expect that some electric charge can leak from this floating boom subsequently, therefore expected information can intactly not keep above sometime (common several milliseconds to a few hours, but not the several years is to many decades) and need to upgrade, rewrite or refresh in the phase in due course.
Although this device is not suitable for the long-term no electric archives storage of numeral and/or analog information, but for some application suitable and even highly desirable, especially preferably avoid using the outer high voltage of chip or avoid using charge pump circuit on chip, to form high voltage (required usually) or preferably avoid the application of (as using Fu Le-Nuo Dehan tunnelling to write floating boom and hot electron injects the floating-gate device of it being wiped (or opposite) usually) of asymmetric writing speed as Fu Le-Nuo Dehan tunnelling.And, this device for need than traditional capacitor circuit can provide for the application of long charge storage of charge storage time can be suitable and even highly desirable, in such is used, be used for being measured to several milliseconds the leakage current that the pn of capacitor charge or discharge knot occurs the retention time to count microsecond, but in such is used, neither need also unnecessary information stores several months or several years.
For example, the present invention can be used for storing the analog to digital converter (ADC) of periodic calibration and the calibration information of digital to analog converter (DAC), and wherein the present invention is applicable to period inner storag information between those calibration event.The present invention also can be used for: the pseudo-nonvolatile adjustment information that storage is used for the linearisation transfer function, storage is used for the length of delay of continuous variable delay circuit, adjust the capacitance of floating boom trimmed variable capacitors, adjust the output current of adjustable current source, adjust the output voltage of variable voltage source, the input offset of fine setting operation transconductance amplifier (OTA), the centre frequency of fine setting voltage controlled oscillator (VCO), the image of fine adjustment signal blender suppresses response and similar application.
Following characteristics make the present invention become a general-purpose device that does not exist as yet up to now: only need use 10 dust to 50 dust SiO commonly used in pFET-and/or nFET-type structure and the present CMOS processing
2Gate oxide need not to use 70 dust to 200 dust oxides in the traditional, nonvolatile memories promptly can make up the present invention in standard logic CMOS structure as a gate insulator, and do not need high voltage, can store analog or digital information, can realize symmetrical renewal speed, have than retention time of the long some orders of magnitude of traditional capacitor structure that use semiconductor (that is pn knot) to write and wipe etc.
When not needing long-term nonvolatile storage (several years or many decades), maybe when expectation subnormal voltage operation and standard CMOS processing and design rule, those structures, method and mechanism that this paper set forth can provide remarkable advantage.Specific, write with the traditional capacitor structure of wiping and compare with using semiconductor (that is pn knot), it can keep the longer time with simulation and/or digital-valued information, but, not resembling the traditional, nonvolatile memories part, it uses the low-voltage direct Tunneling with floating boom charging and/or discharge.Since direct Tunneling do not need high insulator voltages or high electronic energy to or from the floating boom transmission electronic, so the speed of insulator damage allows updated stored device more continually much smaller than traditional NVM.In fact, the present invention can store analog-and digital-value information with the maintenance feature between traditional capacitor structure and traditional NVW, with the retention time longer but shorter than NVM than traditional capacitor, the every other advantage that keeps the traditional capacitor structure simultaneously, for example, working voltage is low and the method for renewal stored information is easy.
Subnormal voltage operation will to the demand of additional power supply level or chip power lotus pump reduce to minimum or even eliminate fully, thereby can reduce chip lead, save chip area and reduce power consumption.
Subnormal voltage operation can avoid producing hot hole and/or hot electron, and this is the inevitable side effect of high voltage floating boom charging/discharging method and can destroys insulating barrier and thereby cause the insulating barrier wearing and tearing also finally to cause chip failure.
Subnormal voltage operation does not help avoid in originally not needing to use the advanced technologies of big semiconductor junction and thick gate insulator and uses big semiconductor junction and thick gate insulator.
Because can use the low-voltage direct Tunneling of same mechanism charges to a floating boom and discharges, control and implement all common irrealizable mode symmetries of high-voltage charge and charging method more of those chargings and the required circuit of discharge operation and running time, this causes littler with renewal speed symmetry and refresh circuit is the more economical form of implementation of feature.
Although memory technology set forth in the present invention is not a long-term nonvolatile, its required refreshing frequency is than the little many orders of magnitude of the necessary renewal frequency of traditional electrical capacitive memory technology, and thereby system's operation at its place interfered still less.
Different with traditional floating-gate device, the low-voltage floating-gate device of being set forth among the present invention can be adjusted the electric charge on its floating boom when operation in some big circuit; This adjustment process need not interrupted its signal and be transmitted or readability.Therefore, the low-voltage floating-gate device also can be used for can not interrupting in the application of all circuit functions recalibrations.
The application that other the present invention are suitable for includes, but is not limited to: the calibration information of storage ADC and DAC; Storage is used for the simulation refinement information of linearisation transfer function; Storage is used for the length of delay of continuous variable delay circuit; Adjust the capacitance of floating boom trimmed variable capacitors; Adjust the output current value of adjustable current source; Adjust the output voltage values of variable voltage source; Reach other application that the those skilled in the art is understood this moment.
In some applications, will can not to cause inconvenience and increase refresh circuit will be to be to obtain the receivable compromise proposal of advantage of the present invention to the shortcoming of memory time shorter (when comparing with traditional NVM).In other application of regularly recalibrating with compensates, mains voltage variations or other circuit non-ideal conditions, the invention provides than based on the lower calibration intervals of the conventional calibration structure frequency of electric capacity, reduce power consumption thus and thereby reduce calibration loop the entire circuit Effect on Performance.
The present invention compares with EEPROM or Flash type nonvolatile memory can provide several advantages.Because use the low writing voltage that can not produce the hot carrier of damaging insulator, wearing and tearing reduce.The present invention can be used in single polysilicon logic CMOS technology and only use pFET and the used structure fabrication of nFET form.Simulation and digital value all can be stored.Write and the erasing voltage requirement reduces and to mean and can use less chip power lotus pump maybe it can be omitted fully.Can simplify charging and discharge circuit and make its symmetry.
According to the present invention, four preconditions are crucial.At first, use low-voltage direct Tunneling is charged floating boom (adding electronics to it) and/or is used for discharge (removing electronics from it).The second, circuit design only need to revise slightly can with floating boom pFET and/or floating boom nFET cooperating equally well.The 3rd, can store the analogue value or digital-valued information.The 4th, accept institute's data on file and only retain several milliseconds to a few hours and for keeping the compromise proposal of uncertain necessary periodic refresh.Therefore, it is non-volatile this memory function to be called " puppet ".
In specification of the present invention, institute's drawings attached is all based on the present CMOS logic process that uses p-type substrate.It will be understood by one of ordinary skill in the art that those conduction forms can be reverse and can use a n-type substrate, wherein the n-trap becomes p-trap and similar trap.It should also be apparent to those skilled in the art that to use to have n-type trap and both insulated substrates of p-type trap, or the substrate that constitutes by the material beyond the silica removal.P-(and n-) substrate uses p-type (with the n-type) dopant with about 10
15To about 10
18The amount of dopant/cubic centimeter is mixed.P-(and n-) trap with corresponding dopant with about 10
15To about 10
18The amount of dopant/cubic centimeter is mixed.P+ and n+ zone with corresponding dopant with about 10
18To about 10
21The amount of dopant/cubic centimeter is mixed.The technology that is used to make structure described herein all can be buied from the commercial producer place of production logic CMOS integrated circuit and be known for the those skilled in the art.Conducting element can be by metal, silicide or heavy doping (about 10
21Dopant/cubic centimeter) polysilicon (polycrystalline silicon) (being referred to herein as polysilicon (poly-or polysilicon)) constitutes.Although expection is with silicon dioxide (SiO
2) as altogether with dielectric come as insulator with those floating booms of the present invention insulated from each other and with substrate and trap insulation thereof, but can use other insulating materials separately maybe with this this insulating material and SiO
2Use together.Insulator can be formed by following material: silicon dioxide, nitride-oxide, nitride, oxide/nitride composition, titanium dioxide, tantalum oxide, zirconia, hafnium oxide, lanthana (or oxide of any lanthanide series), titanium silicate, silicic acid tantalum, zirconium silicate, hafnium silicate and lanthanum silicate (or silicate of any lanthanide series), above-mentioned dielectric any combination or those skilled in the art are known other insulating material that maybe may know.For the insulator that forms by silicon dioxide, be generally used for non-volatile memories between about 70 dusts to the thickness of about 200 dusts, and be generally used for the pseudo-nonvolatile storage between about 10 dusts to the thickness of about 50 dusts.Other insulating materials will have different one-tenth-value thickness 1/10s.Therefore, too complicated for avoiding this disclosure, will repeat no more extra manufacturing details except that thinking to this paper the important manufacturing link of the present invention.
Fig. 2 D, 2E and 2F are the curve chart of the charge decay of various semiconductor storage units based on electric charge to the time.Those curve charts show the greatest differences of the retention time of various types of semiconductor storage.The shape of attenuation curve is all similar under each situation; But three the time constant of each bar is significantly different in the curve.For the non-floating gate capacitance memory element of prior art (Fig. 2 D, curve 34) that has based on the charge/discharge circuit of pn-knot, the electric charge of capacitor leaks rapid relatively, and the common every several microseconds of those devices just need refresh to several milliseconds.An example of prior art capacitance stores is the dynamic random access memory of knowing (DRAM), wherein uses the semiconductor knot with a capacitor charge/discharge.For prior art nonvolatile semiconductor memory member (Fig. 2 F, curve 38), charge storage cell and active semi-conductor material insulation and too thick so that tangible direct Tunneling can not occur and leak around the insulation dielectric of charge storage cell; Therefore, it is extremely slow that electric charge leaks, but and usually guarantee information keep many decades and in fact can be longer.For the present invention (Fig. 2 E, curve 36), the retention time is extreme middle between these two; Electric charge leaks enough slowly to can making several milliseconds of information maintenances to a few hours, but it must refresh or upgrade and can use for a long time.
Fig. 3 A, 3B and 3C are the electron energy band figure of electronics direct Tunneling one thin dielectric layer 40, show the operation of a direct tunnelling system under three kinds of different voltage conditions.Under each situation, the X-axle is that physical distance and Y-axle are voltage and electron energy; Voltage is directly proportional with electron energy and proportionality constant is unit charge e
-Tunnelling is basic quantum-mechanical phenomenon, and wherein electronics has the probability that certain passes through a physical insulation barrier layer according to electronic wave character, even needs enough to cross according to its particle properties acquisition the energy of this barrier layer.Along with barrier layer thickness reduces, the probability of electron tunneling is index to be increased.The barrier layer is one to place the insulating barrier between floating boom and the silicon face in this article, and it is enough thin in the present invention, millisecond to second markers on the probability of electron tunneling quite big.In Fig. 3 A, the voltage potential at insulating barrier two ends is identical; Therefore, although on each direction, all there is the tunnelling electronics to flow, par equate and direction opposite, cancel out each other and do not have net current.In Fig. 3 B, floating boom 42 is in a voltage potential lower than silicon face 44, and it is big therefore to flow to the rightabout electric current of current ratio of silicon face 44 from grid 42; Therefore there is a clean electron stream that electronics is shifted to silicon face 44 from floating boom 42.In Fig. 3 C, this voltage potential situation is opposite, therefore has one from the clean electron stream of silicon face 44 to floating boom 42 transfers.
Fig. 4 A, 4B, 4C and 4D are electrical schematic diagrams, and it shows according to the embodiment of the invention and is used for four kinds of basic circuits of floating boom 46 charge/discharges are constructed by the direct Tunneling in the capacitor.In Fig. 4 A, 4B, 4C and 4D, a tunnelling voltage V is arranged all
TUN, it must both can be used as positive voltage+V
TNNAlso can be used as negative voltage-V
TUN, simultaneously+V
TUNWith-V
TUNUsually with floating boom voltage V
Fg46 is the center symmetry, but does not require+V
TUNWith-V
TUNMust be with V
FgBe the center symmetry.And, the two-way direct Tunneling that although Fig. 4 is A, 4B, 4C and 4D all show one embodiment of the invention, but the those skilled in the art can understand, the combination that also can use direct Tunneling and traditional hot electronics to inject, and wherein tunnelling removes electronics and injects to floating boom and add electronics from floating boom.In the circuit of Fig. 4 A and 4B, a single tunnel capacitor 48 is connected to can be at+V
TUNAnd V
TUNBetween the voltage source 50 that switches, simultaneously, be+V according to selected
TUNOr V
TUN, tunnelling occurs on the either direction between voltage source 50 and the floating boom 46; Yet, in Fig. 4 C and 4D, two tunnel capacitor 52 and 54 being arranged, one of them capacitor is connected to when electron tunneling leaves floating boom 46+V
TUNAnd another is connected to-V when electron tunneling is to floating boom 46
TUNIn the device shown in Fig. 4 A and the 4C, reading transistor is a pFET (p-slot field-effect transistor), regards it as a four-terminal device, and its trap contact 56 is the 4th end (other ends is source electrode, drain electrode and floating boom); Yet in device shown in Fig. 4 B and the 4D, reading transistor is a nFET (n-slot field-effect transistor), regards it as a four-terminal device equally, and its trap contact 58 is the 4th end (other ends is source electrode, drain electrode and floating boom).Under those situations, (be generally silicon dioxide in CMOS technology, that SiO2) makes is enough thick, occurs tunnelling in the transistor hardly so that read under the normal circuit working voltage will to read transistorized gate insulation layer usually.It is not to be applicable to all embodiment disclosed herein that constraints is planted in the back.
Fig. 5 A, 5B, 5C, 5D, 5E, 5F and 5G be according to the embodiment of the invention one tunnel capacitor many may forms of implementation in a few side view in transverse section.The those skilled in the art will understand many other embodiment this moment.
Now referring to Fig. 5 A, under situation shown in except that Fig. 5 F all, this tunnel capacitor form of implementation comprises one or two four end MOSFET 60, and two or three ends in four ends of each MOSFET (source electrode 62, drain electrode 64 and some combination of trap 66) are usually by metal interconnected 68 short circuits be in the same place (this short circuit function also can be implemented by other conducting elements that the those skilled in the art understands).Those short circuits zone together constitutes a pole plate of capacitor, and floating boom 70 constitutes another pole plate.Shown in all situations under, substrate 72 is p-section bar material, and it has p+ (62,64) and n+ (66) resistance contact and vertical metal path 74,76,78, those metal pathway lead to metal interconnected 68 by interlayer dielectric layer (ILD) 80 materials.In fact, metal pathway may penetrate additional ILD material layer, and additional metal layer also can insert between those ILD layers, but for avoiding too complicated not shown those extra plays of this disclosure.The top of this substrate is the different insulating barrier of thickness 82, and it usually but be not to be necessary for silicon dioxide; Insulating barrier (is called as ' gate oxide ') as thin as a wafer in the zone 84 that produces MOSFET, (and be called as that ' field oxide ' or ' shallow trench isolation ') is to slacken the coupling between MOSFET to the degree that can ignore coupling effect and the zone between MOSFET is 86 thicker.In the MOSFET gate region, the polysilicon layer on thin gate oxide 84 tops forms floating boom 70.
Fig. 5 A shows as tunnel capacitor and is formed at single pFET 60 in the n-type trap 88.The equivalent schematic of device 60 is shown in 61 places.
Fig. 5 B shows as tunnel capacitor 90 and is made in single nFET in the p-type substrate 92.Electron tunneling appears between shorted source/drain implant and the floating boom 98.The short circuit n+ source electrode 94 of nFET and drain electrode 96 can not be pulled down to current potential and be lower than p-substrate 92, otherwise the pn-junction diode that forms between this substrate and the source/drain diffusion is with forward bias and conduction.The equivalent schematic of device 90 is shown in 91 places.
Fig. 5 C shows the single nFET as a tunnel capacitor 100, and it is formed in the p-type trap 102 herein, and p-type trap 102 is sealed in the n-type trap 104 fully, so that p-type 102 traps and main p-type substrate 106 electric insulations.The equivalent schematic of device 100 is shown in 101 places.In this form of implementation, can source electrode 108 and drain electrode 110 be pulled down to by suitable bias voltage insulation n-trap 104 (circuit closing contacts 112, path 114 and n+ zones 116) and p-trap 102 (circuit closing contacts 118, path 120 and p+ zone 122) and be lower than substrate voltage so that there is not diode junction to conduct electricity.
Fig. 5 D show to use the circuit structure 124 of two floating gate tunneling capacitors 126,128 in parallel (one is that pFET 128 and one are nFET 126), capacitor 126,128 is formed in the p-type trap 130, and p-type trap 130 is sealed in the n-type trap 132 fully so that p-type trap 130 and main p-type substrate 134 electric insulations; This combination is still as a capacitor, and the single MOSFET device that plays this effect has better capacitance-voltage characteristics.The equivalent schematic of device 124 is shown in 125 places.This structure is called dark n-trap or " DNW ".Floating boom 127 is that a part and the floating boom 129 of nFET 126 is parts of pFET 128.Floating boom 127 and 129 is coupled as shown in signal Figure 125.N+ zone 131 and 133 forms drain electrode and the source electrode of nFET 126 respectively.P+ zone 135 and 137 forms source electrode and the drain electrode of pFET 128 respectively. Drain electrode 131 and 137 is coupled to interconnection 148 with path 139,141 respectively.Trap contact 143,145 is coupled respectively to path 147,149.Interconnection 151 coupling source electrodes 133 and 135.
Fig. 5 E show to use the circuit form of implementation 136 of two floating gate tunneling capacitors 138,140 in parallel (one is that pFET 138 and one are nFET 140), in nFET 140 is formed at p-substrate 142 and in the nonisulated p-type well area 130, it is similar to the circuit form of implementation shown in Fig. 5 D; And first pole plate the 144, the 146th of independent tunnel capacitor, the branch beginning consistent, rather than the single pole plate 148 in the described device 124 of Fig. 5 D with Fig. 4 C and 4D.The equivalent schematic of device 136 is shown in 137 places.
Fig. 5 F shows a kind of nMOS ' bowl-type capacitor ' 150, says not to be a nFET in this device strictness, because it is without any source electrode and drain diffusion.The equivalent schematic of device 150 is shown in 153 places.This structure can manufacture in the n-trap material under thin gate oxide 152 and be added with the additional dopant atom, all structures of Fig. 5 A, 5B, 5C, 5D, 5E, 5F and 5G also can so be made, but for avoiding too complicated not shown this extra play of this disclosure.A multi-crystal silicon floating bar 154, a trap contact 156 that is coupled to the n+ zone 160 in the n-trap 162 via path 158 are arranged in the device 150 of Fig. 5 F.
The device 164 that shows among Fig. 5 G is similar with device shown in Fig. 5 E.Tunnel capacitor 166,168 parallel connections, one is that pFET 166 and one are nFET 168, but nFET 168 is formed in the p-type trap 170 herein, and p-type trap 170 is sealed in the n-type trap 172 fully so that p-type trap 170 and main p-type substrate 174 electric insulations.The equivalent schematic of device 164 is shown in 165 places.In this form of implementation, can be by suitable bias voltage insulation n-trap 172 (circuit closing contacts 176, path 178 and n+ zones 180) and p-trap 170 with the source electrode of nFET 168 with drain and 161,163 be pulled down to and be lower than substrate voltage, so that do not have the diode junction conduction, in the device 100 as Fig. 5 C.
Fig. 6 A, 6B, 6C, 6D and 6E are the electrical schematic diagrams of display circuit, wherein according to one embodiment of the invention, a pFET reads transistor 182 and self is used for implementing the direct Tunneling operation and promptly adds electronics and/or remove one of electric charge or both from it to himself floating boom.Suppose that this reads pFET and have a gate oxide, this gate oxide is enough thin, the direct electron tunnelling shown in Fig. 3 B and the 3C can occur.In the circuit shown in Fig. 6 A, 6B and the 6C, tunnel capacitor 184 is used for one of two electron transfer directions (add or remove), and reads transistor self and be used for another electron transfer direction.In circuit shown in Fig. 6 D and the 6E, do not use tunnel capacitor, and read electric crystal 182 and self be used for two electron transfer directions.In the circuit shown in Fig. 6 A and the 6C, this tunnel capacitor is connected to-V
TUNThis tunnel capacitor is used for adding electronics to floating boom 186, and removing in circuit shown in Fig. 6 A of electronics is by to the trap 188 of reading pFET and be by to reading pFET trap 190 and/or source electrode 192 applies+V in circuit shown in Fig. 6 C
TUNRealize.Voltage among Fig. 6 C on trap 190 and the source electrode 192 is similar usually, but it is also nonessential identical; Therefore, it is designated+V
TUN1With+V
TUN2Also it should be noted that voltage+V
TUNWith-V
TUNNeedn't be the center symmetry also with floating boom voltage.The antithesis form of implementation of Fig. 6 B displayed map 6A form of implementation, wherein in the circuit shown in Fig. 6 B, adding electronics to floating boom 186 is to be connected to-V by the drain electrode 194 that will read pFET
TUNRealize, and to remove electronics be by tunnel capacitor 184 is connected to+V
TUNRealize.In the circuit shown in Fig. 6 D and the 6E, the drain electrode 196 of reading pFET is connected to-V
TUNBe used for adding electronics to floating boom 186; The trap 198 of reading pFET in both cases all is connected to+V
TUNTo remove electronics.In circuit shown in Fig. 6 D, the source electrode 200 of reading pFET also is connected to+V
TUNAnd can be connected collaborative with trap or not use and replace the trap connection and remove electronics from floating boom 186.Equally, the voltage in Fig. 6 D on trap 198 and the source electrode 200 is similar usually, but it is also nonessential identical, therefore it is designated+V
TUN1With+V
TUN2Tunnel capacitor can be shown in Fig. 5 A, 5B, 5C, 5D, 5E, 5F and the 5G any and other structures that the those skilled in the art can know now in the structure.
Fig. 7 A, 7B, 7C, 7D and 7E are circuit diagrams, in those circuit, according to the embodiment of the invention, a nFET reads transistor 210 and self is used for implementing adding electronics and/or removing a kind of of these two kinds of direct Tunneling operations of electronics or both from floating boom 212 to himself floating boom 212.Suppose to read nFET 210 and have a gate oxide, this gate oxide is enough thin, the tunnelling of direct electron shown in Fig. 3 can occur.Fig. 7 A, 7B, 7C, 7D and 7E are the antithesis of Fig. 6 A, 6B, 6C, 6D and 6E, wherein use the pFET 182 in nFET 210 alternate figures 6 among Fig. 7, and according to circumstances the electron stream direction are reversed.In the circuit shown in 7A, 7B and the 7C, tunnel capacitor 214 is used for one of two electron transfer directions (add or remove), and reads transistor 210 and self be used for another electron transfer direction.In the circuit shown in Fig. 7 D and the 7E, do not use tunnel capacitor, read transistor 210 and self be used for two electron transfer directions.In the circuit shown in Fig. 7 A and the 7C, tunnel capacitor 214 is connected to+V
TUNThis tunnel capacitor is used for removing electronics from floating boom, and to add electronics to floating boom 212 be by to the trap 216 of reading nFET and be by applying-V to the trap 216 of reading nFET and/or source electrode 218 in Fig. 7 C in Fig. 7 A
TUNFinish.In Fig. 7 C, the voltage on trap 216 and the source electrode 218 is similar usually, but it needn't be identical; Therefore it is labeled as-V
TUN1With-V
TUN2The circuit of Fig. 7 B show Fig. 7 A form of implementation the antithesis form of implementation, wherein remove electronics and be connected to+V by the drain electrode 220 that will read nFET
TUNFinish, and add electronics by tunnel capacitor 214 is connected to-V
TUNFinish.In the circuit of Fig. 7 D and 7E, the drain electrode 220 of reading nFET is connected to+V
TUNAnd be used for removing electronics from floating boom 212; In both cases, the trap 216 of reading nFET all is connected to-V
TUNTo add electronics.In the circuit of Fig. 7 D, the source electrode 218 of reading nFET also is connected to-V
TUNAnd be connected 216 collaborative or do not use trap to connect and add electronics with trap to floating boom 212.Equally, the voltage in Fig. 7 D on trap 216 and the source electrode 218 is similar usually, but also nonessential identical, and therefore is designated-V
TUN1With-V
TUN2Tunnel capacitor 214 can be shown in Fig. 5 A, 5B, 5C, 5D, 5E, 5F and the 5G any and other structures that the those skilled in the art can know now in the structure.
Fig. 8 A, 8B, 8C and 8D are the electrical schematic diagrams that shows the embodiment of the invention, wherein one or more read MOSFET-222-1 ..., 222-n (and any capacitor embodiment that has set forth) can be connected to single floating boom or floating node 224.Unique herein restriction is that the shared electric contact of those a plurality of floating booms can not be connected to any insulation not as tunneling oxide effective circuit element.Be suitable for adding electronics and or can be any in the said elements from its circuit element that removes electronics to those electric shared floating booms.To the combination of the floating boom of the floating boom of pFET and nFET without limits: Fig. 8 A shows a plurality of pFET, Fig. 8 B shows a plurality of nFET and a plurality of pFET combination, Fig. 8 C shows a plurality of nFET, and figure FIG.8D shows that a plurality of pFET, a plurality of nFET and one or more are connected to the coupling capacitor 226 of floating boom or floating node 224.
Fig. 9 is Fig. 5 C circuit characteristic semilog diagram of I-V of (comprises the tunnel capacitor of a nFET 100 in an insulation p-trap 102), and wherein X-axis is represented the voltage at insulator 228 two ends, and Y-axis is represented the absolute value by the tunnelling current of insulator 228.Two pole plates of tunnel capacitor are (1) floating booms 230; And (2) insulation p-trap 102, wherein the drain electrode 108 of nFET is shorted to insulation p-trap 102 (promptly keeping identical current potential with insulation p-trap 102) with source electrode 110 ends.When insulator voltages was center increase or reduction with zero, tunnelling current can increase many orders of magnitude.The zone (that is, gate voltage＜p-trap voltage) on zero left side is the place of accumulating in p-type trap, that is mobile hole is attracted and formation one hole enriched layer under gate insulator 228 by electronegative grid 230.The zone (that is, gate voltage＞p-trap voltage) on zero the right is the place that counter-rotating takes place in p-trap 102, that is mobile electron is by 230 attractions of positively charged grid and form an electronics enriched layer under gate insulator 228.For this circuit, it is quite asymmetric that holding of tunnelling current involved the counter-rotating effect, that is (for example), and the tunnelling current of the tunnelling current during 2V during with-2V is obviously different.So draw according to the curve of analog computation and the curve of under laboratory condition, measuring near not distinguishing consequently whether it separates; Therefore, the graphical representation of Fig. 9 both.
Figure 10 is the vertical view that Fig. 5 D tunnel capacitor 124 is arranged.With in an insulation p-trap 102, comprising that the device 100 of a single nFET is different shown in Fig. 5 C, Fig. 5 D comprise the nFET 126 that is configured in the insulation p-trap 130 and pFET 128 the two, two FET 126,128 shared single shared floating boom 127/129 (pole plate of tunnel capacitor) and shared shared tunnelling conductors 131 (another pole plate of tunnel capacitor).Two pole plates of tunnel capacitor are: the floating boom 127 and 129 of (1) short circuit, and for n-type and p-type MOSFET, it is respectively Doped n-type and p-type usually; And (2) insulation p-trap 130, wherein the source terminal 131 of nFET is shorted to p-trap 130 by conductor 244, and pFET source terminal 137 is shorted to p-trap 130 owing to forming p-trap (p+ is in the p-trap) with the resistance contact.Because floating boom nFET or pFET raceway groove all have conductivity for hundreds of millivolts of voltages leaving on Figure 11 curve on zero the either direction, therefore the drain electrode end 133 and 135 of butt joint and short circuit (using silicide in one embodiment) also is on the current potential identical with insulate n-trap 132 and p-trap 130 between nFET126 and pFET 128.Many other similar arrangements forms of implementation also can be arranged, but too complicated and not shown for fear of this disclosure, for example, electricity is isolated nFET and pFET drain electrode end 133,135; Make nFET contact a conductor and short them to p-trap 130 and source terminal 131,137 with pFET drain electrode end 133,135; With nFET and/or pFET source electrode 131,137 and/or drain and 133,135 be connected on the different conductor of those trap ends; Or other layouts of knowing now of those skilled in the art.
Figure 11 (comparing with Fig. 9) is Fig. 5 D and the characteristic semilogarithmic plot of Figure 10 circuit I-V.The X-axle is represented the voltage at insulator two ends, and the Y-axle is represented the absolute value by the tunnelling current of insulator.Tunnelling current increases many orders of magnitude when insulator voltages is center increase or reduction with zero.The zone (that is, gate voltage＜p-trap voltage) on zero left side is the situation when occurring accumulating in p-type trap, that is mobile hole is attracted by electronegative grid and form a hole enriched layer under gate insulator.The zone (that is, gate voltage＞p-trap voltage) on zero the right is the situation when counter-rotating occurring in the p-trap, that is mobile electron is by 230 attractions of positively charged grid and form an electronics enriched layer under gate insulator.Because the circuit structure symmetry of Figure 10, MOSFET has a p-doped gate and another has a n-doped gate simultaneously, and the tunnelling current of Figure 11 is the center symmetry with zero volt also to the curve chart of insulator voltages.Because this intrinsic symmetry (symmetry of Figure 11 and the dissymmetry ratio of Fig. 9 are), it is an improvement that the structure that it has been generally acknowledged that Fig. 5 D device 124 is compared with the device 100 of Fig. 5 C, needs an extra transistor of use and extra silicon crystal grain district although this improves.In Fig. 9, like this near consequently not distinguishing whether it separates drafting according to the curve of analog computation and the curve of under laboratory condition, measuring; Therefore, the graphical representation of Figure 11 both.
For all features of clearer demonstration and entity, Figure 12 A, 12B, 12C; 13A, 13B, 13C; 14A, 14B, 14C; 15A, 15B, 15C; All amplify with the layout shown in 16A, 16B, the 16C and reset.Those are not the actual arrangement of practical devices, and practical devices should be with quite compact arranged in form.And the cross section of some device on drawing is up and down but not lateral alignment, so do not show its All Ranges.
Figure 12 A, 12B and 12C are respectively electrical schematic diagram, side cross-sectional, view and the vertical views of implementing the circuit arrangement of Fig. 6 B structure according to one embodiment of the invention, and this structure comprises that a pFET tunnel capacitor 260 and four ends read pFET262 and form a PNVFG charge storage device.The source electrode 264 of pFET tunnel capacitor 260, drain electrode 266 and n-trap 268 equal short circuits constitute a pole plate of this tunnel capacitor together; Its floating boom 270 constitutes another pole plate.Two transistors 260,262 all use enough thin gate insulator and oxide, to allow to take place the direct electron tunnelling.Be pulled down to far below floating boom voltage so that electron tunneling to floating boom 270 by the drain voltage that will read pFET electronics is added into floating boom 270.Rise to by n-trap/drain pole tension (at node 272 places) and to leave floating boom 270 far above floating boom voltage so that electron tunneling the floating boom 270 of electronics from pFET removed the pFET tunnel capacitor.Reading pFET 262 has a source electrode 274, drain electrode 276, trap contact 278 and is coupled to floating boom or node 270.As mentioned above, floating boom 270 is by insulator 82 and substrate (p-) 280 and 282 insulation of n-trap.
Figure 13 A, 13B and 13C are respectively electrical schematic diagram, side cross-sectional, view and the vertical views of implementing the circuit arrangement of Fig. 4 C basic structure according to another embodiment of the present invention, and this structure is used a pFET tunnel capacitor 286, a nFET tunnel capacitor 288 and one or four ends to read pFET 290 and formed a PNVFG charge storage device.The source electrode 292 of pFET tunnel capacitor 286 and drain electrode 294 short circuits constitute a pole plate of this tunnel capacitor together; Floating boom or floating node 296 constitute another pole plate.Its n-trap 295 is drawn separately, and is not shorted to source electrode 292 and drains 294 shared common points.The source electrode 298 of nFET tunnel capacitor 288, drain electrode 300 and trap 302 short circuits constitute a pole plate of this tunnel capacitor together; Floating boom 296 constitutes another pole plate.Two tunnel capacitor are all used enough thin gate insulator 304,306 so that allow to take place the direct electron tunnelling.Wherein provide one to be similar to four ends shown in Figure 12 A, 12B and the 12C and to read pFET 290, but it does not implement the tunnelling function in this embodiment, this is because its gate insulator 308 is made thicklyer than the insulator 304,306 that is used for tunnel capacitor, so tunnelling or leakage that occur or that pass gate insulator 308 are enough to ignore in the gate insulator 308.By apply a tunnelling voltage that is lower than floating boom voltage to the shorted source 292 of pFET tunnel capacitor 286 and drain electrode 294 ends, make electron tunneling gate insulator 304 to floating boom 296, electronics is added into floating boom 296.N-trap 295 can be subjected to bias voltage as shorted drain 294 and source electrode 292 ends, or it can keep an earthing potential or be higher than earthing potential.Trap 295 remained on a fixed potential but not short them to drain electrode 294 and source electrode 292 ends, can allow the drain electrode 294 of pFET tunnel capacitor and source electrode 292 ends are biased into and be lower than earthing potential, and need not connect p-substrate-to-parasitic pn-junction diode of n-trap.By apply a tunnelling voltage that is higher than floating boom voltage to the shorted source 298 of nFET tunnel capacitor 288, drain electrode 300 and n-trap 302, make electron tunneling gate insulator 306 leave floating boom 296, electronics is removed from floating boom 296.Reading pFET 290 has one source pole 301, drain electrode 303 and trap contact 305 and this and reads pFET and be arranged in the n-trap 307.
Figure 14 A, 14B and 14C are respectively layout electrical schematic diagram, lateral cross-sectional view and the vertical views of implementing a circuit 320 of Fig. 7 C circuit according to one embodiment of the invention, this circuit comprises that a pFET tunnel capacitor 322 and one or four ends read nFET 324, forms a PNVFG charge storage device.Read nFET 324 and be configured in the insulation p-trap 326 that is arranged in a n-trap 328, and therefore this circuit must be made in a CMOS technology that allows insulation p-trap to exist.Two transistors all use the enough thin gate insulator 330,332 that consequently can allow to take place the direct electron tunnelling.Source electrode 336 by will reading nFET and/or p-trap 338 voltages are pulled down to far below floating boom voltage so that electron tunneling to floating boom 334 electronics are added into floating boom 334.Rise to by short circuit n-trap, source electrode and drain voltage and to leave floating boom 334 far above floating boom voltage so that electron tunneling electronics is removed from floating boom 334 the pFET tunnel capacitor.Reading transistor 324 has one and is applied with V
DDN+ drain contact 325, one be applied with V
INJN+ source contact 327, one be applied with V
WELLP+ insulation p-trap contact 329 and one be applied with V
ODOr the dark n-trap of the n+ of ground connection contact 331.
Figure 15 A, 15B and 15C are respectively electrical schematic diagram, side cross-sectional, view and the vertical views according to the layout of one embodiment of the invention one circuit 340, and circuit 340 comprises that a pFET tunnel capacitor 342 and one four end read-inject nFET 344 and form a PNVFG charge storage device.PFET tunnel capacitor 342 is used enough thin and the gate insulator 346 of permission generation direct electron tunnelling.Owing to read and inject nFET344 and use the gate insulator 348 make enough thickly, so it can hold (accommodate) channel hot electron and injects (CHEI) required voltage and can not cause insulator damage.Compare with the circuit of Figure 14, the circuit of Figure 15 has and is configured in a substrate but not reads nFET in the insulation p-trap, and uses CHEI but not direct Tunneling is added electronics to floating boom 350.Electronics is added into floating boom 350 in the following manner: the drain voltage that will read nFET is pulled to far above its source voltage, so that it some is in the channel electrons and the collision of semiconductor lattice that drain and be accelerated to the raceway groove depleted region of nFET, upwards scatter to gate insulator, overcome the electron affinity difference between semiconductor and the insulator and enter the conductive strips of insulator thus, and collected (collect) by floating boom 350.Rise to by short circuit n-trap, source electrode and drain voltage (at node 352 places) and to leave floating boom 350 far above floating boom voltage so that electron tunneling electronics is removed from floating boom 350 the pFET tunnel capacitor.There are many other to arrange form of implementation, but, for example, nFET are configured in the insulation p-trap for avoiding this disclosure too complicated not shown; Use the source side hot electron to inject electronics is added into floating boom; Or other layouts that will know now of those skilled in the art.
Figure 16 A, 16B and 16C are respectively electrical schematic diagram, side cross-sectional, view and the vertical views of arranging according to one embodiment of the invention circuit 360, and circuit 360 comprises that a pFET tunnel capacitor 362 and one or four ends read-inject pFET 364 and form a PNVFG charge storage device.PFET tunnel capacitor 362 is used enough thin and the gate insulator 366 of permission generation direct electron tunnelling.Read and inject the enough thick gate insulator 368 of pFET 364 use manufacturings, inject (IHEI) required voltage and do not damage insulator so that it can hold collision-ionization-Re-electronics.With the circuit of Figure 15 relatively, the circuit of Figure 16 uses to be read-injects pFET 364 but not read-injects nFET 344, and use IHEI but not CHEI are to floating boom 368 interpolation electronics.Electronics is by the following floating boom 368 that is added into: the drain voltage that will read pFET is pulled down to far below its source voltage, so that its some channel hole (raceway groove to the depleted region that drains at pFET is accelerated) and the collision of semiconductor lattice, and by means of ionization by collision generation free electron.Those free electrons by identical raceway groove to drain electric quicken away from the drain region and wherein some scattering that makes progress go in the gate insulator, overcome the electron affinity difference between semiconductor and the insulator and enter the conductive strips of insulator thus, and caught by floating boom 368.Leave floating boom 368 and remove electronics in the floating boom 368 by short circuit n-trap, source electrode and the drain voltage of pFET tunnel capacitor being risen to far above floating boom voltage so that electron tunneling at node 370 places.Have many other and arrange form of implementation, but for avoiding this disclosure too complicated not shown, for example, a single thin-oxide pFET not only is used for direct Tunneling but also be used for IHEI; Or other layouts that will know now of one of ordinary skill in the art.
Figure 17 A and 17B are respectively that this charge refresh circuit can be used for upgrading the floating gate charge of voltage variable capacitor according to the electrical schematic diagram of the embodiment of the invention one PNVFG voltage variable capacitor 380 and the electrical schematic diagram of a charge refresh circuit 382.The voltage variable capacitor 380 of Figure 17 A comprises pFET 384,386 and 388.The gate insulator of pFET 384,386 is much thicker than used insulator among the pFET 388, thus wherein occur or by its tunnelling or leak and can ignore.PFET 388 is tunnel capacitor, and the gate oxide that it had is enough thin, to such an extent as to direct electron tunnelling as shown in Figure 3 occurs.From the climax plate 390 of voltage variable capacitor to sole plate 392 measured electric capacity can stored charge quantity changes on the floating boom 394 by adjusting.For adjusting and/or refreshing this amount of charge, the charge refresh circuit 382 of Figure 17 B provides a kind of shorted source to pFET 388, drain electrode and trap to apply the means of tunnelling pulse.This refresh circuit is used for voltage variable capacitor and reference capacitor 396 are compared, and the floating boom 398 of reference capacitor 396 provides a reference voltage V
REF2(being set at the floating boom voltage that equals to wish) sets its capacitance.This is compared as follows described enforcement: at first variable capacitor 380 and reference capacitor 396 are both be charged to reference voltage, V
REF1By integrator 400 in a usual manner with stored charge quantity integration on two capacitors 380,396 and with a reference voltage V of comparator 420
REF3Relatively.If two amount of charge are unequal, then the tunnelling pulse of the output 404 places one suitable polarity of comparator 402 will be applied to shorted source, drain electrode and the trap of tunnel capacitor 388.During refreshing, feedback loop 406 applies those+V
TUNOr-V
TUNStored charge quantity on the floating boom 394 is regulated in the tunnelling pulse of polarity, thereby the value of variable capacitor is set at equals reference capacitor 396.To understand now as the those skilled in the art, and can use similar techniques to come the electric charge on the floating boom in the refresh circuit, for example, variable resistance, variable current source, variable voltage source, variable time delay, simulation and/or digital value memory etc.
Although shown and set forth embodiments of the invention and application, benefit from being understood by those skilled in the art that of this disclosure, the present invention can have than the more modification of above-mentioned modification and not deviate from principle of the present invention herein.Therefore, the present invention only is subject to the spirit of the claim of enclosing.
Claims (77)
1, a kind of pseudo-nonvolatile charge storage device, it comprises:
The semiconductor substrate;
One is arranged in the source area in the described substrate;
One drain region that is arranged in the described substrate and separates with described source area;
One is arranged in the raceway groove between described source area and the described drain region;
One electric charge holding region that separates with described raceway groove; And
One thickness is less than the direct Tunneling dielectric of one Fu Le-Nuo Dehan tunnelling dielectric thickness, and described direct Tunneling dielectric and described electric charge holding region territory are also put so that electric charge passes described direct Tunneling dielectric and are transferred to the electric charge holding region territory,
Wherein said charge storage device does not have the control gate that is arranged on the described raceway groove.
2, device according to claim 1, wherein said electric charge holding region territory is arranged on the described raceway groove.
3, device according to claim 2, wherein said electric charge holding region territory comprises polysilicon.
4, device according to claim 1, it further comprises:
One is coupled to the charge refresh circuit in described electric charge holding region territory, stored charge in the described electric charge holding region of the described charge refresh circuit periodic refresh territory.
5, a kind of pseudo-nonvolatile charge storage device, it comprises:
The semiconductor substrate;
One is arranged in the source area in the described substrate;
One drain region that is arranged in the described substrate and separates with described source area;
One is arranged in the raceway groove between described source area and the described drain region;
The one electric charge holding region territory that separates with described raceway groove; And
One thickness is less than the direct Tunneling dielectric of one Fu Le-Nuo Dehan tunnelling dielectric thickness, and also put in described direct Tunneling dielectric and described electric charge holding region territory, so that of the electric charge transfer of described direct Tunneling dielectric occur passing to the electric charge holding region territory,
Wherein said electric charge holding region territory is Electrostatic Coupling to a control gate not.
6, device according to claim 5, wherein said electric charge holding region territory is arranged on the described raceway groove.
7, device according to claim 6, wherein said electric charge holding region territory comprises polysilicon.
8, device according to claim 5, it further comprises:
One is coupled to the charge refresh circuit in described electric charge holding region territory, stored charge in the described electric charge holding region of the described charge refresh circuit periodic refresh territory.
9, device according to claim 1, wherein said source area and described drain region comprise that one first conductive-type semiconductor material and described source area and described drain region are arranged in the first area that comprises one second conductive-type semiconductor.
10, require described device according to right 5, wherein said source area and described drain region comprise that the semi-conducting material of one first conductivity type and described source area and described drain region are arranged in the first area that comprises one second conductive-type semiconductor.
11, device according to claim 9, wherein said first area are described semiconductor substrates.
12, device according to claim 10, wherein said first area are described semiconductor substrates.
13, device according to claim 9, wherein said first area are one to be arranged in the trap in the described semiconductor substrate.
14, device according to claim 10, wherein said first area are one to be arranged in the trap in the described semiconductor substrate.
15, device according to claim 13, wherein said trap comprises the semi-conducting material of described second conductivity type.
16, device according to claim 14, wherein said trap comprise the described second conductive-type semiconductor material.
17, a kind of pseudo-nonvolatile charge storage device, it comprises:
One reads transistor, and it comprises:
The semiconductor substrate;
One is arranged in the source area in the described substrate;
One drain region that is arranged in the described substrate and separates with described source area;
One is arranged in the raceway groove between described source area and the described drain region; And
The one electric charge holding region territory that separates with described raceway groove; And
One first tunnel capacitor, it comprises:
One thickness is less than the direct Tunneling dielectric of one Fu Le-Nuo Dehan tunnelling dielectric thickness;
One is used to receive the first node of one first tunnelling control voltage, and described first node is corresponding to one first pole plate of described first tunnel capacitor; And
One first floating node corresponding to one second pole plate of described first tunnel capacitor, described first floating node is coupled to described electric charge holding region territory.
18, device according to claim 17, it further comprises:
One second tunnel capacitor, it comprises:
One thickness is less than the direct Tunneling dielectric of one Fu Le-Nuo Dehan tunnelling dielectric thickness;
One is used to receive the Section Point of one second tunnelling control voltage, and described Section Point is corresponding to one first pole plate of described second tunnel capacitor; And
One second floating node corresponding to one second pole plate of described second tunnel capacitor, described second floating node is coupled to described first floating node and described electric charge holding region territory.
19, device according to claim 17, the wherein said transistor of reading is a pFET.
20, device according to claim 17, the wherein said transistor of reading is a nFET.
21, device according to claim 18, the wherein said transistor of reading is a pFET.
22, device according to claim 18, the wherein said transistor of reading is a nFET.
23, device according to claim 17, the wherein said transistor of reading has source electrode, drain electrode and trap contact.
24, a kind of pseudo-nonvolatile charge storage device, it comprises:
One comprises the substrate of one first conductive-type semiconductor material;
One is arranged in the trap in the described substrate, and described trap comprises one second conductive-type semiconductor material;
One is arranged in the source area in the described trap, and described source area comprises described first a conductive-type semiconductor material;
One is arranged in the drain region in the described trap, and described drain region comprises described first a conductive-type semiconductor material;
One is arranged in the trap joining zone in the described trap, and described trap joining zone comprises described second a conductive-type semiconductor material;
Raceway groove in the one described trap that is arranged between described source area and the described drain region;
The one electric charge holding region territory that separates with described raceway groove;
One thickness is less than the direct Tunneling dielectric of one Fu Le-Nuo Dehan tunnelling dielectric thickness, and also put in described direct Tunneling dielectric and described electric charge holding region territory, so that the electric charge transfer of described direct Tunneling dielectric to described electric charge holding region territory occur passing; And
The interconnection of described source area, described drain region and described trap joining zone is coupled.
25, device according to claim 24, wherein said first conductivity type is the p type.
26, device according to claim 24, wherein said first conductivity type is the n type.
27, a kind of pseudo-nonvolatile charge storage device, it comprises:
One comprises the substrate of one first conductive-type semiconductor material;
One is arranged in the source area in the described trap, and described source area comprises one second conductive-type semiconductor material;
One is arranged in the drain region in the described trap, and described drain region comprises described second a conductive-type semiconductor material;
Raceway groove in one trap that is arranged between described source area and the described drain region;
The one electric charge holding region territory that separates with described raceway groove;
One thickness is less than the direct Tunneling dielectric of one Fu Le-Nuo Dehan tunnelling dielectric thickness, and also put in described direct Tunneling dielectric and described electric charge holding region territory, so that the electric charge transfer of described direct Tunneling dielectric to described electric charge holding region territory occur passing; And
The interconnection of described source area and described drain region is coupled.
28, device according to claim 27, wherein said first conductivity type is the p type.
29, device according to claim 27, wherein said first conductivity type is the n type.
30, a kind of pseudo-nonvolatile charge storage device, it comprises:
One comprises the substrate of one first conductive-type semiconductor material;
One is arranged in first trap in the described substrate, and described first trap comprises one second conductive-type semiconductor material;
One is arranged in second trap in described first trap, and described second trap comprises the described first conductive-type semiconductor material;
One is arranged in the source area in described second trap, and described source area comprises described second a conductive-type semiconductor material;
One is arranged in the drain region in described second trap, and described drain region comprises described second a conductive-type semiconductor material;
One is arranged in the second trap joining zone in described second trap, and the described second trap joining zone comprises described first a conductive-type semiconductor material;
Raceway groove in one described second trap that is arranged between described source area and the described drain region;
The one electric charge holding region territory that separates with described raceway groove;
One thickness is less than the direct Tunneling dielectric of one Fu Le-Nuo Dehan tunnelling dielectric thickness, and also put in described direct Tunneling dielectric and described electric charge holding region territory, so that the electric charge transfer of described direct Tunneling dielectric to described electric charge holding region territory occur passing; And
The interconnection of described source area, described drain region and the described second trap joining zone is coupled.
31, device according to claim 30, it further comprises:
One is arranged in the first trap joining zone in described first trap, and the described first trap joining zone comprises described second a conductive-type semiconductor material.
32, device according to claim 30, wherein said first conductivity type is the p type.
33, device according to claim 30, wherein said first conductivity type is the n type.
34, device according to claim 31, wherein said first conductivity type is the p type.
35, device according to claim 31, wherein said first conductivity type is the n type.
36, a kind of pseudo-nonvolatile charge storage device, it comprises:
One comprises the substrate of one first conductive-type semiconductor material;
One is arranged in first trap in the described substrate, and described first trap comprises one second conductive-type semiconductor material;
One is arranged in second trap in described first trap, and described second trap comprises described first a conductive-type semiconductor material;
One is arranged in first source area in described second trap, and described first source area comprises described second a conductive-type semiconductor material;
One is arranged in first drain region in described second trap, and described first drain region comprises described second a conductive-type semiconductor material;
One is arranged in second source area in described second trap, and described second source area comprises described first a conductive-type semiconductor material;
One is arranged in second drain region in described second trap, and described second drain region comprises described first a conductive-type semiconductor material;
One is arranged in the first trap joining zone in described first trap, and the described first trap joining zone comprises described second a conductive-type semiconductor material;
First raceway groove in one described second trap that is arranged between described first source area and described first drain region;
Second raceway groove in one described second trap that is arranged between described second source area and described second drain region;
The one first electric charge holding region territory that separates with described first raceway groove;
The one second electric charge holding region territory that separates with described second raceway groove;
One thickness is less than the first direct Tunneling dielectric of one Fu Le-Nuo Dehan tunnelling dielectric thickness, also put in described first direct Tunneling dielectric and the described first electric charge holding region territory, so that the electric charge transfer of the described first direct Tunneling dielectric to the described first electric charge holding region territory occur passing;
One thickness is less than the second direct Tunneling dielectric of one Fu Le-Nuo Dehan tunnelling dielectric thickness, also put in described second direct Tunneling dielectric and the described second electric charge holding region territory, so that the electric charge transfer of the described second direct Tunneling dielectric to the described second electric charge holding region territory occur passing;
First of described first source area and described second source area that be coupled interconnects;
Be coupled described first drain region and described second drain region second the interconnection; And
The 3rd interconnection in described first electric charge holding region territory and the described second electric charge holding region territory is coupled.
37, device according to claim 36, it further comprises the interconnection of described first trap joining zone of coupling and described first and second source areas.
38, device according to claim 36, wherein said first conductivity type is the p type.
39, device according to claim 36, wherein said first conductivity type is the n type.
40, according to the described device of claim 37, wherein said first conductivity type is the p type.
41, according to the described device of claim 37, wherein said first conductivity type is the n type.
42, a kind of pseudo-nonvolatile charge storage device, it comprises:
One comprises the substrate of one first conductive-type semiconductor material;
One is arranged in the trap in the described substrate, and described trap comprises one second conductive-type semiconductor material;
One is arranged in the trap joining zone in the described trap, and described trap joining zone comprises described second a conductive-type semiconductor material;
The one electric charge holding region territory that separates with described trap;
One thickness is less than the direct Tunneling dielectric of one Fu Le-Nuo Dehan tunnelling dielectric thickness, and also put in described direct Tunneling dielectric and described electric charge holding region territory, so that the electric charge transfer of described direct Tunneling dielectric to described electric charge holding region territory occur passing; And
Described trap joining zone and the outside interconnection that is connected are provided.
43, according to the described device of claim 42, wherein said first conductivity type is the p type.
44, according to the described device of claim 42, wherein said first conductivity type is the n type.
45, a kind of pseudo-nonvolatile charge storage device, it comprises:
One reads transistor, and it comprises:
The semiconductor substrate;
One is arranged in the source area in the described substrate;
One drain region that is arranged in the described substrate and separates with described source area;
One is arranged in the raceway groove between described source area and the described drain region;
The one electric charge holding region territory that separates with described raceway groove; And
One thickness is less than the first direct Tunneling dielectric of one Fu Le-Nuo Dehan tunnelling dielectric thickness, and also put in described direct Tunneling dielectric and described electric charge holding region territory, so that the electric charge transfer of described direct Tunneling dielectric to described electric charge holding region territory occur passing; And
One first tunnel capacitor, it comprises:
One thickness is less than the second direct Tunneling dielectric of one Fu Le-Nuo Dehan tunnelling dielectric thickness;
One is used to receive the first node of one first tunnelling control voltage, and described first node is corresponding to one first pole plate of described first tunnel capacitor; And
One first floating node corresponding to described first tunnel capacitor, one second pole plate, described first floating node is coupled to described electric charge holding region territory.
46, according to the described device of claim 45, it further comprises:
One second tunnel capacitor, it comprises:
One thickness is less than the 3rd direct Tunneling dielectric of one Fu Le-Nuo Dehan tunnelling dielectric thickness;
One is used to receive the Section Point of one second tunnelling control voltage, and described Section Point is corresponding to one first pole plate of described second tunnel capacitor; And
One second floating node corresponding to described second tunnel capacitor, one second pole plate, described second floating node is coupled to described first floating node and is coupled to described electric charge holding region territory.
47, according to the described device of claim 45, the wherein said transistor of reading is a pFET.
48, according to the described device of claim 45, the wherein said transistor of reading is a nFET.
49, according to the described device of claim 46, the wherein said transistor of reading is a pFET.
50, according to the described device of claim 46, the wherein said transistor of reading is a nFET.
51, according to the described device of claim 45, the wherein said transistor of reading has source electrode, drain electrode and trap contact.
52, a kind of pseudo-nonvolatile charge storage device, it comprises:
One reads transistor, and it comprises:
The semiconductor substrate;
One is arranged in the source area in the described substrate;
One drain region that is arranged in the described substrate and separates with described source area;
One is arranged in the raceway groove between described source area and the described drain region;
The one electric charge holding region territory that separates with described raceway groove; And
One thickness is less than the first direct Tunneling dielectric of one Fu Le-Nuo Dehan tunnelling dielectric thickness, and also put in described direct Tunneling dielectric and described electric charge holding region territory, so that of the electric charge transfer of described direct Tunneling dielectric occur passing to described electric charge holding region territory,
When applying appropriate voltage in described when reading transistor drain, source electrode and well area, described read transistor can make the electronics direct Tunneling to and leave described electric charge holding region territory.
53, according to the described device of claim 52, the wherein said transistor of reading is a pFET.
54, according to the described device of claim 52, the wherein said transistor of reading is a nFET.
55, a kind of pseudo-nonvolatile charge storage device, it comprises:
One electric charge holding region territory;
One first direct Tunneling device, it has the I-V characteristic curve of electronics direct Tunneling to the described electric charge holding region territory; And
One second direct Tunneling device, it has the 2nd I-V characteristic curve that the electronics direct Tunneling is left described electric charge holding region territory.
56, according to the described device of claim 55, wherein:
One I-V characteristic curve of described pseudo-nonvolatile charge storage device is the center symmetry with zero volt.
57, according to the described device of claim 56, it further comprises:
One MOSFET floating boom is read transistor, and its floating boom is coupled to described electric charge holding region territory.
58, according to the described device of claim 57, the wherein said transistor of reading further comprises one source pole contact, a drain contact and a trap contact.
59, according to the described device of claim 58, the wherein said transistor of reading is a pFET.
60, according to the described device of claim 58, the wherein said transistor of reading is a nFET.
61, according to the described device of claim 59, the wherein said first direct Tunneling device comprises a MOSFET with a p-doped gate.
62, according to the described device of claim 61, the wherein said second direct Tunneling device comprises that one has the MOSFET of a n-doped gate.
63, according to the described device of claim 60, wherein said direct Tunneling device comprises that one has the MOSFET of a p-doped gate.
64, according to the described device of claim 63, the wherein said second direct Tunneling device comprises that one has the MOSFET of a n-doped gate.
65, a kind of method that is used for stored charge on a floating boom, it comprises:
Use one to have characteristic first electronic device of one the one I-V, make electronics pass first dielectric of a thickness less than one Fu Le-Nuo Dehan tunnelling thickness, direct Tunneling is to described floating boom; And
Use one to have characteristic second electronic device of one the 2nd I-V, make electronics pass second dielectric of a thickness less than one Fu Le-Nuo Dehan tunnelling thickness, direct Tunneling is left described floating boom.
66, according to the described method of claim 65, it further comprises:
Provide one to be centrosymmetric total I-V characteristic curve, make electron tunneling to described floating boom and leave described floating boom with zero volt.
67, a kind of method of manufacturing one pseudo-nonvolatile charge storage device, it comprises:
In the semiconductor substrate, form the one source pole district;
Form a drain region in described semiconductor substrate, described drain region and described source area separate;
Between described source area and described drain region, form a raceway groove;
The electric charge holding region territory that formation one and described raceway groove separate;
Form the direct Tunneling dielectric of a thickness less than one Fu Le-Nuo Dehan tunnelling dielectric thickness, also put in itself and described electric charge holding region territory, shifts so that described direct Tunneling dielectric to the electric charge in described electric charge holding region territory occurs passing; And
On described electric charge holding region territory, form an insulator, and the control gate of Electrostatic Coupling to described electric charge holding region territory is not provided.
68, a kind of method that is used to make a pseudo-nonvolatile charge storage device, it comprises:
Form one and read transistor, it has:
The semiconductor substrate;
One is arranged in the source area in the described substrate;
One drain region that is arranged in the described substrate and separates with described source area;
One is arranged in the raceway groove between described source area and the described drain region; And
The one electric charge holding region territory that separates with described raceway groove; And
Form one first tunnel capacitor, it comprises:
One thickness is less than the direct Tunneling dielectric of one Fu Le-Nuo Dehan tunnelling dielectric thickness;
One is used to receive the first node of one first tunnelling control voltage, and described first node is corresponding to one first pole plate of described first tunnel capacitor; And
One first floating node corresponding to described first tunnel capacitor, one second pole plate, described first floating node is coupled to described electric charge holding region territory.
69, according to the described method of claim 68, it further comprises:
Form one second tunnel capacitor, it comprises:
One thickness is less than the direct Tunneling dielectric of one Fu Le-Nuo Dehan tunnelling dielectric thickness;
One is used to receive the Section Point of one second tunnelling control voltage, and described Section Point is corresponding to one first pole plate of described second tunnel capacitor; And
One second floating node corresponding to described tunnel capacitor second pole plate, described second floating node are coupled to described first floating node and are coupled to described electric charge holding region territory.
70, a kind of on a floating boom method of stored charge, it comprises:
Use one to have characteristic first electronic device of one the one I-V, make electronics pass first dielectric of a thickness less than one Fu Le-Nuo Dehan tunnelling thickness, direct Tunneling is to described floating boom; And
Use one to have characteristic second electronic device of one the 2nd I-V, make electronics pass second dielectric with Fu Le-Nuo Dehan tunnelling thickness, tunnelling is left described floating boom.
71, a kind of on a floating boom method of stored charge, it comprises:
Use one to have characteristic first electronic device of one the one I-V, make electronics pass first dielectric with one Fu Le-Nuo Dehan tunnelling thickness, tunnelling is to described floating boom; And
Use one to have characteristic second electronic device of one the 2nd I-V, make electronics pass second dielectric of a thickness less than one Fu Le-Nuo Dehan tunnelling thickness, direct Tunneling is left described floating boom.
72, a kind of on a floating boom method of stored charge, it comprises:
Use one to have characteristic first electronic device of one the one I-V, by channel hot electron injection mechanism electronics is passed one first dielectric and inject on the described floating boom; And
Use one to have characteristic second electronic device of one the 2nd I-V, make electronics pass a thickness and leave described floating boom less than the second dielectric tunnelling of one Fu Le-Nuo Dehan tunnelling thickness.
73, a kind of on a floating boom method of stored charge, it comprises:
Use one to have characteristic first electronic device of one the one I-V, by ionization by collision hot electron injection mechanism electronics is passed one first dielectric and inject on the described floating boom; And
Use one to have characteristic second electronic device of the 2nd I-V, make electronics pass a thickness and leave described floating boom less than the second dielectric tunnelling of one Fu Le-Nuo Dehan tunnelling thickness.
74, according to the described method of claim 70, it further comprises:
Charge stored on the described floating boom of periodic refresh.
75, according to the described method of claim 71, it further comprises:
Charge stored on the described floating boom of periodic refresh.
76, according to the described method of claim 72, it further comprises:
Charge stored on the described floating boom of periodic refresh.
77, according to the described method of claim 73, it further comprises:
Charge stored on the described floating boom of periodic refresh.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/143,557 | 2002-05-09 | ||
| US10/143,557 US20040206999A1 (en) | 2002-05-09 | 2002-05-09 | Metal dielectric semiconductor floating gate variable capacitor |
| US10/356,645 US20040021166A1 (en) | 2002-05-09 | 2003-01-31 | Pseudo-nonvolatile direct-tunneling floating-gate device |
| US10/356,645 | 2003-01-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1669155A true CN1669155A (en) | 2005-09-14 |
Family
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN03813938.3A Pending CN1669155A (en) | 2002-05-09 | 2003-04-29 | Pseudo-nonvolatile direct-tunneling floating-gate device |
Country Status (3)
| Country | Link |
|---|---|
| CN (1) | CN1669155A (en) |
| AU (1) | AU2003228833A1 (en) |
| WO (1) | WO2003096432A1 (en) |
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| CN102568577A (en) * | 2012-02-21 | 2012-07-11 | 无锡来燕微电子有限公司 | Non-volatile memory array compatible with complementary metal oxide semiconductors (CMOS) logic technology and operating method |
| CN103855164A (en) * | 2012-12-07 | 2014-06-11 | 旺宏电子股份有限公司 | Semiconductor device, manufacturing method and operating method of semiconductor device |
| CN104112474A (en) * | 2014-07-21 | 2014-10-22 | 中国人民解放军国防科学技术大学 | Storage unit of single polycrystalline nonvolatile storage |
| CN105632889A (en) * | 2014-11-04 | 2016-06-01 | 北大方正集团有限公司 | Method of manufacturing capacitor, capacitor and capacitor module |
| CN107293322A (en) * | 2010-02-07 | 2017-10-24 | 芝诺半导体有限公司 | The floating body transistor containing conducting and semiconductor memory component and operating method with permanent and non-permanent function |
| CN105790573B (en) * | 2016-04-20 | 2018-11-23 | 合肥格易集成电路有限公司 | A kind of charging capacitor and pump circuit |
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| US7215251B2 (en) | 2004-04-13 | 2007-05-08 | Impinj, Inc. | Method and apparatus for controlled persistent ID flag for RFID applications |
| JP4881552B2 (en) | 2004-09-09 | 2012-02-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| CN116705843A (en) * | 2023-08-09 | 2023-09-05 | 上海韬润半导体有限公司 | GCNMOS tube and electrostatic discharge protection circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62179162A (en) * | 1986-01-31 | 1987-08-06 | Seiko Instr & Electronics Ltd | Semiconductor variable capacity element |
| EP0354457B1 (en) * | 1988-08-08 | 1994-06-22 | National Semiconductor Corporation | A bipolar field-effect electrically erasable programmable read only memory cell and method of manufacture |
| DE69610062T2 (en) * | 1995-11-21 | 2001-05-03 | Programmable Microelectronics | Non-volatile PMOS memory device with a single polysilicon layer |
| US5969992A (en) * | 1998-12-21 | 1999-10-19 | Vantis Corporation | EEPROM cell using P-well for tunneling across a channel |
| JP4488565B2 (en) * | 1999-12-03 | 2010-06-23 | 富士通株式会社 | Manufacturing method of semiconductor memory device |
-
2003
- 2003-04-29 WO PCT/US2003/013861 patent/WO2003096432A1/en not_active Application Discontinuation
- 2003-04-29 CN CN03813938.3A patent/CN1669155A/en active Pending
- 2003-04-29 AU AU2003228833A patent/AU2003228833A1/en not_active Abandoned
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| CN102568577B (en) * | 2012-02-21 | 2015-01-14 | 无锡来燕微电子有限公司 | Non-volatile memory array compatible with complementary metal oxide semiconductors (CMOS) logic technology and operating method |
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| CN104112474A (en) * | 2014-07-21 | 2014-10-22 | 中国人民解放军国防科学技术大学 | Storage unit of single polycrystalline nonvolatile storage |
| CN104112474B (en) * | 2014-07-21 | 2017-12-22 | 中国人民解放军国防科学技术大学 | A kind of memory cell of single polycrystalline nonvolatile storage |
| CN105632889A (en) * | 2014-11-04 | 2016-06-01 | 北大方正集团有限公司 | Method of manufacturing capacitor, capacitor and capacitor module |
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| CN111724844A (en) * | 2019-03-22 | 2020-09-29 | 东芝存储器株式会社 | Memory device |
| CN111724844B (en) * | 2019-03-22 | 2023-08-25 | 铠侠股份有限公司 | memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| AU2003228833A1 (en) | 2003-11-11 |
| WO2003096432A1 (en) | 2003-11-20 |
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