AU2003228833A1 - Pseudo-nonvolatile direct-tunneling floating-gate device - Google Patents

Pseudo-nonvolatile direct-tunneling floating-gate device

Info

Publication number
AU2003228833A1
AU2003228833A1 AU2003228833A AU2003228833A AU2003228833A1 AU 2003228833 A1 AU2003228833 A1 AU 2003228833A1 AU 2003228833 A AU2003228833 A AU 2003228833A AU 2003228833 A AU2003228833 A AU 2003228833A AU 2003228833 A1 AU2003228833 A1 AU 2003228833A1
Authority
AU
Australia
Prior art keywords
pseudo
gate device
nonvolatile
direct
tunneling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003228833A
Inventor
Christopher J. Diorio
Todd E. Humes
John D. Hyde
Carver A. Mead
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Impinj Inc
Original Assignee
Impinj Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/143,557 external-priority patent/US20040206999A1/en
Application filed by Impinj Inc filed Critical Impinj Inc
Publication of AU2003228833A1 publication Critical patent/AU2003228833A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
AU2003228833A 2002-05-09 2003-04-29 Pseudo-nonvolatile direct-tunneling floating-gate device Abandoned AU2003228833A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US10/143,557 US20040206999A1 (en) 2002-05-09 2002-05-09 Metal dielectric semiconductor floating gate variable capacitor
US10/143,557 2002-05-09
US10/356,645 2003-01-31
US10/356,645 US20040021166A1 (en) 2002-05-09 2003-01-31 Pseudo-nonvolatile direct-tunneling floating-gate device
PCT/US2003/013861 WO2003096432A1 (en) 2002-05-09 2003-04-29 Pseudo-nonvolatile direct-tunneling floating-gate device

Publications (1)

Publication Number Publication Date
AU2003228833A1 true AU2003228833A1 (en) 2003-11-11

Family

ID=29423055

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003228833A Abandoned AU2003228833A1 (en) 2002-05-09 2003-04-29 Pseudo-nonvolatile direct-tunneling floating-gate device

Country Status (3)

Country Link
CN (1) CN1669155A (en)
AU (1) AU2003228833A1 (en)
WO (1) WO2003096432A1 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7215251B2 (en) 2004-04-13 2007-05-08 Impinj, Inc. Method and apparatus for controlled persistent ID flag for RFID applications
JP4881552B2 (en) 2004-09-09 2012-02-22 ルネサスエレクトロニクス株式会社 Semiconductor device
WO2011097592A1 (en) * 2010-02-07 2011-08-11 Zeno Semiconductor , Inc. Semiconductor memory device having electrically floating body transistor, and having both volatile and non-volatile functionality and method
CN102568577B (en) * 2012-02-21 2015-01-14 无锡来燕微电子有限公司 Non-volatile memory array compatible with complementary metal oxide semiconductors (CMOS) logic technology and operating method
CN103855164A (en) * 2012-12-07 2014-06-11 旺宏电子股份有限公司 Semiconductor device, manufacturing method and operating method of semiconductor device
CN104112474B (en) * 2014-07-21 2017-12-22 中国人民解放军国防科学技术大学 A kind of memory cell of single polycrystalline nonvolatile storage
CN105632889A (en) * 2014-11-04 2016-06-01 北大方正集团有限公司 Method of manufacturing capacitor, capacitor and capacitor module
CN105790573B (en) * 2016-04-20 2018-11-23 合肥格易集成电路有限公司 A kind of charging capacitor and pump circuit
JP2020155186A (en) * 2019-03-22 2020-09-24 キオクシア株式会社 Memory device
CN116705843A (en) * 2023-08-09 2023-09-05 上海韬润半导体有限公司 GCNMOS tube and electrostatic discharge protection circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62179162A (en) * 1986-01-31 1987-08-06 Seiko Instr & Electronics Ltd Semiconductor variable capacity element
EP0354457B1 (en) * 1988-08-08 1994-06-22 National Semiconductor Corporation A bipolar field-effect electrically erasable programmable read only memory cell and method of manufacture
DE69610062T2 (en) * 1995-11-21 2001-05-03 Programmable Microelectronics Non-volatile PMOS memory device with a single polysilicon layer
US5969992A (en) * 1998-12-21 1999-10-19 Vantis Corporation EEPROM cell using P-well for tunneling across a channel
JP4488565B2 (en) * 1999-12-03 2010-06-23 富士通株式会社 Manufacturing method of semiconductor memory device

Also Published As

Publication number Publication date
WO2003096432A1 (en) 2003-11-20
CN1669155A (en) 2005-09-14

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase
TH Corrigenda

Free format text: IN VOL 18, NO 2, PAGE(S) 526 UNDER THE HEADING APPLICATIONS OPI - NAME INDEX UNDER THE NAME IMPINJ,INC., APPLICATION NO. 2003228833 , UNDER INID (43) CORRECT THE PUBLICATION DATE TO READ 24.11.2003