US20080290493A1 - Stacked chip semiconductor device - Google Patents
Stacked chip semiconductor device Download PDFInfo
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- US20080290493A1 US20080290493A1 US12/167,157 US16715708A US2008290493A1 US 20080290493 A1 US20080290493 A1 US 20080290493A1 US 16715708 A US16715708 A US 16715708A US 2008290493 A1 US2008290493 A1 US 2008290493A1
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Abstract
A stacked chip semiconductor device whose size is substantially reduced by high density packaging of two or more semiconductor chips. In the semiconductor device, four semiconductor chips are stacked over a printed wiring board. The bottom semiconductor chip has an interface circuit which includes a buffer and an electrostatic discharge protection circuit. All signals that these semiconductor chips receive and send are inputted or outputted through the interface circuit of the bottom semiconductor chip. Since the other semiconductor chips require no interface circuit, the semiconductor device is compact.
Description
- The present application claims priority from Japanese patent application No. 2003-398469 filed on Nov. 28, 2003, the content of which is hereby incorporated by reference into this application.
- The present invention relates to technology for miniaturization of semiconductor integrated circuit devices and more particularly to technology, which is effective for stacked chip semiconductor devices in which two or more semiconductor chips are stacked.
- With the recent trend toward smaller and higher-performance electronic systems, demand for smaller and higher-density semiconductor integrated circuit devices is growing. One widely-known technique for increasing the density of a package almost equal in size to a semiconductor chip is a semiconductor device with two or more semiconductor chips stacked which is called a stacked CSP (Chip Size Package).
- In this stacked chip semiconductor device, two or more semiconductor chips are stacked in the center of a printed wiring board and a lower semiconductor chip is larger than or equal to an upper one.
- When a lower semiconductor chip and an upper one are bonded, an adhesive agent in the form of paste or film is coated over the surface of the lower one, over which the upper one is laid.
- Bonding pads are made around peripheral areas of the upper and lower semiconductor chips and electrodes made on the printed wiring board are connected with the bonding pads through bonding wires.
- In a stacked CSP memory module in which semiconductor chips including semiconductor memories such as flash memories, DRAMs and SRAMs are stacked, external connection terminals such as address terminals and data input/output terminals (I/O terminals) are shared in order to decrease the number of external connection terminals.
- One example of technology for miniaturization of stacked chip semiconductor devices is that a package includes an ESD protection circuit and other buffer circuits such as decoupling capacitors, drivers and receivers which are provided on support chips other than a core integrated circuit chip (for example, see Patent Literature 1: Japanese Unexamined Patent Publication No. Hei 10 (1998)-41458).
- However, the inventors have found that the above stacked chip semiconductor device has the following problems.
- Although the address terminals and data input/output terminals are shared as mentioned above, the area efficiency in chip layout is low because each semiconductor chip has a function of interfacing with an externally connected module.
- As a consequence, it may be difficult to miniaturize the stacked chip semiconductor device and also the device may be not cost-effective.
- An object of the present invention is to provide a substantially miniaturized stacked chip semiconductor device through high density packaging of two or more semiconductor chips.
- The above and further objects and novel features of the invention will more fully appear from the following detailed description and accompanying drawings.
- Typical aspects of the invention will be briefly outlined below.
- According to one aspect of the present invention, a semiconductor device has a primary semiconductor chip and at least one secondary semiconductor chip which are stacked. Here, the primary semiconductor chip has a primary electrostatic discharge protection circuit to be connected with an external connection terminal; the secondary semiconductor chip has a secondary electrostatic discharge protection circuit whose protection capability is smaller than that of the primary electrostatic discharge protection circuit; and an external signal is inputted and outputted through the primary electrostatic discharge protection circuit.
- According to another aspect of the present invention, a semiconductor device has a semiconductor chip for electrostatic discharge protection, which has a primary electrostatic discharge protection circuit, and at least one secondary semiconductor chip. Here, the secondary semiconductor chip has a secondary electrostatic discharge protection circuit whose protection capability is smaller than that of the primary electrostatic discharge protection circuit; and an external signal is inputted and outputted through the primary electrostatic discharge protection circuit.
- Main advantageous effects, which are brought about by the present invention, are as follows:
- (1) A compact stacked chip semiconductor device is realized.
- (2) Power consumption of a stacked chip semiconductor device is reduced.
- (3) The above effects (1) and (2) contribute to miniaturization of electronic systems and reduction in their power consumption.
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FIG. 1 is a top view of a stacked chip semiconductor device according to a first embodiment of the present invention; -
FIG. 2 is a sectional view of the stacked chip semiconductor device ofFIG. 1 ; -
FIG. 3 illustrates an interface circuit in the stacked chip semiconductor device ofFIG. 1 ; -
FIG. 4 is a circuit diagram of an ESD protection circuit and an input buffer which are incorporated in the interface circuit ofFIG. 3 ; -
FIG. 5 is a circuit diagram of an output buffer incorporated in the interface circuit ofFIG. 3 ; -
FIG. 6 is a top view of a stacked chip semiconductor device according to another embodiment of the present invention; -
FIG. 7 is a top view of a stacked chip semiconductor device according to a second embodiment of the present invention; -
FIG. 8 is a sectional view of the stacked chip semiconductor device ofFIG. 7 ; -
FIG. 9 is a sectional view of a stacked chip semiconductor device according to a third embodiment of the present invention; -
FIG. 10 is a sectional view of a stacked chip semiconductor device according to another embodiment of the present invention; -
FIG. 11 shows a bit configuration in the memory of a stacked chip semiconductor device according to another embodiment of the present invention; -
FIG. 12 shows a word address configuration in the memory of a stacked chip semiconductor device according to another embodiment of the present invention; and -
FIG. 13 illustrates an interface circuit as another example in a stacked chip semiconductor device according to another embodiment of the present invention. - Next, preferred embodiments of the present invention will be described in detail referring to the accompanying drawings. In all the drawings that illustrate the preferred embodiments, like elements are designated by like reference numerals; and descriptions of these elements will not be repeated.
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FIG. 1 is a top view of a stacked chip semiconductor device according to a first embodiment of the present invention,FIG. 2 is a sectional view of the stacked chip semiconductor device ofFIG. 1 ,FIG. 3 illustrates an interface circuit in the stacked chip semiconductor device ofFIG. 1 ,FIG. 4 is a circuit diagram of an ESD protection circuit and an input buffer which are incorporated in the interface circuit ofFIG. 3 , andFIG. 5 is a circuit diagram of an output buffer incorporated in the interface circuit ofFIG. 3 . - In the first embodiment, a stacked
chip semiconductor device 1 consists of a BGA (Ball Grid Array) as a kind of surface mount CSP. As shown inFIGS. 1 and 2 , thesemiconductor device 1 has a printedwiring board 2, for example, made of BT (Bismaleimide Triazine). On the back of the printedwiring board 2 is an array of electrodes for connection. - The printed
wiring board 2 has a stacked structure in whichsemiconductor chips 3 to 6 are stacked in the center of its main surface. The bottom semiconductor chip (primary semiconductor chip) 3 is bonded to the printedwiring board 2 through an adhesive agent such as insulating resin. - The semiconductor chip (secondary semiconductor chip) 4 lies over the
semiconductor chip 3 through an adhesive agent such as insulating resin. The semiconductor chip (secondary semiconductor chip) 5 lies over thesemiconductor chip 4 and the semiconductor chip (secondary semiconductor chip) 6 lies over thesemiconductor chip 5. Likewise, these chips are bonded to each other through an adhesive agent such as insulating resin. - The
semiconductor chips 3 to 6 are comprised of semiconductor memories such as nonvolatile memories. Thebottom semiconductor chip 3 has a memory section and aninterface circuit 7. - The memory section comprises: a control circuit which controls nonvolatile memory read, write and erase operations; a decoder circuit which selects word lines to be accessed; and a memory array including a sense amplifier which amplifies the bit line potential and determines the data read from nonvolatile memory cells. The
interface circuit 7 carries out external input/output and includes a buffer which temporarily stores data for external input/output. - The
semiconductor chips 4 to 6 respectively have memory sections but no interface functions. Thesemiconductor chips 4 to 6 are equal in size (area) to each other and smaller than thesemiconductor chip 3. -
Bonding electrodes 2 a are arranged over the main surface of the printedwiring board 2, along one side on the semiconductor chip periphery. Thebonding electrodes 2 a are electrically connected with connection electrodes by a wiring pattern HP formed in the wiring layer of the printedwiring board 2.Solder bumps 2 b (spherical) are made as the connection electrodes on the back surface of the printedwiring board 2. -
External connection electrodes 3 a are arranged near the bondingelectrodes 2 a along one side on the periphery of the main surface of thesemiconductor chip 3.Internal connection electrodes 3 b are arranged on the inside of theexternal connection electrodes 3 a. - The
internal connection electrodes 3 b are, for example, rectangular and have a larger area than theexternal connection electrodes 3 a. Theinternal connection electrodes 3 b are connected with the memory section of thesemiconductor chip 3. The reason that theinternal connection electrodes 3 b have a larger area than theexternal connection electrodes 3 a is that eachinternal connection electrode 3 b is to be connected toconnection electrodes semiconductor chips 4 to 6 through plural bonding wires while eachexternal connection electrode 3 a is to be connected through one bonding wire. This means that if only onesemiconductor chip 4 is laid over thesemiconductor chip 3, the internal connection electrodes may have the same area as theexternal connection electrodes 3 a. This applies throughout this specification. - Electrodes (connection electrodes) 4 a are arranged along one side on the periphery of the main surface of the
semiconductor chip 4. Theseelectrodes 4 a are each connected to the memory section of thesemiconductor chip 4. Thesemiconductor chip 4 is located in the center of thesemiconductor chip 3, adjacent to theinternal connection electrodes 3 b. - Electrodes (connection electrodes) 5 a are arranged along one side on the periphery of the main surface of the
semiconductor chip 5. Theseelectrodes 5 a are each connected to the memory section of thesemiconductor chip 5. Thesemiconductor chip 5 is located not in the center of thesemiconductor chip 4, but decentered (offset) so that theelectrodes 5 a are exposed from thesemiconductor chip 4 and close to the electrodes (connection electrodes) 6 a. - Electrodes (connection electrodes) 6 a are arranged along one side on the periphery of the main surface of the
semiconductor chip 6. Theseelectrodes 6 a are each connected to the memory section of thesemiconductor chip 6. Like thesemiconductor chip 5, thesemiconductor chip 6 is decentered (offset) so that theelectrodes 6 a are exposed from thesemiconductor chip 5 and close to the electrodes (connection electrodes) 5 a. Thesemiconductor chips 4 to 6 are sifted to the extent that theirelectrodes 4 a to 6 a are exposed and can be connected with theinternal connection electrodes 3 b. - The semiconductor chips 5 and 6 each partially protrude from the projection plane shared with the underlying chip and there is space beneath their protruding parts. Part of the
interface circuit 7 of thesemiconductor chip 3 lies in the space beneath the protruding parts. Since thesemiconductor chip 3 is larger than thesemiconductor chips 4 to 6 and they are stacked in this way, the packaging efficiency is improved. - The
bonding electrodes 2 a of the printedwiring board 2 are connected to theexternal connection electrodes 3 a of thesemiconductor chip 3 throughbonding wires 8. Theexternal connection electrodes 3 a and theinternal connection electrodes 3 b are connected each other through theinterface circuit 7 of thesemiconductor chip 3. Theinternal connection electrodes 3 b and theelectrodes 4 a to 6 a are connected each other throughbonding wires 9 to 11. - This means that signals which not only the memory section of the
semiconductor chip 3 but also the memory sections of thesemiconductor chips 4 to 6 receive and send are all inputted or outputted through theinterface circuit 7 of thesemiconductor chip 3. - Next, the structure of the
interface circuit 7 of thesemiconductor chip 3 will be explained. -
FIG. 3 shows theexternal connection electrodes 3 a,internal connection electrodes 3 b andinterface circuit 7 of thesemiconductor chip 3. - As shown in
FIG. 3 , theexternal connection electrodes 3 a are located on the right and theinternal connection electrodes 3 b on the left and theinterface circuit 7 in the center. However, the layout with these elements of thesemiconductor chip 3 is not limited thereto. - As shown in
FIG. 3 , theexternal connection electrodes 3 a are arranged from top to bottom as follows:external connection electrodes 3 a1 which are connected to external address buses;external connection electrodes 3 a2 which receive control signals;external connection electrodes 3 a3 which are connected to external data buses; and anexternal connection electrode 3 a4 which is connected to an external power line. - As shown in
FIG. 3 , theinternal connection electrodes 3 b are arranged from top to bottom as follows:internal connection electrodes 3 b1 which are connected to internal address buses;internal connection electrodes 3 b2 which receive control signals;internal connection electrodes 3 b3 which are connected to internal data buses; and aninternal connection electrode 3 b4 which is connected to an internal power line. - The
interface circuit 7 includes electrostatic discharge protection circuits (primary ESD protection circuits) 12, input buffers 13, input/output buffers 14, adecoder 15 and apower supply circuit 16. - The
external connection electrodes internal connection electrodes ESD protection circuits 12 and input buffers 13, respectively. - Some of the
internal connection electrodes external connection electrodes decoder 15. And thedecoder 15 further receives the address signals and the control signals. - The
decoder 15 decodes the address signal and control signal which it has received, and generates and outputs a chip select signal which is for selecting whether to activate or inactivate the memory sections of thesemiconductor chips 3 to 6. In writing operation, signals, which are inputted through external data bus, are outputted through an input/output buffer 14 to aninternal connection electrode 3 b3, which is connected to an internal data bus. This input/output changeover in the input/output buffer 14 is carried out according to some of the control signals which come from the outside. - The
power supply circuit 16 transforms the voltage level of power supplied through theexternal connection electrode 3 a4 from an external power line to generate internal power supply voltage. The internal power supply voltage generated by thepower supply circuit 16 is supplied through theinternal connection electrode 3 b4 to thesemiconductor chips 3 to 6. Thepower supply circuit 16 is capable of generating a plurality of internal power supply voltages, which are different voltage levels from And thepower supply circuit 16 is capable of including not only the voltage step down circuit but also the voltage step up circuit, for example a charge pump circuit, etc. - Furthermore, the
interface circuit 7 may also include a circuit which encodes or decodes address signals or data signals. This substantially improves security of the stackedchip semiconductor device 1. -
FIG. 4 illustrates anESD protection circuit 12 and aninput buffer 13 connected between anexternal connection electrode 3 a1 and aninternal connection electrode 3 b1. - The
ESD protection circuit 12 prevents discharge current from reaching the internal circuits of thesemiconductor chips 3 to 6 or limits the discharge current. TheESD protection circuit 12 comprises athyristor 17, aresistor 18, and aclamp MOS transistor 19. Theinput buffer 13 is comprised of aresistor 20 and aNAND circuit 21. - The
external connection electrode 3 a1 is connected to one end of theresistor 18. Thethyristor 17 is connected between the one end of theresistor 18 and reference potential VSS. The other end of theresistor 18 is connected to one end of theinput buffer 13. - The
clamp MOS transistor 19 is connected between the other end of theresistor 18 and reference potential VSS. The other end of theresistor 20 is connected to one input of theNAND circuit 21. And the other input of theNAND circuit 21 is connected to a control signal (write enable signal, etc) output from the internal circuit of thesemiconductor chip 3. The output of theNAND circuit 21 serves as an output of theinput buffer 13. - The
ESD protection circuit 12 is a high ESD tolerance circuit. In order to prevent breakdown of theESD protection circuit 12 itself due to high voltage, its elements are larger than in an internal circuit of a chip core. - On the other hand, since the
semiconductor chips 4 to 6 receive and send signals through theinterface circuit 7 of thesemiconductor chip 3, they only have to withstand at most electrostatic discharge which can occur in an ESD-controlled manufacturing environment. Therefore, they incorporate a relatively simple ESD protection circuit (secondary ESD protection circuit) which is, for example, only composed of a diode and a resistor. - Because the
semiconductor chips 4 to 6 do not require a relatively largeESD protection circuit 12, it is possible to decrease their area for layout and achieve remarkable cost reduction. - Next, the circuitry of the input/output buffer 14 (
FIG. 3 ) will be explained. - The input/
output buffer 14 is comprised of an input buffer 13 (FIG. 4 ) and anoutput buffer 21.FIG. 5 illustrates the structure of theoutput buffer 21. Theoutput buffer 21 is comprised of aninverter 22, ANDcircuits transistors - The input of the
inverter 22 and one input of the ANDcircuit 23 are connected to theinternal connection electrode 3 b3. The output of theinverter 22 is connected to one input of the ANDcircuit 24. - The other inputs of the AND
circuits semiconductor chip 3. The output of the ANDcircuit 23 is connected to the gate of thetransistor 25 and the output of the ANDcircuit 23 is connected to the gate of thetransistor 26. - The
transistors transistors external connection electrode 3 a3. - A signal from one of the
semiconductor chips 3 to 6 goes through theinternal connection electrode 3 b3 to theoutput buffer 21. In thisoutput buffer 21, whether to output the signal or make a high impedance condition is selected according to an output select signal which enters the other inputs of the ANDcircuits - The gate width of the
transistors chip semiconductor device 1 and their gate length is also large enough to obtain a required ESD tolerance at the same time. - Therefore, the
transistors interface circuit 7 is shared among thesemiconductor chips 3 to 6 and the size of thesemiconductor chips 4 to 6 can be remarkably reduced. - Hence, according to this embodiment, sharing of the
interface circuit 7 of thesemiconductor chip 3 permits the use of a fewer number of large transistors necessary for theinterface circuit 7, thereby leading to reduction in the cost of the stackedchip semiconductor device 1 and reduction in its power consumption. - Although the
external connection electrodes 3 a are arranged along one side on the periphery of the main surface of thesemiconductor chip 3 in the first embodiment, instead they may be arranged along two or more sides. For example, as shown inFIG. 6 , in the stacked chip semiconductor device 1 a,external connection electrodes 3 a are arranged along the four sides of thesemiconductor chip 3. In this case, thebonding electrodes 2 a of the printedwiring board 2 are also arranged along the four sides of the printedwiring board 2 and thebonding electrodes 2 a and theexternal connection electrodes 3 a are connected throughbonding wires 8 respectively. - This allows more latitude in layout and permits reduction in the size of the
semiconductor chip 3. -
FIG. 7 is a top view of a stacked chip semiconductor device according to the second embodiment of the present invention; andFIG. 8 is a sectional view of the stacked chip semiconductor device ofFIG. 7 . - As shown in
FIGS. 7 and 8 , in the second embodiment, the stackedchip semiconductor device 1 b consists of a BGA with a stacked structure. Like the first embodiment (seeFIGS. 1 and 2 ), the stackedchip semiconductor device 1 b includes a printedwiring board 2, solder bumps 2 b,semiconductor chips 3 to 6,bonding wires 8 a andbonding wires 9 to 11. The difference from the first embodiment is the layout of the interface circuit of thesemiconductor chip 3. - The
interface circuit 7 is located not on the periphery of theexternal connection electrodes 3 a andinternal connection electrodes 3 b on thesemiconductor chip 3, but on the side facing the side where theexternal connection electrodes 3 a are located. - The connection electrodes are located on the back surface of the printed
wiring board 2 as an array.Semiconductor chips 3 to 6 are stacked in the center of the main surface of the printedwiring board 2. - The
bonding electrodes 2 a are located on the left side of the periphery of the main surface of the printedwiring board 2. Thebonding electrodes 2 a are electrically connected with connection electrodes by a wiring pattern HP formed in the wiring layer of the printedwiring board 2. Solder bumps 2 b (spherical) are made as the connection electrodes on the back surface of the printedwiring board 2. - The
electrodes 3 a are located near thebonding electrodes 2 a, on the left side of the periphery of the main surface of thesemiconductor chip 3 and theinterface circuit 7 is located on the inside of theexternal connection electrodes 3 a. - The
internal connection electrodes 3 b are located on the right side of the periphery of the main surface of thesemiconductor chip 3. They are, for example, rectangular, and larger than theexternal connection electrodes 3 a. They are connected to the memory section of thesemiconductor chip 3. - Like the first embodiment,
electrodes 4 a to 6 a are located on the right side of the periphery of the main surface of each of thesemiconductor chips 4 to 6. Thesesemiconductor chips 4 to 6 are stacked in a staggered manner. - The
bonding electrodes 2 a of the printedwiring board 2 are connected to theexternal connection electrodes 3 a of thesemiconductor chip 3 throughbonding wires 8 a. Theexternal connection electrodes 3 a and theinternal connection electrodes 3 b are connected with each other through theinterface circuit 7 and the internal wiring of thesemiconductor chip 3. Theinternal connection electrodes 3 b and theelectrodes 4 a to 6 a are connected each other throughbonding wires 9 to 11. - Thus, in the second embodiment, for the
semiconductor chip 3, theexternal connection electrodes 3 a andinternal connection electrodes 3 b are separately connected so that the area efficiency of thesemiconductor chip 3 is improved. -
FIG. 9 is a sectional view of a stacked chip semiconductor device according to the third embodiment of the present invention. - In the third embodiment, a stacked
chip semiconductor device 1 c is the same as in the first embodiment except that a semiconductor chip (semiconductor chip with ESD protection) 27 is newly added andsemiconductor chips - As shown in
FIG. 9 , in the stackedchip semiconductor device 1 c, the connection electrodes are located on the back surface of the printedwiring board 2 as an array. The semiconductor chips 3 l, and 4 to 6 are stacked in the center of the main surface of the printedwiring board 2 and theadditional semiconductor chip 27, on which an interface circuit 7 (FIG. 3 ) is structured, lies over thesemiconductor chip 6. - The
bonding electrodes 2 a are located on the right side of the periphery of the main surface of the printedwiring board 2. Thebonding electrodes 2 a are electrically connected with connection electrodes by a wiring pattern HP formed in the wiring layer of the printedwiring board 2. Solder bumps 2 b (spherical) are made as the connection electrodes on the back surface of the printedwiring board 2. -
External connection electrodes 27 a are located on the left side of the periphery of the main surface of thesemiconductor chip 27 andinternal connection electrodes 27 b are located on the right of theexternal connection electrodes 27 a. Theinternal connection electrodes 27 b are, for example, rectangular, and larger than theexternal connection electrodes 3 a. They are connected to the memory sections of thesemiconductor chips - Electrodes (connection electrodes) 28 are located on the right side of the periphery of the main surface of the semiconductor chip (secondary semiconductor chip) 3 l.
Electrodes 4 a to 6 a are provided on the right side of the periphery of the main surfaces of thesemiconductor chips 4 to 6. - The
bonding electrodes 2 a of the printedwiring board 2 are connected to theexternal connection electrodes 27 a of thesemiconductor chip 27 throughbonding wires 29. Theexternal connection electrodes 27 a and theinternal connection electrodes 27 b are connected each other through theinterface circuit 7 of thesemiconductor chip 27. - The
internal connection electrodes 27 b of thesemiconductor chip 27 and theelectrodes semiconductor chips bonding wires 30 to 33. - Thus, in the third embodiment, the addition of the
semiconductor chip 27 with an interface function makes it possible to reduce the sizes of thesemiconductor chips chip semiconductor device 1 c. - When the stacked
chip semiconductor device 1 c is used to make a multimedia card, it is possible to use thesemiconductor chip 27 as a control chip (memory controller). - Although the
semiconductor chip 27 is located at the top in the third embodiment, instead it may lie side-by-side with thesemiconductor chip 3 l at the bottom as shown inFIG. 10 . - In this case, the
electrodes 28 of thesemiconductor chip 3 l are located on the left in the peripheral area and are connected to theinternal electrodes 27 b of thesemiconductor chip 27 throughbonding electrodes 34 provided on the printedwiring board 2, wiring pattern HP1 andbonding wires 35. - When the
semiconductor chip 27 is located at the bottom in this way, if it incorporates a circuit (security means) which encodes/decodes address signals and/or data signals, the security of the stackedchip semiconductor device 1 c is substantially increased. - This means that, because the
semiconductor chip 27 is hard to detach, someone who tries to reverse-engineer the device might break thesemiconductor chip 27. - So far, preferred embodiments of the invention made by the inventors have been concretely described. However, obviously the present invention is not limited to the above embodiments but may be embodied in other various forms without departing from the scope and spirit thereof.
- In the first to third embodiments, input/output buses for the memory sections of the semiconductor chips used in the stacked chip semiconductor device need not consist of 2n bits.
- For example, it is also possible that when a semiconductor chip (primary semiconductor chip) 36, which has a memory of 1 M words×5 bits and an
interface circuit 7, is combined with a semiconductor chip (secondary semiconductor chip) 37 having a memory of 1 M words×3 bits as shown inFIG. 11 , they are regarded as a single memory of 1 M words×8 bits by an external interface. - Consequently, the memory packaging form can be diversified to suit the available packaging space and the device can be mounted in a module or memory card whose shape is restricted, and its memory capacity can be increased.
- In the first to third embodiments, address space in the memory sections of the semiconductor chips used in the stacked chip semiconductor device need not consist of 2n bits.
- For example, it is also possible to combine a semiconductor chip (primary semiconductor chip) 38, which has a memory of 5 M words×8 bits and an
interface circuit 7, with a semiconductor chip (secondary semiconductor chip) 39 having a memory of 3 M words×8 bits as shown inFIG. 12 . - In this case, the
interface circuit 7 incorporates a decoder circuit and 8 M words address is decoded by the decoder circuit and distributed to 5 M words address and 3 Ms word address so that an external interface regards this as a memory of 8 M words×8 bits. - Consequently, the memory packaging form can be diversified to suit the available packaging space and the device can be mounted in a module or memory card whose shape is restricted, and its memory capacity can be increased.
- A function of protection against data leaks can be provided by adding a distribution rule encoding circuit to a decoder circuit which distributes the address space so that the security of the stacked chip semiconductor device is increased.
- In the first to third embodiments, it is also possible to add a counter circuit which generates address signals for the semiconductor chips from clock signals.
-
FIG. 13 shows a stacked chip semiconductor device which includes twosemiconductor chips interface circuit 7 and the semiconductor chip (secondary semiconductor chip) 41 only has a memory section. In this case, acounter circuit 42 is structured in theinterface circuit 7 of thesemiconductor chip 40. - Hence, a memory which permits serial access can be constituted using a random access memory, and a large capacity memory (stacked chip semiconductor device) with a smaller number of external connection terminals can be realized.
- The semiconductor chip packaging technology used for semiconductor devices according to the present invention is suitable for high density packaging of stacked semiconductor chips.
Claims (7)
1-14. (canceled)
15. A semiconductor device comprising:
a printed wiring board having a main surface and a back surface;
a first semiconductor chip having an external connection electrode connected with external connection means for receiving a signal from outside of the semiconductor device, first electrostatic discharge protection means connected with the external connection electrode, a first internal connection electrode connected with the external connection electrode through the first electrostatic discharge protection means and through an input buffer, and a first internal circuit connected to the first internal connection electrode, the first semiconductor chip being mounted on the main surface of the printed wiring board;
a bonding wire having an end connected with the first internal connection electrode; and
a second semiconductor chip having a second internal connection electrode connected with another end of the bonding wire, a second internal circuit connected to the second internal connection electrode, and second electrostatic discharge protection means connected with the second internal connection electrode, the second electrostatic discharge protection means having a smaller area size than the first electrostatic discharge protection means, and the second semiconductor chip being stacked on the first semiconductor chip so that a part of the second semiconductor chip overlaps the first semiconductor chip;
wherein each of a size of the external connection electrode and a size of the second internal connection electrode is less than a size of the first internal connection electrode.
16. The semiconductor device of claim 15 ,
wherein the first semiconductor chip has a first side and a second side;
wherein the external connection electrode and the first internal connection electrode are gathered in a part of the first side of the first semiconductor chip;
wherein the second semiconductor chip has a first side and a second side; and
wherein the second semiconductor chip is stacked on the first semiconductor chip so that the external connection electrode and the first internal connection electrode are exposed from the second semiconductor chip and the first side of the first semiconductor chip is arranged side by side with the first side of the second semiconductor chip.
17. The semiconductor device according to claim 15 ,
wherein the first semiconductor chip includes a memory controller; and
wherein the second semiconductor chip includes a semiconductor memory controlled by the memory controller.
18. The semiconductor device according to claim 15 , wherein the first semiconductor chip and the second semiconductor chip include semiconductor memories.
19. The semiconductor device according to claim 18 , wherein the first semiconductor chip includes a counter circuit which generates address signals for the first semiconductor chip and the second semiconductor chip from clock signals inputted from outside the semiconductor device.
20. The semiconductor device according to claim 19 , wherein the first semiconductor chip includes a security portion for encoding/decoding signals which are received from, or output to, outside the semiconductor device.
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JP2003398469A JP2007066922A (en) | 2003-11-28 | 2003-11-28 | Semiconductor integrated circuit device |
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US10/994,243 US7420281B2 (en) | 2003-11-28 | 2004-11-23 | Stacked chip semiconductor device |
US12/167,157 US20080290493A1 (en) | 2003-11-28 | 2008-07-02 | Stacked chip semiconductor device |
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Also Published As
Publication number | Publication date |
---|---|
US7420281B2 (en) | 2008-09-02 |
US20050116331A1 (en) | 2005-06-02 |
WO2005053025A1 (en) | 2005-06-09 |
JP2007066922A (en) | 2007-03-15 |
TW200524096A (en) | 2005-07-16 |
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