US20080232507A1

US20080232507A1 - Method and System for Simultaneous FM Transmission and FM Reception Using a Shared Antenna and an Integrated Local Oscillator Generator

Info

Publication number: US20080232507A1
Application number: US11/754,621
Authority: US
Inventors: Ahmadreza Rofougaran; Maryam Rofougaran
Original assignee: Broadcom Corp
Current assignee: Broadcom Corp
Priority date: 2007-03-19
Filing date: 2007-05-29
Publication date: 2008-09-25
Also published as: US20080231535A1; US20110206099A1; US7586458B2; US8249650B2; US20080231536A1; US20110291911A1; US20080233891A1; US7920893B2; US20090289870A1; US20080232512A1; US20080233874A1; US20080233868A1; US8509356B2; US7925222B2; US8600315B2; US8369889B2; US20080231357A1; US20120231752A1; US7821472B2; US20080233871A1

Abstract

Certain aspects of a method and system for simultaneous FM transmission and FM reception using a shared antenna and an integrated local oscillator generator may be disclosed. In a chip that handles communication of Bluetooth signals and FM signals, a clock signal may be generated at a particular frequency to enable transmission and/or reception of Bluetooth signals. A plurality of signals may be generated via a plurality of direct digital frequency synthesizers (DDFSs), which enable simultaneous transmission of FM signals and reception of FM signals. The plurality of DDFSs may be clocked by the generated clock signal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

This application makes reference to, claims priority to, and claims benefit of U.S. Provisional Application Ser. No. 60/895,698 (Attorney Docket No. 18372US01) filed Mar. 19, 2007.
This application also makes reference to:
U.S. patent application Ser. No. ______ (Attorney Docket Number 18372US02) filed on even date herewith;
U.S. patent application Ser. No. ______ (Attorney Docket Number 18574US02) filed on even date herewith;
U.S. patent application Ser. No. ______ (Attorney Docket Number 18575US02) filed on even date herewith;
U.S. patent application Ser. No. ______ (Attorney Docket Number 18577US02) filed on even date herewith;
U.S. patent application Ser. No. ______ (Attorney Docket Number 18578US02) filed on even date herewith;
U.S. patent application Ser. No. ______ (Attorney Docket Number 18579US02) filed on even date herewith;
U.S. patent application Ser. No. ______ (Attorney Docket Number 18580US02) filed on even date herewith;
U.S. patent application Ser. No. ______ (Attorney Docket Number 18581US02) filed on even date herewith;
U.S. patent application Ser. No. ______ (Attorney Docket Number 18590US02) filed on even date herewith; and
U.S. patent application Ser. No. ______ (Attorney Docket Number 18591US02) filed on even date herewith.
Each of the above stated applications is hereby incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

Certain embodiments of the invention relate to multi-standard systems. More specifically, certain embodiments of the invention relate to a method and system for simultaneous FM transmission and FM reception using a shared antenna and an integrated local oscillator generator.

BACKGROUND OF THE INVENTION

A direct digital frequency synthesizer (DDFS) is a digitally-controlled signal generator that may vary the output signal frequency over a large range of frequencies, based on a single fixed-frequency precision reference clock. In addition, a DDFS is also phase-tunable. In essence, within the DDFS, discrete amplitude levels are input to a digital-to-analog converter (DAC) at a sampling rate determined by the fixed-frequency reference clock. The output of the DDFS may provide a signal whose shape may depend on the sequence of discrete amplitude levels that are input to the DAC at the constant sampling rate. The DDFS is particularly well suited as a frequency generator that outputs a sine or other periodic waveforms over a large range of frequencies, from almost DC to approximately half the fixed-frequency reference clock frequency.
A DDFS offers a larger range of operating frequencies and requires no feedback loop, thereby providing near instantaneous phase and frequency changes, avoiding overshooting, undershooting and settling time issues associated with other analog systems. A DDFS may provide precise digitally-controlled frequency and/or phase changes without signal discontinuities.
With the popularity of portable electronic devices and wireless devices that support audio applications, there is a growing need to provide a simple and complete solution for audio communications applications. For example, some users may utilize Bluetooth-enabled devices, such as headphones and/or speakers, to allow them to communicate audio data with their wireless handset while freeing to perform other activities. Other users may have portable electronic devices that may enable them to play stored audio content and/or receive audio content via broadcast communication, for example.
However, integrating multiple audio communication technologies into a single device may be costly. Combining a plurality of different communication services into a portable electronic device or a wireless device may require separate processing hardware and/or separate processing software. Moreover, coordinating the reception and/or transmission of data to and/or from the portable electronic device or a wireless device that uses FM transceivers may require significant processing overhead that may impose certain operation restrictions and/or design challenges.
Furthermore, simultaneous use of a plurality of radios in a handheld may result in significant increases in power consumption. Power being a precious commodity in most wireless mobile devices, combining devices such as a Bluetooth radio and a FM radio requires careful design and implementation in order to minimize battery usage. Additional overhead such as sophisticated power monitoring and power management techniques are required in order to maximize battery life.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

A method and/or system for simultaneous FM transmission and FM reception using a shared antenna and an integrated Bluetooth local oscillator generator, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.
These and other advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1A is a block diagram of an exemplary FM transmitter that communicates with handheld devices that utilize a single chip with integrated Bluetooth and FM radios, in accordance with an embodiment of the invention.

FIG. 1B is a block diagram of an exemplary FM receiver that communicates with handheld devices that utilize a single chip with integrated Bluetooth and FM radios, in accordance with an embodiment of the invention.

FIG. 1C is a block diagram of an exemplary single chip with integrated Bluetooth and FM radios that supports FM processing and an external device that supports Bluetooth processing, in accordance with an embodiment of the invention.

FIG. 1D is a block diagram of an exemplary single chip with integrated Bluetooth and FM radios and an external device that supports Bluetooth and FM processing, in accordance with an embodiment of the invention.

FIG. 1E is a block diagram that illustrates an exemplary single integrated circuit (IC) that supports FM and Bluetooth radio operations, in accordance with an embodiment of the invention.

FIG. 2A is a block diagram illustrating an exemplary integration of Bluetooth and FM local oscillator generation in a single unit using a direct digital frequency synthesizer (DDFS), in accordance with an embodiment of the invention.

FIG. 2B is a block diagram illustrating an exemplary DDFS, in accordance with an embodiment of the invention.

FIG. 3 is a block diagram of an exemplary system for FM transmission and/or FM reception, in connection with an embodiment of the invention.

FIG. 4 is an exemplary diagram of a System on Chip (SoC) with integrated Bluetooth and FM radios, in accordance with an embodiment of the invention.

FIG. 5 is an exemplary block diagram of simultaneous FM transmission and FM reception using a shared antenna and an integrated Bluetooth local oscillator generator, in accordance with an embodiment of the invention.

FIG. 6 is a flowchart illustrating exemplary steps for simultaneous FM transmission and FM reception using a shared antenna and an integrated Bluetooth local oscillator generator, in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Certain embodiments of the invention may be found in a method and systems for simultaneous FM transmission and FM reception using a shared antenna and an integrated local oscillator generator. In a chip that handles communication of Bluetooth signals and FM signals, a clock signal may be generated at a particular frequency to enable transmission and/or reception of Bluetooth signals. A plurality of signals may be generated via a plurality of direct digital frequency synthesizers (DDFSs), which enable simultaneous transmission of FM signals and reception of FM signals. The plurality of DDFSs may be clocked by the generated clock signal.
FIG. 1A is a block diagram of an exemplary FM transmitter that communicates with handheld devices that utilize a single chip with integrated Bluetooth and FM radios, in accordance with an embodiment of the invention. Referring to FIG. 1A, there is shown an FM transmitter 102, a cellular phone 104 a, a smart phone 104 b, a computer 104 c, and an exemplary FM and Bluetooth-equipped device 104 d. The FM transmitter 102 may be implemented as part of a radio station or other broadcasting device, for example. Each of the cellular phone 104 a, the smart phone 104 b, the computer 104 c, and the exemplary FM and Bluetooth-equipped device 104 d may comprise a single chip 106 with integrated Bluetooth and FM radios for supporting FM and Bluetooth data communications. The FM transmitter 102 may enable communication of FM audio data to the devices shown in FIG. 1A by utilizing the single chip 106. Each of the devices in FIG. 1A may comprise and/or may be communicatively coupled to a listening device 108 such as a speaker, a headset, or an earphone, for example.
The cellular phone 104 a may be enabled to receive an FM transmission signal from the FM transmitter 102. The user of the cellular phone 104 a may then listen to the transmission via the listening device 108. The cellular phone 104 a may comprise a “one-touch” programming feature that enables pulling up specifically desired broadcasts, like weather, sports, stock quotes, or news, for example. The smart phone 104 b may be enabled to receive an FM transmission signal from the FM transmitter 102. The user of the smart phone 104 b may then listen to the transmission via the listening device 108.
The computer 104 c may be a desktop, laptop, notebook, tablet, and a PDA, for example. The computer 104 c may be enabled to receive an FM transmission signal from the FM transmitter 102. The user of the computer 104 c may then listen to the transmission via the listening device 108. The computer 104 c may comprise software menus that configure listening options and enable quick access to favorite options, for example. In one embodiment of the invention, the computer 104 c may utilize an atomic clock FM signal for precise timing applications, such as scientific applications, for example. While a cellular phone, a smart phone, computing devices, and other devices have been shown in FIG. 1A, the single chip 106 may be utilized in a plurality of other devices and/or systems that receive and use Bluetooth and/or FM signals.
A clock signal f_LOmay be generated at a particular frequency in the single chip 106 that handles communication of Bluetooth signals and FM signals. The generated clock signal f_LOmay be utilized for clocking one or more direct digital frequency synthesizers (DDFSs) to enable transmission of the FM signals.
FIG. 1B is a block diagram of an exemplary FM receiver that communicates with handheld devices that utilize a single chip with integrated Bluetooth and FM radios, in accordance with an embodiment of the invention. Referring to FIG. 1B, there is shown an FM receiver 110, the cellular phone 104 a, the smart phone 104 b, the computer 104 c, and the exemplary FM and Bluetooth-equipped device 104 d. In this regard, the FM receiver 110 may comprise and/or may be communicatively coupled to a listening device 108. A device equipped with the Bluetooth and FM transceivers, such as the single chip 106, may be able to broadcast its respective signal to a “deadband” of an FM receiver for use by the associated audio system. For example, a cellphone or a smart phone, such as the cellular phone 104 a and the smart phone 104 b, may transmit a telephone call for listening over the audio system of an automobile, via usage of a deadband area of the car's FM stereo system. One advantage may be the universal ability to use this feature with all automobiles equipped simply with an FM radio with few, if any, other external FM transmission devices or connections being required.
In another example, a computer, such as the computer 104 c, may comprise an MP3 player or another digital music format player and may broadcast a signal to the deadband of an FM receiver in a home stereo system. The music on the computer may then be listened to on a standard FM receiver with few, if any, other external FM transmission devices or connections. While a cellular phone, a smart phone, and computing devices have been shown, a single chip that combines a Bluetooth and FM transceiver and/or receiver may be utilized in a plurality of other devices and/or systems that receive and use an FM signal.
A clock signal f_LOmay be generated at a particular frequency in the single chip 106 that handles communication of Bluetooth signals and FM signals. The generated clock signal f_LOmay be utilized for clocking one or more direct digital frequency synthesizers (DDFSs) to enable reception of the FM signals.
FIG. 1C is a block diagram of an exemplary single chip with integrated Bluetooth and FM radios that supports FM processing and an external device that supports Bluetooth processing, in accordance with an embodiment of the invention. Referring to FIG. 1C, there is shown a single chip 112 a that supports Bluetooth and FM radio operations and an external device 114. The single chip 112 a may comprise an integrated Bluetooth radio 116, an integrated FM receiver 118, an integrated FM transmitter 121 and an integrated processor 120. The Bluetooth radio 116 may comprise suitable logic, circuitry, and/or code that enable Bluetooth signal communication via the single chip 112 a. In this regard, the Bluetooth radio 116 may support audio signals or communication. The FM receiver 118 may comprise suitable logic, circuitry, and/or code that enable FM signal communication via the single chip 112 a.
The integrated processor 120 may comprise suitable logic, circuitry, and/or code that may enable processing of the FM data received by the FM receiver 118. Moreover, the integrated processor 120 may enable processing of FM data to be transmitted by the FM receiver 118 when the FM receiver 118 comprises transmission capabilities. The external device 114 may comprise a baseband processor 122. The baseband processor 122 may comprise suitable logic, circuitry, and/or code that may enable processing of Bluetooth data received by the Bluetooth radio 116. Moreover, the baseband processor 122 may enable processing of Bluetooth data to be transmitted by the Bluetooth radio 116. In this regard, the Bluetooth radio 116 may communicate with the baseband processor 122 via the external device 114. The Bluetooth radio 116 may communicate with the integrated processor 120. The FM transmitter 121 may comprise suitable logic, circuitry, and/or that may enable transmission of FM signals via appropriate broadcast channels, for example.
FIG. 1D is a block diagram of an exemplary single chip with integrated Bluetooth and FM radios and an external device that supports Bluetooth and FM processing, in accordance with an embodiment of the invention. Referring to FIG. 1D, there is shown a single chip 112 b that supports Bluetooth and FM radio operations and an external device 114. The single chip 112 b may comprise the Bluetooth radio 116, FM reception radio 118, and FM transmission radio 123. The Bluetooth radio 116, the FM reception radio 118 and FM transmission radio 123 may be integrated into the single chip 112 b. The external device 114 may comprise a baseband processor 122. The baseband processor 122 may comprise suitable logic, circuitry, and/or code that may enable processing of Bluetooth data received by the Bluetooth radio 116 and/or processing of Bluetooth data to be transmitted by the Bluetooth radio 116. In this regard, the Bluetooth radio 116 may communicate with the baseband processor 122 via the external device 114. Moreover, the baseband processor 122 may comprise suitable logic, circuitry, and/or code that may enable processing of the FM data received by the FM reception radio 118. The baseband processor 122 may enable processing FM data to be transmitted by the FM transmission radio 123. In this regard, the FM reception radio 118 and the FM transmission radio 123 may communicate with the baseband processor 122 via the external device 114.
FIG. 1E is a block diagram that illustrates an exemplary single radio chip that supports FM and Bluetooth radio operations, in accordance with an embodiment of the invention. Referring to FIG. 1F, there is shown a mobile phone 150 that may comprise a FM/Bluetooth coexistence antenna system 152 and a single chip FM/Bluetooth (FM/BT) radio device 154. The single chip FM/BT radio device 154 may comprise a FM radio portion 156 and a Bluetooth radio portion 158. The single chip FM/BT radio device 154 may be implemented based on a system-on-chip (SOC) architecture, for example.
The FM/Bluetooth coexistence antenna system 152 may comprise suitable hardware, logic, and/or circuitry that may be enabled to provide FM and Bluetooth communication between external devices and a coexistence terminal. The FM/Bluetooth coexistence antenna system 152 may comprise at least one antenna for the transmission and reception of FM and Bluetooth packet traffic.
The FM radio portion 156 may comprise suitable logic, circuitry, and/or code that may be enabled to process FM packets for communication. The FM radio portion 156 may be enabled to transfer and/or receive FM packets and/or information to the FM/Bluetooth coexistence antenna system 152 via a single transmit/receive (Tx/Rx) port. In some instances, the transmit port (Tx) may be implemented separately from the receive port (Rx). The FM radio portion 156 may also be enabled to generate signals that control at least a portion of the operation of the FM/Bluetooth coexistence antenna system 152. Firmware operating in the FM radio portion 156 may be utilized to schedule and/or control FM packet communication, for example.
The FM radio portion 156 may also be enabled to receive and/or transmit priority signals 160. The priority signals 160 may be utilized to schedule and/or control the collaborative operation of the FM radio portion 156 and the Bluetooth radio portion 158. The Bluetooth radio portion 158 may comprise suitable logic, circuitry, and/or code that may be enabled to process Bluetooth protocol packets for communication. The Bluetooth radio portion 158 may be enabled to transfer and/or receive Bluetooth protocol packets and/or information to the FM/Bluetooth coexistence antenna system 152 via a single transmit/receive (Tx/Rx) port. In some instances, the transmit port (Tx) may be implemented separately from the receive port (Rx). The Bluetooth radio portion 158 may also be enabled to generate signals that control at least a portion of the operation of the FM/Bluetooth coexistence antenna system 152. Firmware operating in the Bluetooth radio portion 158 may be utilized to schedule and/or control Bluetooth packet communication. The Bluetooth radio portion 158 may also be enabled to receive and/or transmit priority signals 160. A portion of the operations supported by the FM radio portion 156 and a portion of the operations supported by the Bluetooth radio portion 158 may be performed by common logic, circuitry, and/or code.
In some instances, at least a portion of either the FM radio portion 156 or the Bluetooth radio portion 158 may be disabled and the wireless terminal may operate in a single-communication mode, that is, coexistence may be disabled. When at least a portion of the FM radio portion 156 is disabled, the FM/Bluetooth coexistence antenna system 152 may utilize a default configuration to support Bluetooth communication. When at least a portion of the Bluetooth radio portion 158 is disabled, the FM/Bluetooth coexistence antenna system 152 may utilize a default configuration to support FM communication.
FIG. 2A is a block diagram illustrating an exemplary integration of Bluetooth and FM local oscillator generation in a single unit using a direct digital frequency synthesizer (DDFS), in accordance with an embodiment of the invention. Referring to FIG. 2A, there is shown a communication system 200. The communication system 200 comprises a FM transceiver 202, a Bluetooth transceiver 204, a processor 240, a local oscillator generation unit (LOGEN) 212, and a coupler 234 coupled to an antenna 244. The FM transceiver 202 may comprise a FM receiver 232 and a FM transmitter 230. The Bluetooth transceiver 204 may comprise a Bluetooth receiver 208 and a Bluetooth transmitter 210. The LOGEN 212 may comprise a filter 236, a digital to analog converter (DAC) 238 a direct digital frequency synthesizer (DDFS) 242, and a frequency synthesizer/phase locked loop (PLL) 214.
The LOGEN 212 may comprise suitable logic, circuitry, and/or code that may be enabled to generate a Bluetooth clock signal f_BTcomprising an in-phase (I) component f_BT _— _Iand a quadrature-phase (Q) component f_BT _— _Q. The I component and Q component signals may be communicated to the Bluetooth receiver 208 and the Bluetooth transmitter 210. The frequency of the generated Bluetooth clock signal f_BTto the Bluetooth receiver 208 and the Bluetooth transmitter 210 may be about 2.4 GHz, for example, and may be enabled to clock one or more of the Bluetooth receiver 208 and the Bluetooth transmitter 210. The LOGEN 212 may also be enabled to generate an I component and a Q component output signal, f_FM _— _Iand f_FM _— _Qrespectively to the FM transceiver 202. The I and Q component signals, f_FM _— _Iand f_FM _— _Qrespectively may be communicated to the FM receiver 232 and the FM transmitter 230. The frequency of the generated FM clock signal f_FMto the FM receiver 232 and the FM transmitter 230 may be about 78-100 MHz, for example, and may be enabled to clock one or more of the FM receiver 232 and the FM transmitter 230.
The PLL 214 may comprise suitable logic, circuitry, and/or code that may be enabled to be utilized as frequency modulation (FM) demodulators, or carrier recovery circuits, or as frequency synthesizers for modulation and demodulation. The output of the PLL 214 may have a phase noise characteristic similar to that of the DDFS 242, but may operate at a higher frequency.
The PLL 214 may be enabled to generate a Bluetooth clock signal f_BTcomprising an in-phase (I) component f_BT _— _Iand a quadrature-phase (Q) component f_BT _— _Q. The I component and Q component signals may be communicated to the Bluetooth receiver 208 and the Bluetooth transmitter 210. In accordance with an exemplary embodiment of the invention, the PLL 214 may be enabled to clock the DDFS 242 at a particular frequency, for example, at 1 GHz.
The DAC 238 may comprise suitable logic, circuitry and/or code that may enable generation of an analog output signal based on a received sequence of input binary numbers. The DAC 238 may be enabled to generate a corresponding analog voltage level for each input binary number. The number of distinct analog voltage levels may be equal to the number of distinct binary numbers in the input sequence.
The filter 238 may comprise suitable logic, circuitry and/or code that may enable low pass filtering (LPF) of signal components contained in a received input signal. The filter 238 may enable smoothing of the received input signal to attenuate amplitudes for undesirable frequency components contained in the received input signal. The filter 238 may generate a signal, f_FM, having a frequency in the FM frequency band. In an exemplary embodiment of the invention, the range of frequencies for the signal f_FMmay be between about 78 MHz and 100 MHz, for example. The signal f_FMmay be a quadrature signal comprising I and Q signal components, f_FM _— _Iand f_FM _— _Qrespectively. The 78-100 MHz I and Q signals may be communicated to an FM transmitter 230 and/or an FM receiver 232.
In an exemplary embodiment of the invention, the FM transmitter 230 and the FM receiver 232 may be coupled to an antenna 244 via a bidirectional coupler 234. The bidirectional coupler 234 may couple the antenna to the FM receiver 232 at a given time instant, such that the FM receiver 232 signal may receive signals via the antenna 244. The bidirectional coupler 234 may couple the antenna to the FM transmitter 230 at a different time instant under the control of a different f_Wordto the DDFS 242, such that the FM transmitter 230 signal may transmit signals via the antenna 244. In another exemplary embodiment of the invention, the FM transmitter 230 may be coupled to a transmitting antenna 245 b, while the FM receiver 232 may be coupled to a receiving antenna 245 a.
In accordance with an embodiment of the invention, the value f_Wordmay be selected to maintain an approximately constant frequency for the signal f_FMdespite changes that may occur in the signal f_LO, which may occur due to frequency hopping in the Bluetooth communication signal.
FIG. 2B is a block diagram illustrating an exemplary direct digital frequency synthesizer (DDFS), in accordance with an embodiment of the invention. Referring to FIG. 2B, there is shown a DDFS 250, a clock 252 and a DDFS controller 254. The DDFS 250 may be a digitally-controlled signal generator that may vary the analog output signal g(t) over a large range of frequencies, based on a single fixed-frequency precision reference clock, for example, clock 252. Notwithstanding, the DDFS 250 may also be phase-tunable. The digital input signal d(t) may comprise control information regarding the frequency and/or phase of the analog output signal g(t) that may be generated as a function of the digital input signal d(t). The clock 252 may provide a reference clock that may be N times higher than the frequency fc of the generated output signal g(t). The DDFS controller 254 may generate a variable frequency analog output signal g(t) by utilizing the clock 252 and the digital input signal d(t).
FIG. 3 is a block diagram of an exemplary system for FM transmission and/or FM reception, in connection with an embodiment of the invention. Referring to FIG. 3, there is shown a radio 320. The radio 320 may comprise two frequency synthesizers 324 a and 324 b, an FM reception (Rx) block 326, a memory 328, a processor 330, and a FM transmission (Tx) block 332.
The frequency synthesizers 324 a and 324 b may comprise suitable logic, circuitry, and/or code that may enable generation of fixed or variable frequency signals. For example, the frequency synthesizers 324 a and 324 b may each comprise one or more phase locked loops (PLL) and one or more reference signal generators, such as a crystal oscillator. Additionally, the frequency synthesizers 324 a and 324 b may each comprise, for example, one or more phase shifters and/or signal dividers such that two signals in phase quadrature may be generated.
The memory 328 may comprise suitable logic circuitry and/or code that may enable storing information. In this regard, the memory 328 may, for example, enable storing information utilized for controlling and/or configuring the frequency synthesizers 324. For example, the memory may store the value of state variables that may be utilized to control the frequency output by each of the frequency synthesizers 324. Additionally, the memory 328 may enable storing information that may be utilized to configure the FM Tx block 332 and the FM Rx block 326. In this regard, the FM RX block 326 and/or the FM Tx block 332 may comprise logic, circuitry, and/or code such as a filter, for example that may be configured based on the desired frequency of operation.
The processor 330 may comprise suitable logic, circuitry, and/or code that may enable interfacing to the memory 328, the frequency synthesizer 324, the FM Rx block 326 and/or the FM Tx block 332. In this regard, the processor 330 may be enabled to execute one or more instructions that enable reading and/or writing to/from the memory 328. Additionally, the processor 330 may be enabled to execute one or more instruction that enable providing one or more control signals to the frequency synthesizer 324, the FM Rx block 326, and/or the FM Tx block 332.
The FM Rx block 326 may comprise suitable logic, circuitry, and/or code that may enable reception of FM signals. In this regard, the FM Rx block 326 may be enabled to tune to a desired channel, amplify received signals, down-convert received signals, and/or demodulate received signals to, for example, output data and/or audio information comprising the channel. For example, the FM Rx block 326 may utilize phase quadrature local oscillator signals generated by frequency synthesizer 324 a to down-convert received FM signals. The FM Rx block 326 may, for example, be enabled to operate over the FM broadcast band, or approximately 60 MHz to 130 Mhz. Signal processing performed by the FM Rx block 326 may be preformed entirely in the analog domain, or the FM Rx block 326 may comprise one or more analog to digital converters and/or digital to analog converters.
The FM Tx block 332 may comprise suitable logic, circuitry, and/or code that may enable transmission of FM signals. In this regard, the FM Tx block 332 may enable frequency modulating a carrier signal with audio/data information. In this regard, the carrier frequency may be generated by the clock frequency synthesizer 324 b. The FM Tx block 332 may also enable up-converting a modulated signal to a frequency, for example, in the FM broadcast band, or approximately 60 MHz to 130 MHz. Additionally, the FM Tx block 332 may enable buffering and/or amplifying a FM signal such that the signal may be transmitted via the antenna 336.
The FM Rx block 326 and the FM Tx block 332 may share an antenna or utilize separate antennas. In the case of a shared antenna, a directional coupler, transformer, or some other circuitry may be utilized to couple the Tx output and Rx input to the single antenna. Additionally, any antennas utilized by the FM Tx block 332 and/or the FM Rx block 326 may be integrated into the same substrate as the radio 320 or may be separate.
In an exemplary operation of the radio 320, one or more signals provided by the processor 330 may configure the radio 320 to either transmit or receive FM signals. To receive FM signals the processor 330 may provide one or more control signals to frequency synthesizers 324 a and 324 b in order to generate appropriate LO frequencies based on the reference signal f_ref. In this regard, the processor 330 may interface with the memory 328 in order to determine the appropriate state of any control signals provided to the frequency synthesizers 324 a and 324 b. In this manner, the transmit frequency and receive frequency may be determined independently. Accordingly, utilizing a transmit frequency different from the receive frequency may enable simultaneous transmission and reception of FM signals.
FIG. 4 is an exemplary diagram of a System on Chip (SoC) with integrated Bluetooth and FM radios, in accordance with an embodiment of the invention. Referring to FIG. 4, the SoC 400 may comprise a Bluetooth block 410 and an FM block 420. The FM block 420 may comprise two DDFSs 422 a and 422 b, an FM reception (Rx) block 426, a memory 428, a processor 430, and a FM transmission (Tx) block 432. The various components of FIG. 4 may be substantially as described in FIG. 3.
The Bluetooth block 410 may comprise suitable logic, circuitry, and/or code that may enable communicating with a Bluetooth terminal. In this regard, the Bluetooth block 410 may be similar to or the same as the Bluetooth transceiver 204 disclosed in FIG. 2A. Accordingly, the frequency synthesizer 412 may comprise a PLL that may generate a signal utilized in the communication of Bluetooth data. One or more control signals may be provided to the Bluetooth block 410 by the processor 430 and/or the memory 428. Similarly, one or more control signals may be provided to the memory 428 and/or the processor 430 by the Bluetooth block 410. In this regard, digital information may be exchanged between the Bluetooth block 410 and the FM block 420. For example, changes in operating frequency of the frequency synthesizer 412 may be communicated to the memory 428 and/or the processor 430 such that the frequency control word f_wordto the DDFSs 422 a and 422 b may be altered to compensate for the frequency change.
The FM block 420 may comprise suitable logic, circuitry, and/or code that may enable the simultaneous transmission and reception of FM signals. In this regard, the FM block 420 may be similar to the radio 320 disclosed in FIG. 3. In contrast to the radio 320, the FM block 420 may comprise two DDFSs 422 a and 422 b instead of the traditional analog frequency synthesizers, such as the frequency synthesizers 324 a and 324 b. Accordingly, the FM block 420 may be enabled to utilize reference signals of widely varying frequency. In this regard, the DDFSs 422 a and 422 b may enable utilizing the output of the frequency synthesizers 412 to generate signals utilized by the FM Tx block 432 and the FM Rx block 426. In this manner, a reduction in power consumption and circuit size may be realized in the SoC 400 by sharing a single frequency synthesizer 412 between the FM block 420 and the Bluetooth block 410. Moreover, because the DDFSs 422 a and 422 b may be controlled to output nearly any frequency from DC to half the reference frequency, a single reference frequency may be utilized to generate different transmit and receive frequencies. Consequently, the FM block 420 may simultaneously transmit and receive FM signals.
In an exemplary operation, the SoC 400 may simultaneously transmit FM signals, receive FM signals, and interface to a Bluetooth terminal. To receive FM signals, the processor 430 may interface with the memory 428 to provide a frequency control word f_word1to the DDFS 422 a to enable generation of an appropriate LO frequency for the desired receive channel, based on the reference signal, f_ref. In this regard, f_refmay comprise an output of a PLL utilized by the Bluetooth block 410. For example, the Bluetooth may operate at 2.4 GHz and the frequency generator 412 may accordingly output a 2.4 GHz signal. The DDFS 422 a may utilize an appropriate frequency control word f_word1and the 2.4 GHz signal to generate, for example, a frequency in the FM broadcast band, or approximately 60 MHz to 130 MHz.
To transmit FM signals, the processor 430 may provide a frequency control word f_word2to the DDFS 422 b in order to generate an appropriate LO frequency for the desired transmit channel, based on the reference signal, f_ref. Alternatively, the processor may provide a series of frequency control words to the DDFS 422 b in order to generate a FM signal. In this regard, the processor 430 may interface with the memory 428 in order to determine the appropriate state of any control signals and the appropriate values of the frequency control word f_word2provided to the DDFS 422 b. The reference signal f_refmay comprise an output of a PLL utilized by the Bluetooth block 410. For example, the Bluetooth block 410 may operate at 2.4 GHz and the frequency synthesizer 412 may accordingly output a 2.4 GHz signal. The DDFS 422 b may utilize an appropriate frequency control word f_word2and the 2.4 GHz signal to generate, for example, a carrier frequency in the FM broadcast band, or approximately 60 MHz to 130 MHz.
A different frequency control word may be provided to each of the DDFSs 422 a and 422 b to enable generating a transmit frequency and a different receive frequency. Accordingly, the system may enable simultaneous transmission and reception of FM signals utilizing a single reference frequency.
FIG. 5 is an exemplary block diagram of simultaneous FM transmission and FM reception using a shared antenna and an integrated Bluetooth local oscillator generator, in accordance with an embodiment of the invention. Referring to FIG. 5, there is shown a communication system 500. The communication system 500 comprises a Bluetooth transceiver 502, a FM receiver 528, a FM transmitter 529, a processor 518, a bi-directional coupler 530 coupled to an antenna 532, a divider 510, a DDFS 512, a DAC 514, and a filter 516. The FM transmitter 529 may comprise a divider 520, a DDFS 522, a DAC 524, and a filter 526. The Bluetooth transceiver 502 may comprise a Bluetooth receiver 504, a Bluetooth transmitter 506 and a fractional synthesizer/PLL 508.
The PLL 508 may comprise suitable logic, circuitry, and/or code that may be enabled to generate a Bluetooth clock signal f_BTcomprising an in-phase (I) component f_BT _— _Iand a quadrature-phase (Q) component f_BT _— _Q. The I component and Q component signals may be communicated to the Bluetooth receiver 504 and the Bluetooth transmitter 506. The frequency of the generated Bluetooth clock signal f_BTto the Bluetooth receiver 504 and the Bluetooth transmitter 506 may be about 2.4 GHz, for example, and may be enabled to clock one or more of the Bluetooth receiver 504 and the Bluetooth transmitter 506. The PLL 308 may also be enabled to generate a clock signal f_LOto the plurality of dividers 510 and 520. The PLL 508 may comprise suitable logic, circuitry, and/or code that may be enabled to be utilized as frequency modulation (FM) demodulators, or carrier recovery circuits, or as frequency synthesizers for modulation and demodulation. The output of the PLL 507 may have a phase noise characteristic similar to that of the DDFSs 512 and 522, but may operate at a higher frequency.
The divider 510 may comprise suitable logic, circuitry, and/or code that may be enabled to divide a frequency of the generated clock signal f_LOinto one or more signals with different frequencies. For example, the divider 510 may be enabled to receive a 2.4 GHz input signal from the PLL 508 and generate a frequency divided clock signal, f_DIV _— _RX, which may be utilized to clock the DDFS 512. The frequency divided clock signal f_DIV _— _RXmay have a frequency of about 78-100 MHZ, for example. In an embodiment of the invention, the frequency of the frequency divided clock signal f_DIV _— _RXmay be equal to the frequency of the received FM signal f₁.
In an embodiment of the invention, the frequency divided clock signal, f_DIV _— _RX, may be communicated to the DDFS 512. The DDFS 512 may comprise suitable logic, circuitry and/or code that may enable reception of the frequency divided clock signal, f_DIV _— _RXand generate a sequence of binary numbers. The process of converting the frequency divided clock signal, f_DIV _— _RXto a sequence of binary numbers may comprise analog to digital conversion (ADC) whereby each distinct voltage, current and/or power level associated with the received frequency divided clock signal, f_DIV _— _RXmay be represented as a binary number selected from a plurality of binary numbers. Conversely, each binary number may correspond to a range of voltage, current and/or power levels in the received frequency divided clock signal, f_DIV _— _RX. An exemplary frequency divided clock signal, f_DIV _— _RXmay be a sinusoidal signal for which the corresponding period may be equal to the inverse of the frequency, (1/f_DIV _— _RX).
The number of binary numbers may be determined by the amount of bits, b, in the binary number representation. Each binary number may comprise a least significant bit (LSB) and a most significant bit (MSB). In an exemplary numerical representation, each of binary numbers may have a value within the range 0 to 2^b−1. The operation of the DDFS 512 may be such that a period of the received clock signal, f_LOmay be converted to a binary sequence 0, 1, . . . , 2^b−1, wherein upon reaching the value 2^b−1 the next number in the binary sequence may be 0 with the sequence continuing. The set of numbers from 0 to 2^b−1 may represent a period of the binary sequence. The DDFS 512 may receive a frequency control word, f_word1, from the processor 518 upon which the value of b may be determined. Consequently, the period of the sequence of binary numbers generated by the DDFS 512 may be programmable based on the f_Word1input signal.
The DAC 514 may comprise suitable logic, circuitry and/or code that may enable generation of an analog output signal based on a received sequence of input binary numbers. The DAC 514 may be enabled to generate a corresponding analog voltage level for each input binary number. The number of distinct analog voltage levels may be equal to the number of distinct binary numbers in the input sequence.
The filter 516 may comprise suitable logic, circuitry and/or code that may enable low pass filtering (LPF) of signal components contained in a received input signal. The filter 516 may enable smoothing of the received input signal to attenuate amplitudes for undesirable frequency components contained in the received input signal. The filter 516 may generate a signal, f_FM, having a frequency in the FM frequency band. In an exemplary embodiment of the invention, the range of frequencies for the signal f_FMmay be between about 78 MHz and 100 MHz, for example. The signal f_FMmay be a quadrature signal comprising I and Q signal components, f_FM _— _Xand f_FM _— _Qrespectively. The 78-100 MHz I and Q signals may be communicated to the FM receiver 528.
The divider 520 may comprise suitable logic, circuitry, and/or code that may be enabled to divide a frequency of the generated clock signal f_LOinto one or more signals with different frequencies. For example, the divider 520 may be enabled to receive a 2.4 GHz input signal from the PLL 508 and generate a frequency divided clock signal, f_DIV _— _TX, which may be utilized to clock the DDFS 522. The frequency divided clock signal f_DIV _— _TXmay have a frequency of about 78-100 MHZ, for example. In an embodiment of the invention, the frequency of the frequency divided clock signal f_DIV _— _TXmay be equal to the frequency of the transmitted FM signal f₂.
In an embodiment of the invention, the frequency divided clock signal, f_DIV _— _TX, may be communicated to the DDFS 522. The DDFS 522 may comprise suitable logic, circuitry and/or code that may enable reception of the frequency divided clock signal, f_DIV _— _TXand generate a sequence of binary numbers. The process of converting the frequency divided clock signal, f_DIV _— _TXto a sequence of binary numbers may comprise analog to digital conversion (ADC) whereby each distinct voltage, current and/or power level associated with the received frequency divided clock signal, f_DIV _— _TXmay be represented as a binary number selected from a plurality of binary numbers. Conversely, each binary number may correspond to a range of voltage, current and/or power levels in the received frequency divided clock signal, f_DIV _— _TX. An exemplary frequency divided clock signal, f_DIV _— _TXmay be a sinusoidal signal for which the corresponding period may be equal to the inverse of the frequency, (1/f_DIV _— _TX).
The number of binary numbers may be determined by the amount of bits, b, in the binary number representation. Each binary number may comprise a least significant bit (LSB) and a most significant bit (MSB). In an exemplary numerical representation, each of binary numbers may have a value within the range 0 to 2^b−1. The operation of the DDFS 522 may be such that a period of the received clock signal, f_LOmay be converted to a binary sequence 0, 1, . . . , 2^b−1, wherein upon reaching the value 2^b−1 the next number in the binary sequence may be 0 with the sequence continuing. The set of numbers from 0 to 2^b−1 may represent a period of the binary sequence. The DDFS 522 may receive a frequency control word, f_word2, from the processor 518 upon which the value of b may be determined. Consequently, the period of the sequence of binary numbers generated by the DDFS 522 may be programmable based on the frequency control word f_Word2input signal.
In accordance with an embodiment of the invention, the FM receiver 528 may be enabled to receive FM signals at a particular frequency f₁. The DDFS 522 may be enabled to modulate the FM data by shifting the center frequency to Δf, where Δf=f₂−f₁, where f₂is the frequency of simultaneous transmission of FM data by the FM transmitter 529. The DDFS 522 may receive a frequency control word, f_word2, from the processor 518 to enable modulation of the FM data. In accordance with another embodiment of the invention, the DDFS 522 may be enabled to modulate the FM data by shifting the center frequency to Δf, where Δf=f₁−f₂. The DDFS 522 may receive a frequency control word, f_word2, from the processor 518 to enable modulation of the FM data. The DDFS 522 may be enabled to generate the output signal to the DAC 524 based on the received frequency control word f_word2from the processor 518.
The DAC 524 may comprise suitable logic, circuitry and/or code that may enable generation of an analog output signal based on a received sequence of input binary numbers. The DAC 524 may be enabled to generate a corresponding analog voltage level for each input binary number. The number of distinct analog voltage levels may be equal to the number of distinct binary numbers in the input sequence.
The filter 526 may comprise suitable logic, circuitry and/or code that may enable low pass filtering (LPF) of signal components contained in a received input signal. The filter 526 may enable smoothing of the received input signal to attenuate amplitudes for undesirable frequency components contained in the received input signal. The filter 526 may generate a signal, f₂, having a frequency in the FM frequency band. In an exemplary embodiment of the invention, the range of frequencies for the signal f₂may be between about 78 MHz and 100 MHz, for example. The signal f₂may be a quadrature signal comprising I and Q signal components, f₂ _— ₁and f₂ _— _Qrespectively.
In an exemplary embodiment of the invention, the FM transmitter 529 and the FM receiver 528 may be coupled to an antenna 532 via a bidirectional coupler 530. The bidirectional coupler 530 may couple the antenna 532 to the FM receiver 528 at a given time instant based on a received frequency control word f_word1such that the FM receiver 528 may receive signals via the antenna 532. The bidirectional coupler 530 may couple the antenna to the FM transmitter 529 at the same time instant under the control of a different frequency control word f_Word2to the DDFS 522, such that the FM transmitter 529 may transmit signals via the antenna 532.
In accordance with an embodiment of the invention, the value f_Wordmay be selected to maintain an approximately constant frequency for the signal f_FMdespite changes that may occur in the generated clock signal f_LO, which may occur due to frequency hopping in the Bluetooth communication signal. In this regard, the value of f_Wordmay be dynamically changed to maintain an approximately constant frequency.
In an exemplary embodiment of the invention, the FM transmitter 529 and the FM receiver 528 may be coupled to the antenna 532 via the bi-directional coupler 530 for simultaneous transmission and/or reception of FM signals. The bi-directional coupler 530 may couple the antenna 532 to the FM receiver 528 at a given time instant, such that the FM receiver 528 may receive signals via the antenna 532 at a particular frequency f₁under the control of a frequency control word f_word1generated by the processor 518. The bi-directional coupler 530 may couple the antenna 532 to the FM transmitter 529 at the same time instant under the control of a frequency control word f_word2generated by the processor 518.
FIG. 6 is a flowchart illustrating exemplary steps for simultaneous FM transmission and FM reception using a shared antenna and an integrated Bluetooth local oscillator generator, in accordance with an embodiment of the invention. In this regard, one or more of the exemplary steps shown in FIG. 6 may be performed by a system such as the SoC 400 illustrated in FIG. 4. Referring to FIG. 6, exemplary steps may begin at step 600. In step 602, an appropriate frequency to generate Bluetooth communication signals may be determined. For example, at start-up, the processor 430 (FIG. 4) may read a default frequency setting from the memory 428. In step 604, a PLL or a frequency synthesizer may be controlled/configured to generate the frequency determined in step 602. For example, the processor 430 may provide the value of N for a divide-by-N block of a PLL comprising the frequency synthesizer 412. In step 606, an appropriate frequency f₂for FM transmission and an appropriate frequency f₁for FM reception may be determined. For example, an external input may allow a user to configure desired FM transmission and receive frequencies. Alternatively, the processor 430 may read frequency settings from the memory 428.
In step 608, the FM Tx block 432 and the FM Rx block 426 may be configured to transmit and receive FM signals at the frequencies determined in step 606. In this regard, the processor 430 and/or the memory 428 may provide one or more frequency control words f_word1and f_word2to the DDFSs 422 a and 422 b respectively. Accordingly, the frequency control words f_word1and f_word2may be such that the DDFSs 422 a and 422 b output the frequencies determined in step 606 when clocked by the PLL frequency determined in step 602. Additionally in step 608, the processor 430 may provide one or more control signals to configure the FM Tx block 432 and the FM Rx block 426. For example, the FM Tx block 432 and the FM Rx block 426 may each comprise a digitally tunable bandpass filter that the processor 430 may configure to pass the FM frequencies determined in step 606. Control then passes to end step 610.
In accordance with an embodiment of the invention, a method and system for simultaneous FM transmission and FM reception using a shared antenna and an integrated Bluetooth local oscillator generator may be disclosed. In a chip 400 that handles communication of Bluetooth signals and FM signals, a clock signal f_LOmay be generated at a particular frequency, for example, 2.4 GHz to enable transmission and/or reception of Bluetooth signals. The PLL 508 may be enabled to generate the clock signal f_LOat the particular frequency.
A plurality of signals, for example, f_FMand f₂may be generated via a plurality of direct digital frequency synthesizers (DDFSs) 512 and 522 respectively, which enable simultaneous transmission of FM signals and reception of FM signals. The plurality of DDFSs 512 and 522 may be clocked by the generated clock signal f_LO. The processor 518 may be enabled to generate one or more frequency control words, for example, f_word1and f_word2for controlling the generation of the plurality of signals, for example, f_FMand f₂via the plurality of DDFSs 512 and 522 respectively. The processor 518 may be enabled to adjust one or more of the generated frequency control words, for example, f_word1and f_word2to compensate for changes in a frequency of the generated clock signal f_LO. The reception of the FM signals may occur at a first frequency f₁and the transmission of the FM signals may occur at a second frequency f₂. The plurality of dividers 510 and 520 may be enabled to divide the generated clock signal f_LOto generate a frequency divided clock signal f_DIV.
In one embodiment, the divider 510 in the receive path may generate a frequency divided clock signal f_DIV _— _RXto clock the DDFS 512. In another embodiment, the divider 520 in the transmit path may generate a frequency divided clock signal f_DIV _— _TXto clock the DDFS 522. Each of the generated plurality of signals, for example, f_FMand f₂may comprise an in phase (I) component f_FM _— _Iand f₂ _— _Irespectively, and a quadrature phase (Q) component f_FM _— _Qand f₂ _— _Qrespectively. The bi-directional coupler 530 may enable controlling of the simultaneous transmission of the FM signals and the reception of said FM signals.
Another embodiment of the invention may provide a machine-readable storage, having stored thereon, a computer program having at least one code section executable by a machine, thereby causing the machine to perform the steps as described above for simultaneous FM transmission and FM reception using a shared antenna and an integrated Bluetooth local oscillator generator.
Accordingly, the present invention may be realized in hardware, software, or a combination of hardware and software. The present invention may be realized in a centralized fashion in at least one computer system, or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software may be a general-purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein.
The present invention may also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods. Computer program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form.
While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.

Claims

1. A method for communicating signals, the method comprising:

in a chip that handles communication of Bluetooth signals and FM signals:

generating a clock signal at a particular frequency to enable transmission and/or reception of said Bluetooth signals; and

generating, via a plurality of direct digital frequency synthesizers (DDFSs), a plurality of signals which enable simultaneous transmission of said FM signals and reception of said FM signals, wherein said plurality of DDFSs are clocked by said generated clock signal.

2. The method according to claim 1, comprising generating one or more frequency control words for controlling said generation of said plurality of signals via said plurality of DDFSs.

3. The method according to claim 2, comprising adjusting said one or more generated frequency control words to compensate for changes in a frequency of said generated clock signal.

4. The method according to claim 1, wherein said reception of said FM signals occurs at a first frequency and said transmission of said FM signals occurs at a second frequency.

5. The method according to claim 1, comprising dividing said generated clock signal to generate a frequency divided clock signal.

6. The method according to claim 1, wherein each of said generated plurality of signals via said plurality of DDFSs comprises an in phase (I) component and a quadrature phase (Q) component.

7. The method according to claim 1, comprising controlling said simultaneous transmission of said FM signals and said reception of said FM signals via a bi-directional coupler.

8. The method according to claim 1, comprising generating said clock signal at said particular frequency utilizing a phase locked loop (PLL).

9. A system for communicating signals, the system comprising:

one or more circuits in a chip that handles communication of Bluetooth signals and FM signals:

said one or more circuits enable generation of a clock signal at a particular frequency to enable transmission and/or reception of said Bluetooth signals; and

said one or more circuits enable generation, via a plurality of direct digital frequency synthesizers (DDFSs), a plurality of signals which enable simultaneous transmission of said FM signals and reception of said FM signals, wherein said plurality of DDFSs are clocked by said generated clock signal.

10. The system according to claim 9, wherein said one or more circuits enable generation of one or more frequency control words for controlling said generation of said plurality of signals via said plurality of DDFSs.

11. The system according to claim 10, wherein said one or more circuits enable adjustment of said one or more generated frequency control words to compensate for changes in a frequency of said generated clock signal.

12. The system according to claim 9, wherein said reception of said FM signals occurs at a first frequency and said transmission of said FM signals occurs at a second frequency.

13. The system according to claim 9, wherein said one or more circuits enable division of said generated clock signal to generate a frequency divided clock signal.

14. The system according to claim 9, wherein each of said generated plurality of signals via said plurality of DDFSs comprises an in phase (I) component and a quadrature phase (Q) component.

15. The system according to claim 11, wherein said one or more circuits enable controlling of said simultaneous transmission of said FM signals and said reception of said FM signals via a bi-directional coupler.

16. The system according to claim 11, wherein said one or more circuits enable generation of said clock signal at said particular frequency utilizing a phase locked loop (PLL).

17. A machine-readable storage having stored thereon, a computer program having at least one code section for communicating signals, the at least one code section being executable by a machine for causing the machine to perform steps comprising:

in a chip that handles communication of Bluetooth signals and FM signals:

18. The machine-readable storage according to claim 17, wherein said at least one code section comprises code for generating one or more frequency control words for controlling said generation of said plurality of signals via said plurality of DDFSs.

19. The machine-readable storage according to claim 18, wherein said at least one code section comprises code for adjusting said one or more generated frequency control words to compensate for changes in a frequency of said generated clock signal.

20. The machine-readable storage according to claim 17, wherein said reception of said FM signals occurs at a first frequency and said transmission of said FM signals occurs at a second frequency.

21. The machine-readable storage according to claim 17, wherein said at least one code section comprises code for dividing said generated clock signal to generate a frequency divided clock signal.

22. The machine-readable storage according to claim 17, wherein each of said generated plurality of signals via said plurality of DDFSs comprises an in phase (I) component and a quadrature phase (Q) component.

23. The machine-readable storage according to claim 17, wherein said at least one code section comprises code for controlling said simultaneous transmission of said FM signals and said reception of said FM signals via a bi-directional coupler.

24. The machine-readable storage according to claim 17, wherein said at least one code section comprises code for generating said clock signal at said particular frequency utilizing a phase locked loop (PLL).