US20080220576A1 - Manufacturing method of anti-punch-through semiconductor device - Google Patents
Manufacturing method of anti-punch-through semiconductor device Download PDFInfo
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- US20080220576A1 US20080220576A1 US12/123,482 US12348208A US2008220576A1 US 20080220576 A1 US20080220576 A1 US 20080220576A1 US 12348208 A US12348208 A US 12348208A US 2008220576 A1 US2008220576 A1 US 2008220576A1
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- trench
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Definitions
- the present invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to an anti-punch-through semiconductor device and a manufacturing method thereof.
- the size of the entire circuit device is forced to be minimized to meet the requirement.
- the distance between devices also relatively reduces.
- the process problem due to the high integration of device may occur. Therefore, it is a common objective in the industry to produce a semiconductor device with small size, high integration and high quality.
- FIG. 1 is a schematic cross-sectional view of a conventional trench device.
- a plurality of trenches 102 is formed in the substrate 100 , and the trench device is disposed in the trench 102 .
- the trench devices are trench memories, and the trench memories includes a floating gate 104 , a dielectric layer 106 , and a control gate 108 .
- the trench device further includes a source/drain region 110 disposed in the substrate under the floating gate 104 , the dielectric layer 106 and the control gate 108 .
- the dopant may diffuse into the source/drain region 110 to extend the region, which may easily cause the abnormal electric punch-through in the adjacent source/drain regions 110 .
- the problem of the electric punch-through may cause abnormal electric connection between adjacent trench devices, which may result in low operation speed and low performance efficiency, and even short or open circuit of the devices. Accordingly, the yield and reliability of the whole process are adversely affected.
- the present invention is directed to a manufacturing method of an anti-punch-through semiconductor device, wherein an isolation region can be formed between adjacent source/drain regions to avoid electric punch-through between the devices from affecting the performance efficiency of the devices.
- Another objective of the present invention is to provide an anti-punch-through semiconductor device, wherein, the isolation region between the source/gate regions can avoid the electric punch-through between the devices.
- the present invention provides a manufacturing method of anti-punch-through semiconductor device. First, a substrate is provided. Next, an insulation layer is formed on the substrate. Next, the insulation layer is patterned to form a plurality of isolation regions. Next, a silicon layer is formed on the substrate to cover the isolation region. Next, a trench is formed between each adjacent isolation region. Thereafter, a trench device is formed in each trench. Moreover, the trench device further includes a source/drain region formed in the silicon layer under the trench and between two adjacent isolation regions.
- the material of the insulation layer is, for example, silicon oxide.
- the thickness of the insulation layer is, for example, about 100 ⁇ -1000 ⁇ .
- the shape of the isolation region includes block or parallel stripes.
- the method of forming the source/drain region is, for example, ion-implanting method.
- the trench device is, for example, a trench memory.
- a dielectric layer is formed on the silicon layer to cover the trench memory, and a conductive layer is formed on the dielectric layer.
- the present invention also provides an anti-punch-through semiconductor device, comprising a substrate, a plurality of trench devices and at least one insulation region.
- the trench device is disposed in the substrate, wherein the trench device includes a source/drain region, and the source/drain region is disposed in the bottom of the trench device.
- the insulation layer is disposed in the substrate and between the source/drain regions of each trench device.
- the thickness of the insulation layer is, for example, about 100 ⁇ -1000 ⁇ .
- the material of the insulation layer is, for example, silicon oxide.
- the shape of the isolation region includes block or parallel stripes.
- the trench device is, for example, a trench memory.
- an isolation region is formed between two adjacent trench devices, so as to avoid adjacent source/drain regions during the ion-implanting process of forming the doped polysilicon from the electric punch-though as the dopant diffuses into the source/drain region to extend the region. And, the problem of the low operation speed and low performance efficiency due to the electric punch-through and reduced yield and reliability of the whole process, can also be avoided.
- FIG. 1 is a schematic cross-sectional view of a conventional trench device.
- FIG. 2A to FIG. 2G are cross-sectional views showing the flowchart of fabricating the anti-punch-through semiconductor device.
- FIG. 2A to FIG. 2G are cross-sectional views showing the flowcharts of manufacturing the anti-punch-through semiconductor device according to the embodiment of the present invention.
- the trench memory is described in the following as an example.
- a substrate 200 is provided, and the substrate 200 is, for example, a silicon substrate.
- an insulation layer 202 is formed on the substrate 200 .
- the material of the insulation layer is, for example, silicon oxide
- the thickness of the insulation layer 202 is about 100 ⁇ -1000 ⁇
- the forming method is, for example, a chemical vapor deposition process.
- the insulation layer 202 is patterned by photolithography process and etching process, and an isolation region 204 is formed on the substrate 200 .
- the isolation region is different from the shallow trench isolation structure used to form the active region.
- the isolation region of the present invention is formed deeper in the substrate than the shallow trench isolation structure.
- the shape of the isolation region 204 includes block or parallel stripes.
- a silicon layer 206 is formed on the substrate 200 to cover the isolation region 204 .
- the method of forming the silicon layer 206 is, for example, a chemical vapor deposition process.
- the silicon layer 206 is planarized, and the method of the planarization is, for example, a chemical mechanical polishing process.
- a patterned mask layer 208 is formed on the silicon layer 206 .
- the material of the patterned mask layer 208 is, for example, silicon nitride.
- the silicon layer 206 is etched to form the trench 210 in the silicon layer 206 between two adjacent isolation regions 204 by using the patterned mask layer 208 as a mask.
- a tunnel oxide layer 212 is formed on the surface of the trench 210 .
- the material of the tunnel oxide layer 212 is, for example, silicon oxide
- the method of forming the tunnel oxide layer 212 is, for example, a thermal oxidation process.
- a conductive layer 214 is formed on the silicon layer 206 and fills in the trench 210 .
- the material of the conductive layer 214 is, for example, doped polysilicon
- the forming method is, for example, by performing an ion-planting process after a non-doped polysilicon layer is formed in a chemical vapor deposition process.
- the conductive layer 214 is removed from the patterned mask layer 208 .
- the removing method is, for example, a chemical mechanical polishing process.
- an etching back process is performed to etch a part of conductive layer 214 , so that the top of the conductive layer 214 is higher than the surface of the silicon layer 206 and lower than the surface of the patterned mask layer 208 .
- a spacer 216 is formed to cover a part of the surface of the conductive layer 214 .
- the method of forming the spacer 216 is, for example, by forming an insulation material layer (not shown), then removing a part of the insulation material layer in a non-isotropic etching process.
- an etching process is performed to form a floating gate 218 on the sidewall of the trench 210 by using the patterned mask layer 208 and the spacer 216 as the mask.
- a source/drain region 220 is formed in the substrate 200 on the bottom of the trench 210 , and the source/drain region 220 is disposed between two adjacent isolation regions 204 .
- the method of forming the source/drain region 220 is, for example, an ion-planting process.
- a dielectric layer 222 is formed on the substrate 200 .
- the dielectric layer 222 can be a compound layer composed of silicon oxide layer, silicon nitride layer and silicon oxide layer in sequence from the bottom up. Of course, the dielectric layer 222 can also include only silicon oxide layer/silicon nitride layer or only a silicon oxide layer.
- the method of forming the dielectric layer 222 is, for example, a chemical vapor deposition process.
- a part of the tunnel oxide layer 212 and the dielectric layer 222 disposed on the bottom of the trench 210 are removed to expose the substrate 200 .
- the removing method is, for example, a non-isotropic etching process.
- a doped polysilicon layer (not shown) is formed on the substrate 200 , and a part of the doped polysilicon layer is removed in a chemical mechanical polishing process to form the control gate 224 .
- the tunnel oxide layer 212 , the floating gate 218 , the dielectric layer 222 , the control gate 224 and the source/drain region 220 are called a trench device 225 .
- the patterned mask layer 208 is removed.
- a dielectric layer 226 is formed on the trench device 225 and the silicon layer 206 .
- the material of the dielectric layer 226 is, for example, silicon oxide.
- a conductive layer 228 is formed on the dielectric layer 226 .
- the material of the conductive layer 228 is, for example, doped polysilicon. In the embodiment, the conductive layer 228 is used as word line.
- the isolation region is provided between the source/drain regions in two adjacent trench devices, the abnormal electric punch-through between two source/drain region, which affects the performance of the devices, can be avoided by the isolation region.
- an isolation region is formed between the source/drain under two adjacent trench memories, therefore, with increased integration, in the process of forming the gate with the material of doped polysilicon, the implanted dopant can be prevented from diffusing into the source/drain region to extend the source/drain region resulting in abnormal electric punch-through between adjacent devices. Meanwhile, the problem of short or open circuit of the devices resulting from the electric punch-through, which may reduce the yield and reliability of the whole process, can also be avoided.
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
An anti-punch-through semiconductor device is provided. The anti-punch-through semiconductor device includes a substrate, at least an isolation region and a plurality of trench devices. The trench device is disposed in the substrate. The trench device includes a source/drain region. The source/drain region of the trench device is disposed at the bottom of the trench device. The isolation region is disposed in the substrate and between the source/drain regions of each trench device.
Description
- This application is a divisional application of prior filed application Ser. No. 11/164,825, filed on Dec. 7, 2005, now allowed, which claims the priority benefit of Taiwan application serial no. 94122056, filed on Jun. 30, 2005. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
- 1. Field of Invention
- The present invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to an anti-punch-through semiconductor device and a manufacturing method thereof.
- 2. Description of Related Art
- Along with the rapid development of the integrated circuit industry and the trend of high integration, the size of the entire circuit device is forced to be minimized to meet the requirement. When the size of the semiconductor reduces gradually, the distance between devices also relatively reduces. When the distance reduces to some degree, the process problem due to the high integration of device may occur. Therefore, it is a common objective in the industry to produce a semiconductor device with small size, high integration and high quality.
-
FIG. 1 is a schematic cross-sectional view of a conventional trench device. Referring toFIG. 1A , a plurality oftrenches 102 is formed in thesubstrate 100, and the trench device is disposed in thetrench 102. The trench devices are trench memories, and the trench memories includes afloating gate 104, adielectric layer 106, and acontrol gate 108. Moreover, the trench device further includes a source/drain region 110 disposed in the substrate under thefloating gate 104, thedielectric layer 106 and thecontrol gate 108. - However, along with increased integration, in the process of forming the gate made of doped polysilicon, the dopant may diffuse into the source/
drain region 110 to extend the region, which may easily cause the abnormal electric punch-through in the adjacent source/drain regions 110. The problem of the electric punch-through may cause abnormal electric connection between adjacent trench devices, which may result in low operation speed and low performance efficiency, and even short or open circuit of the devices. Accordingly, the yield and reliability of the whole process are adversely affected. - Accordingly, the present invention is directed to a manufacturing method of an anti-punch-through semiconductor device, wherein an isolation region can be formed between adjacent source/drain regions to avoid electric punch-through between the devices from affecting the performance efficiency of the devices.
- Another objective of the present invention is to provide an anti-punch-through semiconductor device, wherein, the isolation region between the source/gate regions can avoid the electric punch-through between the devices.
- The present invention provides a manufacturing method of anti-punch-through semiconductor device. First, a substrate is provided. Next, an insulation layer is formed on the substrate. Next, the insulation layer is patterned to form a plurality of isolation regions. Next, a silicon layer is formed on the substrate to cover the isolation region. Next, a trench is formed between each adjacent isolation region. Thereafter, a trench device is formed in each trench. Moreover, the trench device further includes a source/drain region formed in the silicon layer under the trench and between two adjacent isolation regions.
- In the manufacturing method of anti-punch-through semiconductor device according to the embodiment of the present invention, the material of the insulation layer is, for example, silicon oxide.
- In the manufacturing method of anti-punch-through semiconductor device according to the embodiment of the present invention, the thickness of the insulation layer is, for example, about 100 Å-1000 Å.
- In the manufacturing method of anti-punch-through semiconductor device according to the embodiment of the present invention, the shape of the isolation region includes block or parallel stripes.
- In the manufacturing method of anti-punch-through semiconductor device according to the embodiment of the present invention, the method of forming the source/drain region is, for example, ion-implanting method.
- In the manufacturing method of anti-punch-through semiconductor device according to the embodiment of the present invention, the trench device is, for example, a trench memory.
- In the manufacturing method of anti-punch-through semiconductor device according to the embodiment of the present invention, after the trench memory is formed, a dielectric layer is formed on the silicon layer to cover the trench memory, and a conductive layer is formed on the dielectric layer.
- The present invention also provides an anti-punch-through semiconductor device, comprising a substrate, a plurality of trench devices and at least one insulation region. The trench device is disposed in the substrate, wherein the trench device includes a source/drain region, and the source/drain region is disposed in the bottom of the trench device. The insulation layer is disposed in the substrate and between the source/drain regions of each trench device.
- According to the anti-punch-through semiconductor device in the embodiment of the present invention, the thickness of the insulation layer is, for example, about 100 Å-1000 Å.
- According to the anti-punch-through semiconductor device in the embodiment of the present invention, the material of the insulation layer is, for example, silicon oxide.
- According to the anti-punch-through semiconductor device in the embodiment of the present invention, the shape of the isolation region includes block or parallel stripes.
- According to the anti-punch-through semiconductor device in the embodiment of the present invention, the trench device is, for example, a trench memory.
- In the present invention, an isolation region is formed between two adjacent trench devices, so as to avoid adjacent source/drain regions during the ion-implanting process of forming the doped polysilicon from the electric punch-though as the dopant diffuses into the source/drain region to extend the region. And, the problem of the low operation speed and low performance efficiency due to the electric punch-through and reduced yield and reliability of the whole process, can also be avoided.
- In order to the make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
-
FIG. 1 is a schematic cross-sectional view of a conventional trench device. -
FIG. 2A toFIG. 2G are cross-sectional views showing the flowchart of fabricating the anti-punch-through semiconductor device. -
FIG. 2A toFIG. 2G are cross-sectional views showing the flowcharts of manufacturing the anti-punch-through semiconductor device according to the embodiment of the present invention. The trench memory is described in the following as an example. - First, referring to
FIG. 2A , asubstrate 200 is provided, and thesubstrate 200 is, for example, a silicon substrate. Next, aninsulation layer 202 is formed on thesubstrate 200. Wherein, the material of the insulation layer is, for example, silicon oxide, and the thickness of theinsulation layer 202 is about 100 Å-1000 Å, and the forming method is, for example, a chemical vapor deposition process. - Next, referring to
FIG. 2B , theinsulation layer 202 is patterned by photolithography process and etching process, and anisolation region 204 is formed on thesubstrate 200. Note that the isolation region is different from the shallow trench isolation structure used to form the active region. The isolation region of the present invention is formed deeper in the substrate than the shallow trench isolation structure. Moreover, the shape of theisolation region 204 includes block or parallel stripes. - Next, referring to
FIG. 2B , asilicon layer 206 is formed on thesubstrate 200 to cover theisolation region 204. Wherein, the method of forming thesilicon layer 206 is, for example, a chemical vapor deposition process. Next, thesilicon layer 206 is planarized, and the method of the planarization is, for example, a chemical mechanical polishing process. Next, a patternedmask layer 208 is formed on thesilicon layer 206. Wherein, the material of the patternedmask layer 208 is, for example, silicon nitride. Thereafter, thesilicon layer 206 is etched to form thetrench 210 in thesilicon layer 206 between twoadjacent isolation regions 204 by using the patternedmask layer 208 as a mask. - Next, referring to
FIG. 2C , atunnel oxide layer 212 is formed on the surface of thetrench 210. Wherein, the material of thetunnel oxide layer 212 is, for example, silicon oxide, and the method of forming thetunnel oxide layer 212 is, for example, a thermal oxidation process. Next, aconductive layer 214 is formed on thesilicon layer 206 and fills in thetrench 210. Wherein, the material of theconductive layer 214 is, for example, doped polysilicon, and the forming method is, for example, by performing an ion-planting process after a non-doped polysilicon layer is formed in a chemical vapor deposition process. - Next, referring to
FIG. 2D , theconductive layer 214 is removed from the patternedmask layer 208. Wherein, the removing method is, for example, a chemical mechanical polishing process. Next, an etching back process is performed to etch a part ofconductive layer 214, so that the top of theconductive layer 214 is higher than the surface of thesilicon layer 206 and lower than the surface of the patternedmask layer 208. Next, aspacer 216 is formed to cover a part of the surface of theconductive layer 214. Wherein, the method of forming thespacer 216 is, for example, by forming an insulation material layer (not shown), then removing a part of the insulation material layer in a non-isotropic etching process. - Next, referring to
FIG. 2E , an etching process is performed to form a floatinggate 218 on the sidewall of thetrench 210 by using the patternedmask layer 208 and thespacer 216 as the mask. Next, a source/drain region 220 is formed in thesubstrate 200 on the bottom of thetrench 210, and the source/drain region 220 is disposed between twoadjacent isolation regions 204. Wherein, the method of forming the source/drain region 220 is, for example, an ion-planting process. Next, adielectric layer 222 is formed on thesubstrate 200. Wherein, thedielectric layer 222 can be a compound layer composed of silicon oxide layer, silicon nitride layer and silicon oxide layer in sequence from the bottom up. Of course, thedielectric layer 222 can also include only silicon oxide layer/silicon nitride layer or only a silicon oxide layer. The method of forming thedielectric layer 222 is, for example, a chemical vapor deposition process. - Next, referring to
FIG. 2F , a part of thetunnel oxide layer 212 and thedielectric layer 222 disposed on the bottom of thetrench 210 are removed to expose thesubstrate 200. Wherein, the removing method is, for example, a non-isotropic etching process. Next, a doped polysilicon layer (not shown) is formed on thesubstrate 200, and a part of the doped polysilicon layer is removed in a chemical mechanical polishing process to form thecontrol gate 224. In the embodiment, note that thetunnel oxide layer 212, the floatinggate 218, thedielectric layer 222, thecontrol gate 224 and the source/drain region 220 are called atrench device 225. - Next, referring to
FIG. 2G , the patternedmask layer 208 is removed. Next, adielectric layer 226 is formed on thetrench device 225 and thesilicon layer 206. Wherein, the material of thedielectric layer 226 is, for example, silicon oxide. Then, aconductive layer 228 is formed on thedielectric layer 226. Wherein, the material of theconductive layer 228 is, for example, doped polysilicon. In the embodiment, theconductive layer 228 is used as word line. - Moreover, in the trench memory (as shown in
FIG. 2G ) provided by the present invention, as an isolation region is provided between the source/drain regions in two adjacent trench devices, the abnormal electric punch-through between two source/drain region, which affects the performance of the devices, can be avoided by the isolation region. - In summary, an isolation region is formed between the source/drain under two adjacent trench memories, therefore, with increased integration, in the process of forming the gate with the material of doped polysilicon, the implanted dopant can be prevented from diffusing into the source/drain region to extend the source/drain region resulting in abnormal electric punch-through between adjacent devices. Meanwhile, the problem of short or open circuit of the devices resulting from the electric punch-through, which may reduce the yield and reliability of the whole process, can also be avoided.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (7)
1. A manufacturing method of anti-punch-through semiconductor device, comprising:
providing a substrate;
forming an insulation layer on the substrate;
patterning the insulation layer to form a plurality of isolation regions;
forming a silicon layer on the substrate to cover the isolation regions;
forming a plurality of trenches between each adjacent isolation region; and
forming a trench device in each trench, wherein the trench device further comprises a source/drain region formed in the silicon layer under the trench and disposed between two adjacent isolation regions.
2. The method of claim 1 , wherein the material of the insulation layer comprises silicon oxide.
3. The method of claim 1 , wherein the thickness of the insulation layer is about 100 Å-1000 Å.
4. The method of claim 1 , wherein the shape of the isolation region includes blocks or parallel stripes.
5. The method of claim 1 , wherein the method of forming the source/drain region comprises an ion-implanting method.
6. The method of claim 1 , wherein the trench device includes trench memory.
7. The method of claim 6 , further comprising:
forming a dielectric layer on the silicon layer to cover the trench memory after the trench memory is formed; and
forming a conductive layer on the dielectric layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US12/123,482 US20080220576A1 (en) | 2005-06-30 | 2008-05-20 | Manufacturing method of anti-punch-through semiconductor device |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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TW94122056 | 2005-06-30 | ||
TW094122056A TWI269363B (en) | 2005-06-30 | 2005-06-30 | Anti-punch-through semiconductor device and manufacturing method thereof |
US11/164,825 US7442980B2 (en) | 2005-06-30 | 2005-12-07 | Anti-punch-through semiconductor device |
US12/123,482 US20080220576A1 (en) | 2005-06-30 | 2008-05-20 | Manufacturing method of anti-punch-through semiconductor device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US11/164,825 Division US7442980B2 (en) | 2005-06-30 | 2005-12-07 | Anti-punch-through semiconductor device |
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US20080220576A1 true US20080220576A1 (en) | 2008-09-11 |
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US11/164,825 Active 2026-04-26 US7442980B2 (en) | 2005-06-30 | 2005-12-07 | Anti-punch-through semiconductor device |
US12/123,482 Abandoned US20080220576A1 (en) | 2005-06-30 | 2008-05-20 | Manufacturing method of anti-punch-through semiconductor device |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US11/164,825 Active 2026-04-26 US7442980B2 (en) | 2005-06-30 | 2005-12-07 | Anti-punch-through semiconductor device |
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TW (1) | TWI269363B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080142875A1 (en) * | 2006-02-04 | 2008-06-19 | Chungho Lee | Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4890144A (en) * | 1987-09-14 | 1989-12-26 | Motorola, Inc. | Integrated circuit trench cell |
US5504025A (en) * | 1994-05-18 | 1996-04-02 | United Microelectronics Corp. | Method of fabricating a read-only memory cell configuration having steep trenches |
US5763310A (en) * | 1996-10-08 | 1998-06-09 | Advanced Micro Devices, Inc. | Integrated circuit employing simultaneously formed isolation and transistor trenches |
US5821591A (en) * | 1996-02-02 | 1998-10-13 | Siemens Aktiengesellschaft | High density read only memory cell configuration and method for its production |
US6660592B2 (en) * | 2001-11-21 | 2003-12-09 | Mosel Vitelic, Inc. | Fabricating a DMOS transistor |
-
2005
- 2005-06-30 TW TW094122056A patent/TWI269363B/en not_active IP Right Cessation
- 2005-12-07 US US11/164,825 patent/US7442980B2/en active Active
-
2008
- 2008-05-20 US US12/123,482 patent/US20080220576A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4890144A (en) * | 1987-09-14 | 1989-12-26 | Motorola, Inc. | Integrated circuit trench cell |
US5504025A (en) * | 1994-05-18 | 1996-04-02 | United Microelectronics Corp. | Method of fabricating a read-only memory cell configuration having steep trenches |
US5821591A (en) * | 1996-02-02 | 1998-10-13 | Siemens Aktiengesellschaft | High density read only memory cell configuration and method for its production |
US5763310A (en) * | 1996-10-08 | 1998-06-09 | Advanced Micro Devices, Inc. | Integrated circuit employing simultaneously formed isolation and transistor trenches |
US6660592B2 (en) * | 2001-11-21 | 2003-12-09 | Mosel Vitelic, Inc. | Fabricating a DMOS transistor |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080142875A1 (en) * | 2006-02-04 | 2008-06-19 | Chungho Lee | Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes |
US9159568B2 (en) * | 2006-02-04 | 2015-10-13 | Cypress Semiconductor Corporation | Method for fabricating memory cells having split charge storage nodes |
Also Published As
Publication number | Publication date |
---|---|
US7442980B2 (en) | 2008-10-28 |
US20070001257A1 (en) | 2007-01-04 |
TWI269363B (en) | 2006-12-21 |
TW200701327A (en) | 2007-01-01 |
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