US20080087633A1 - Method for forming a metal line and method for manufacturing display substrate having the metal line - Google Patents

Method for forming a metal line and method for manufacturing display substrate having the metal line Download PDF

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Publication number
US20080087633A1
US20080087633A1 US11/870,806 US87080607A US2008087633A1 US 20080087633 A1 US20080087633 A1 US 20080087633A1 US 87080607 A US87080607 A US 87080607A US 2008087633 A1 US2008087633 A1 US 2008087633A1
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gas
layer
etching
metal layer
low
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Inventor
Min-Seok Oh
Sang-Gab Kim
Yu-gwang Jeong
Seung-Ha Choi
Hong-Kee Chin
Shin-II Choi
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHIN, HONG-KEE, CHOI, SEUNG-HA, CHOI, SHIN-IL, JEONG, YU-GWANG, KIM, SANG-GAB, OH, MIN-SEOK
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/10—Etching compositions
    • C23F1/12—Gaseous compositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT

Definitions

  • the present invention relates to a method of manufacturing a display substrate and, more particularly, to a method of manufacturing a display substrate having a metal line exhibiting reduced resistance.
  • a liquid crystal display (“LCD”) apparatus includes a display substrate, a counter substrate, and a liquid crystal layer disposed between the display substrate and the counter substrate.
  • Gate lines and source lines whose longitudinal directions cross each other are formed on the display substrate.
  • the metal layer formed on the display substrate As display apparatus have become larger the RC delay of the metal layer formed on the display substrate has increased. To minimize the RC delay, the metal layer is formed by using aluminum having a low resistance. However, many defects may be generated in manufacturing an aluminum metal layer which also tends to exhibit a high contact resistance with other layers.
  • a double layer structure or a triple layer structure having a low resistivity metal layer may include an aluminum (Al) layer and a molybdenum (Mo) layer while the triple layer structure may include a first molybdenum (Mo) layer, an aluminum (Al) layer and a second molybdenum (Mo) layer.
  • the molybdenum layer is etched by using a chlorine based gas mixed with oxygen gas. Because the chlorine based gas mixed with oxygen has high reactivity, contamination may be a problem. In addition, the mixed gas reacts with aluminum forming an undesired aluminum oxide layer allowing a stringer of the aluminum layer to remain at the edge of a pattern.
  • a display substrate having an accurately formed metal layer of low resistance is made by depositing, on a base substrate, a low resistivity aluminum layer and then sequentially depositing an upper layer having molybdenum on the low resistivity metal layer.
  • a photoresist pattern having a linear shape is formed on the upper layer.
  • the upper layer is etched using a mixed gas with the photoresist pattern as a mask.
  • the low resistivity metal layer is etched using the photoresist pattern as the mask.
  • the mixed gas includes a chlorine based gas mixed with an additional gas having at least one of nitrogen gas, argon gas, helium gas and sulfur hexafluoride gas.
  • a gate insulating layer is formed on a base substrate, and a gate pattern having a gate line and a gate electrode is formed on the base substrate.
  • a source metal layer is formed by sequentially forming a lower layer, a low-resistivity layer, and an upper layer on the gate insulating layer.
  • a source pattern having a source line, a source electrode and a drain electrode is formed by etching the upper layer using a mixed gas including a chlorine based gas mixed with an additional gas having at least one of nitrogen gas, argon gas, helium gas and sulfur hexafluoride gas.
  • a protective insulating layer having a contact hole is formed in the protective insulating layer.
  • a pixel electrode electrically connected to the drain electrode through the contact hole is formed.
  • the lower layer has molybdenum formed on the gate insulating layer.
  • the low-resistivity metal layer has aluminum formed on the lower layer.
  • the upper layer has molybdenum formed on the low-resistivity metal layer.
  • the contact hole partially exposes the drain electrode.
  • etching of the molybdenum layer formed on the aluminum layer is performed so that a stringer that the aluminum layer includes may be removed.
  • FIGS. 1A to 1D are sectional views illustrating a method for forming a metal layer according to a first example embodiment of the present invention
  • FIG. 2 is a schematic view illustrating a reactive ion etcher in accordance with one embodiment of the present invention
  • FIG. 3 is scanning electron microscope images illustrating etching stringers according to a power density in etching conditions for upper molybdenum
  • FIG. 4 is a plan view illustrating a display substrate according to an example embodiment of the present invention.
  • FIGS. 5A to 8 are cross-sectional views illustrating a method for manufacturing a display substrate according to a second example embodiment of the present invention.
  • FIGS. 9 to 12 are cross-sectional views illustrating a method for manufacturing a display substrate according to a third example embodiment of the present invention.
  • Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected.
  • FIGS. 1A to 1D are sectional views illustrating a method for forming a metal layer according to a first example embodiment of the present invention.
  • FIG. 2 is a schematic view illustrating a reactive ion etcher (“RIE”) in accordance with one embodiment of the present invention.
  • RIE reactive ion etcher
  • an insulating layer 110 is formed on a base substrate 101 .
  • a metal line layer 120 is formed on the insulating layer 110 .
  • the metal line layer 120 includes a triple layer having a lower layer 121 , a low resistivity metal layer 122 , and an upper layer.
  • the lower layer 121 includes molybdenum or molybdenum alloy.
  • the low resistivity metal layer 122 includes aluminum or aluminum alloy.
  • the upper layer 123 includes molybdenum or molybdenum alloy.
  • a photoresist pattern 140 is formed to correspond to a metal line, via coating and patterning a photoresist layer on the metal line layer 120 .
  • the metal line layer 120 is dry-etched by using the photoresist pattern 140 .
  • a dry-etching process, a post-treatment process and an ashing process which will be explained, are performed by using the RIE illustrated in FIG. 2 .
  • the RIE 200 includes a vacuum chamber 210 , an RF generator 212 and a power supply part 214 , so that etches a substrate 100 by using an etching gas.
  • the vacuum chamber 210 includes a lower electrode 220 , a ground cover part 230 , an upper electrode 240 , a gas supply part 250 , and a vacuum pump part 260 .
  • the lower electrode 220 is disposed over the ground cover part 230 , and is connected to the RF generator 212 to receive an RF power.
  • the substrate 100 is disposed on the lower electrode 220 .
  • the upper electrode 240 is disposed over the lower electrode 220 , and is electrically connected to the vacuum chamber 210 directly. In this case, the upper electrode 240 may be replaced with the vacuum chamber 210 .
  • the lower electrode 220 is used as a cathode
  • the upper electrode 230 is used as an anode.
  • the gas supply part 250 provides a gas that will be used for the dry-etching, ashing and post-treatment processes into the vacuum chamber 210 .
  • the gas provided by the gas supply part 250 is discharged by the RF power, so that plasma is formed.
  • the vacuum pump part 260 emits the gas inside of the vacuum chamber 210 into an exterior, so that maintains the vacuum chamber 210 in a vacuum state.
  • the substrate 100 that has the photoresist pattern 140 formed on the substrate 100 is disposed on the lower electrode 220 in the vacuum chamber 210 .
  • the vacuum chamber 210 is set to a first dry-etching condition, and then, an oxygen layer (not shown) formed on the upper layer 121 is removed.
  • the first dry-etching condition is that a pressure is about 15 mT, a source power is about 2000 W, and the etching gas of 100BCl 3 is used.
  • the source power and the bias power that will be explained below are powers applied to the lower electrode 220 .
  • the vacuum chamber 210 is set to a second dry-etching condition, and then the upper layer 123 is etched.
  • the second dry-etching condition is that the pressure is about 15 mT, the source power density which is defined as the source power divided by an area of the electrode is between about 1 W/cm 2 and about 2 W/cm 2 , and the bias power density which is defined as the bias power divided by the area of the electrode is between about 0.3 W/cm 2 and about 0.6 W/cm 2 .
  • the area of the electrode is defined as the area of the lower electrode 220 .
  • the etching gas is a mixed gas including a chlorine based gas (for example, C 12 or HCl) mixed with an additional gas having one of nitrogen gas (N 2 ), argon gas (Ar), helium gas (He) and sulfur hexafluoride gas (SF 6 ). A ratio of the additional gas with respect to the chlorine based gas is between about 50% and about 200%.
  • the upper layer 123 is etched with the second dry-etching condition, to form the upper pattern 123 a.
  • the vacuum chamber 210 is set to a third dry-etching condition, and then the oxygen layer formed on the low-resistivity metal layer 122 is removed.
  • the third dry-etching condition is that the pressure is about 15 mT, the source power is about 2000 W, and the etching gas of 20C 12 /100BCl 3 that is the chlorine based gas mixed with BCl 3 is used.
  • the oxygen layer formed on the low-resistivity metal layer 122 is removed with the third dry-etching condition.
  • the vacuum chamber 210 is set to a fourth dry-etching condition, and then the low-resistivity metal layer 122 is etched.
  • the fourth dry-etching condition is that the pressure is between about 10 mT and about 30 mT, the source power density is between about 0.7 and about 1.8, and the bias power density is between about 0.7 and about 1.8.
  • the mixed gas that is the chlorine based gas mixed with one of BCl 3 gas, nitrogen gas (N 2 ) and argon gas (Ar) is used as the etching gas.
  • the mixed gas that is the chlorine based gas for example, C 12 or HCl
  • nitrogen gas (N 2 ) and argon gas (Ar) is used.
  • a ratio of nitrogen gas (N 2 ) or argon gas (Ar) with respect to the chlorine based gas is between about 50% and about 150%.
  • the low-resistivity metal layer 122 is etched with the fourth dry-etching condition, to form a low-resistivity pattern 122 a.
  • the vacuum chamber 210 is set to a fifth dry-etching condition, and then, the lower layer 121 is etched.
  • the fifth dry-etching condition is that the power is between about 15 mT and about 100 mT, the source power is about 1000 W.
  • the mixed gas that is the chlorine based gas mixed with the additional gas having one of nitrogen gas (N 2 ), argon gas (Ar), helium gas (He) and sulfur hexafluoride gas (SF 6 ) is used as the etching gas.
  • the ratio of the additional gas with respect to the chlorine based gas is about 200%.
  • the lower layer 121 is etched to form a lower pattern 121 a.
  • a metal line 120 a having the low resistance is formed on the base substrate 101 .
  • a chlorine ion remains on the base substrate 101 due to chlorine gas C 12 that the etching gas includes.
  • the chlorine ion remaining on the base substrate 101 is exposed to the atmosphere, the chlorine ion is reacted with moisture in the atmosphere to form hydrochloric acid (HCl).
  • HCl corrodes the low-resistivity pattern 122 a including aluminum (Al), so that line stringers occur.
  • the post-treatment process is performed to remove the chlorine ion remaining on the base substrate 101 .
  • at least one of H 2 gas and H 2 0 gas is provided into the vacuum chamber 210 .
  • H 2 gas or H 2 0 gas provided into the vacuum chamber 210 is dissociated by a plasma discharge to generate a hydrogen ion (H+).
  • the hydrogen ion (H+) is reacted with the chlorine ion remaining on the base substrate 101 , to generate hydrochloric acid (HCl).
  • HCl generated from the vacuum chamber 210 is generated and evaporated at the same time due to an equilibrium vapor pressure.
  • the evaporated HCl is emitted outside of the vacuum chamber 210 through the vacuum pump part 260 . Accordingly, the chlorine ion remaining on the base substrate 101 is removed, so that the corrosion of the low-resistivity pattern 122 a may be prevented.
  • the post-treatment process may be performed by using a fluorine (F) based gas in spite of H 2 gas or H 2 0 gas.
  • F fluorine
  • the fluorine based gas provided into the vacuum chamber 210 is discharged by the RF power, so that the plasma is formed.
  • fluorine radical is generated.
  • the fluorine radical has a better reactivity than the chlorine ion.
  • the fluorine radical is reacted with the low-resistivity pattern 122 a on an exposed surface of the low-resistivity pattern 122 a , to substitute the remaining chlorine ion.
  • a corrosion preventing layer including aluminum fluoride (AlF) is formed on the exposed surface of the low-resistivity pattern 122 a .
  • AlF aluminum fluoride
  • oxygen gas is provided into the vacuum chamber 210 , to perform the ashing process that removes the photoresist.
  • Tables 1, 2, and 3 show etching uniformity of the molybdenum layer with the etching conditions of the present example embodiment.
  • the etching uniformity means uniformity in etching quantity of the molybdenum layer.
  • the etching uniformity is a value of measuring surface topography after the etching process, to find out how uniformly the molybdenum layer is etched in the base substrate.
  • the surface topography having a lower value may be better in the uniformity.
  • Tables 1, 2 and 3 show results after etching the single molybdenum layer using a test substrate having the single molybdenum formed on the test substrate, when a nitrated silicon layer (g-SiNx), an amorphous silicon layer (a-Si) and an n + ion doped layer are sequentially formed.
  • Tables 1 and 2 show results after etching an upper molybdenum layer in the single molybdenum layer including Mo/Al/Mo layer.
  • Table 3 shows results after etching a lower molybdenum layer in the single molybdenum layer including Mo/Al/Mo layer.
  • the oxygen layer was removed before etching the single molybdenum layer.
  • the etching condition for removing the oxygen layer was that the pressure was about 15 mT, the source power was about 2000 W, and the etching gas of 100BCl 3 was used.
  • Example 1 Stacked layer Glass/g-SiN x /a-Si/n + a-Si/Mo Mo-t oxygen layer etching condition Pressure(15 mT), Source power(2000 W), Gas(100BCl 3 ), Size(20′′) Mo-t main etching condition Comparative Example 1
  • Example 2 Example 3 (#1) (T#1) (T#2) (T#3) 15 mT, 15 mT, 15 mT, 15 mT, 1500 W, 1500 W, 1500 W, 1500 W, 25Cl 2 /50O 2 25Cl 2 /50N 2 25Cl 2 /50Ar 2 25Cl 2 /50He Etching rate 3285 1450 1356 1537 [ ⁇ /min] Etching 3.7 5.2 3.7 7.9 uniformity [%] Table 1 shows results after etching the upper molybdenum layer (Mo-t) with a main etching condition that the pressure was about 15 mT, the source power was about 1500 W, and the ratio of the additional gas with
  • Comparative Example 1 (#1), the conventional etching gas, for example the chlorine based gas mixed with oxygen gas (O 2 ), was used. In that case, an etching rate (E/R) was about 3285 ⁇ /min and the etching uniformity was about 3.7%.
  • the conventional etching gas for example the chlorine based gas mixed with oxygen gas (O 2 )
  • an etching rate (E/R) was about 3285 ⁇ /min and the etching uniformity was about 3.7%.
  • Example 1 the etching gas including the chlorine based gas mixed with oxygen gas (O 2 ), was used. In that case, the etching rate (E/R) was about 1450 ⁇ /min and the etching uniformity was about 5.2%.
  • Example 2 the etching gas including the chlorine based gas mixed with argon gas (Ar), was used. In that case, the etching rate (E/R) was about 1356 ⁇ /min and the etching uniformity was about 3.7%.
  • Example 3 the etching gas including the chlorine based gas mixed with helium gas (He), was used.
  • the etching rate (E/R) was about 1537 ⁇ /min and the etching uniformity was about 7.9%.
  • Example 1 When Comparative Example 1 is compared with Examples 1, 2 and 3, the etching rate (E/R) in Examples 1, 2 and 3 is smaller than that of in Comparative Example 1, but Examples 1, 2 and 3 may be enough to be applied to the etching process.
  • the etching uniformity in Example 2 is substantially the same as that in Comparative Example 1, and the etching uniformity in Examples 1 and 3 is substantially same as that in Comparative Example 1.
  • Example 4 the etching rate (E/R) was about 2338 ⁇ /min and the etching uniformity was about 8.9%.
  • Example 5 the etching rate (E/R) was about 2406 ⁇ /min and the etching uniformity was about 7.5%.
  • Example 6 the etching rate (E/R) was about 2431 ⁇ /min and the etching uniformity was about 8.2%.
  • a selective ratio should be higher than in the main etching condition of the upper molybdenum layer (Mo-t) illustrated in Tables 1 and 2, to prevent the n + ion doped layer (n + a-Si) that is formed under the lower molybdenum layer (Mo-b) from being etched. Accordingly, the ratios of the pressure and the additional gas are increased.
  • Comparative Example 2 (#2), the conventional etching gas, for example the chlorine based gas mixed with oxygen gas (O 2 ), was used. In that case, an etching rate (E/R) was about 3509 ⁇ /min and the etching uniformity was about 6.8%.
  • E/R etching rate
  • Example 7 the etching gas including the chlorine based gas mixed with nitrogen gas (N 2 ), was used.
  • the etching rate (E/R) was about 1437 ⁇ /min and the etching uniformity was about 6.7%.
  • Example 8 the etching gas including the chlorine based gas mixed with argon gas (Ar), was used.
  • the etching rate (E/R) was about 1684 ⁇ /min and the etching uniformity was about 6.9%.
  • Example 9 the etching gas including the chlorine based gas mixed with helium gas (He), was used.
  • the etching rate (E/R) was about 1637 ⁇ /min and the etching uniformity was about 7.1%.
  • the etching uniformity in etching the upper and lower molybdenum layers (Mo-t, Mo-b) using the mixed gas including the chlorine based gas mixed with the additional gas having one of nitrogen gas (N 2 ), argon gas (Ar) and helium gas (He), is substantially same as that in etching the upper and lower molybdenum layers using conventional oxygen gas (O2).
  • FIG. 3 is scanning electron microscope (“SEM”) images illustrating etching stringers according to a power density in etching conditions for upper molybdenum.
  • the SEM pictures illustrated in FIG. 3 show a channel portion and a line portion, after etching the upper molybdenum layer having the Mo/Al/Mo layer with the corresponding source power density and bias power density conditions, and then sequentially etching the aluminum layer and the lower molybdenum layer.
  • Comparative Example 3 shows the channel and line portions, after etching the upper molybdenum layer with the condition that the source power density was about 0.365 W/cm 2 and the bias power density was about 0.122 W/cm 2 .
  • Comparative Example 4 shows the channel and line portions, after etching the upper molybdenum layer with the condition the source power density was about 0.73 W/cm 2 and the bias power density was about 0.244 W/cm 2 .
  • a surface of the etched metal pattern includes metal remnants, and the metal remnants having a stringer remain at an edge portion of the etched metal pattern.
  • Example 10 shows the line portion, after etching the upper molybdenum layer with the condition that the source power density was about 1.095 W/cm 2 and the bias power density was about 0.366 W/cm 2 .
  • Example 11 shows the channel and line portions, after etching the upper molybdenum layer with the condition that the source power density was about 1.825 W/cm 2 and the bias power density was about 0.61 W/cm 2 .
  • the surface and the edge portion of the etched metal pattern include little metal remnants.
  • the stringer due to the metal remnants does not occur in the power densities used in Example 10 and Example 11.
  • FIG. 4 is a plan view illustrating a display substrate according to an example embodiment of the present invention.
  • FIGS. 5A to 8 are cross-sectional views illustrating a method for manufacturing a display substrate according to a second example embodiment of the present invention.
  • FIGS. 5A and 5B are cross-sectional views illustrating the method for manufacturing the display substrate using a first mask.
  • a gate metal layer 310 is deposited on a base substrate 101 via a sputtering process.
  • the gate metal layer 310 includes a double layer having a low-resistivity metal layer 311 and an upper layer 312 .
  • the low-resistivity metal layer 311 includes aluminum or aluminum alloy
  • the upper layer 312 includes molybdenum or molybdenum alloy.
  • a first photoresist layer is formed on the gate metal layer 310 , and then the first photoresist layer is patterned using the first mask, to form a first photoresist pattern PR 1 .
  • the gate metal layer 310 is etched using the first photoresist pattern PR 1 , to form a gate pattern including a gate line GLn, a gate electrode GE and a storage common line STL.
  • the gate metal layer 310 may be wet-etched or dry-etched. Preferably, as explained above in FIGS. 1A to 1C , in etching the gate metal layer 310 , an oxygen layer of the upper layer 312 , the upper layer 312 , the oxygen layer of the low-resistivity metal layer 311 and the low-resistivity metal layer 311 are sequentially etched with the first to fourth dry-etching conditions.
  • FIGS. 6A to 6D are cross-sectional views illustrating the method for manufacturing the display substrate using a second mask.
  • a gate insulating layer 320 and a semiconductor layer 330 including a silicon nitride (SiNx) layer are formed on the base substrate 301 on which the gate pattern is formed, via a plasma enhanced chemical vapor deposition (“PECVD”) process.
  • the semiconductor layer 330 includes an active layer 331 having amorphous silicon (a-Si:H), and an ohmic contact layer 332 doped with n + ion at a high concentration.
  • the source metal layer 340 is deposited on the ohmic contact layer 332 .
  • the source metal layer 340 has a triple layer including a lower layer 341 , a low-resistivity metal layer 342 and an upper layer 343 sequentially formed.
  • the lower layer 341 includes molybdenum or molybdenum alloy
  • the low-resistivity metal layer includes aluminum or aluminum alloy
  • the upper layer includes molybdenum or molybdenum alloy.
  • a second photoresist layer is formed on the base substrate 301 on which the source metal layer 340 is formed, and then, a second photoresist pattern (PR 2 ) is formed by using the second mask having a slit.
  • the second photoresist pattern PR 2 includes a first picture pattern PR 21 and a second picture pattern PR 22 .
  • the first picture pattern PR 21 corresponds to an area in which a source electrode SE, a drain electrode DE, and a source line DLm of a switching element TFT are formed.
  • the second picture pattern PR 22 corresponds to an area in which a channel portion CH of the switching element TFT is formed, and the second picture pattern PR 22 has a thinner thickness than that of the first picture pattern PR 21 .
  • the source metal layer 340 is patterned by using the second photoresist pattern PR 2 , so that the source pattern having an electrode pattern 340 a and the source line DLm is formed.
  • the electrode pattern 340 a corresponds to the source and drain electrodes of the switching element TFT.
  • the source metal layer 340 is wet-etched.
  • the source metal layer 340 that is wet-etched may include a better accurate pattern than the source metal layer 340 that is etched with the first to fifth dry-etching conditions.
  • the semiconductor layer 330 is etched using the second photoresist pattern and the source pattern as a mask. Accordingly, semiconductor patterns 330 a and 330 b that are patterned along the source pattern, are formed under the source pattern.
  • the second photoresist pattern PR 2 is removed to have a predetermined thickness using an oxygen (O2) plasma discharge via the ashing process (or etch back process).
  • the electrode pattern 340 a corresponding to the channel portion CH of the switching element TFT is partially exposed via the ashing process.
  • a remaining pattern PR 23 of the second photoresist pattern PR 2 is formed on the area in which the source electrode SE, the drain electrode DE, and the source line DLm are formed, via the ashing process.
  • the exposed electrode pattern 340 a is dry-etched by using the remaining pattern PR 23 as the mask.
  • the upper layer 343 of the electrode pattern 340 a is etched with the first and second dry-etching conditions, as explained above in FIGS. 1A and 1B .
  • the oxygen layer formed on the upper layer 343 is etched with the first condition that the pressure is about 15 mT, the source power is about 2000 W, and the etching gas of 100BCl 3 is used.
  • the upper layer 343 is etched with the second dry-etching condition.
  • the second dry-etching condition is that the pressure is about 15 mT, the source power density is between about 1 W/cm 2 and about 2 W/cm 2 , and the bias power density is between about 0.3 W/cm 2 and about 0.6 W/cm 2 .
  • the mixed gas including the chlorine based gas is mixed with the additional gas having one of argon gas (Ar), nitrogen gas (N 2 ), helium gas (He) and sulfur hexafluoride gas (SF 6 ).
  • the ratio of the additional gas with respect to the chlorine based gas is between about 50% and about 200%.
  • the low-resistivity metal layer 342 of the electrode pattern 340 a is etched with the third and fourth dry-etching conditions.
  • the oxygen layer formed on the low-resistivity metal layer 342 is etched with the third dry-etching condition that the pressure is about 15 mT, the source power is about 2000 W and the etching gas of 20Cl 2 /100BCl 3 is used.
  • the low-resistivity metal layer 342 is etched with the fourth dry-etching condition.
  • the fourth dry-etching condition is that the pressure is between about 10 mT and 30 mT, the source power density is between about 0.7 W/cm 2 and about 1.8 W/cm 2 , and the bias power density is between about 0.7 W/cm 2 and about 1.8 W/cm 2 .
  • the mixed gas including the chlorine based gas mixed with argon gas (Ar) or nitrogen gas (N 2 ) is used as the etching gas.
  • the ratio of the argon gas (Ar) or nitrogen gas (N 2 ) with respect to the chlorine based bas is between about 50% and about 150%.
  • the lower layer 341 of the electrode pattern 340 a is etched with the fifth dry-etching condition.
  • the electrode pattern 340 a is patterned to be the source electrode SE and the drain electrode DE, via the dry-etching process mentioned above.
  • the ohmic contact layer 332 exposed between the source and drain electrodes SE and DE is dry-etched by using the source and drain electrodes SE and DE as the mask.
  • the channel portion CH through which the active layer 331 is exposed is formed between the source and drain electrodes SE and DE, so that the switching element TFT is formed.
  • the chlorine ion provided from the chlorine based etching gas is reacted with the low-resistivity metal layer 342 including aluminum or aluminum alloy, to remain on an exposed surface of the low-resistivity metal layer 342 .
  • the post-treatment process is performed to remove the remaining chlorine ion.
  • the surface of the low-resistivity metal layer 342 is prevented from being corroded, via the post-treatment process.
  • the post-treatment process is performed with the same condition as the first example embodiment.
  • FIG. 7 is a cross-sectional view illustrating the method for manufacturing the display substrate using a third mask.
  • FIG. 8 is a cross-sectional view illustrating the method for manufacturing the display substrate using a fourth mask.
  • a protective insulating layer 350 is formed on the base substrate 301 on which the switching element TFT is formed.
  • the protective insulating layer 350 includes the silicon nitride layer.
  • a contact hole 353 that partially exposes the drain electrode DE, is formed via a photolithography process using the third mask.
  • the protective insulating layer 350 including the silicon nitride layer is explained in the present example embodiment, but the protective insulating layer 350 may include an organic layer such as an acrylic material. In addition, the protective insulating layer 350 may include the double layer having the silicon nitride layer and the organic layer sequentially formed.
  • a transparent conductive material (not shown) is deposited on the protective insulating layer 350 in which the contact hole 353 is formed.
  • Examples of materials that can be used for the transparent conductive material may include indium tin oxide or indium zinc oxide. Accordingly, the transparent conductive material is connected to the drain electrode DE through the contact hole 353 .
  • the transparent conductive material is patterned by using the fourth mask, to form a pixel electrode PE.
  • the pixel electrode PE is electrically connected to the switching element TFT through a contact portion CNT.
  • FIGS. 9 to 12 are cross-sectional views illustrating a method for manufacturing a display substrate according to a third example embodiment of the present invention.
  • the same reference numerals will be used to refer to the same or like parts as those described in the second example embodiment and any further repetitive explanation concerning the above elements will be omitted.
  • FIG. 9 is a cross-sectional view illustrating the method for manufacturing the display substrate using a first mask and a second mask.
  • a gate pattern including a gate line GLn, a gate electrode GE and a storage common line STL is formed on a base substrate 301 by using the first mask.
  • the gate pattern includes a double layer having a low-resistivity metal layer 311 and an upper layer 312 .
  • the low-resistivity metal layer 311 includes aluminum or aluminum alloy
  • the upper layer 312 includes molybdenum or molybdenum alloy.
  • the gate metal layer 310 may be wet-etched or dry-etched.
  • the gate metal layer is sequentially etched with the first to fourth dry-etching conditions.
  • a gate insulating layer 320 , an active layer 331 and an ohmic contact layer 332 are sequentially formed on the base substrate 301 on which the gate pattern is formed.
  • a semiconductor layer 330 of the switching element TFT is formed by using a second photoresist pattern PR 2 which is patterned by the second mask.
  • FIGS. 10A and 10B are cross-sectional views illustrating the method for manufacturing the display substrate using a third mask.
  • a source metal layer 340 is formed on the base substrate 301 on which the semiconductor layer 330 of the switching element TFT is formed.
  • the source metal layer 340 including a triple layer having a lower layer 341 , a low-resistivity metal layer 342 and an upper layer 342 is sequentially formed.
  • the lower layer 341 includes molybdenum or molybdenum alloy
  • the low-resistivity metal layer 342 includes aluminum or aluminum alloy
  • the upper layer 342 includes molybdenum or molybdenum alloy.
  • the source metal layer 340 is etched by using a third photoresist pattern PR 3 that is patterned by the third mask, to form a source pattern including a source electrode SE, a drain electrode DE and a source line DLm.
  • the source metal layer 340 as explained above in FIGS. 1A to 1D , is etched with the first to fifth dry-etching conditions, to form the source pattern.
  • a channel portion CH is formed by using the source and drain electrodes SE and DE as a mask.
  • the base substrate 301 on which the channel portion CH is formed is treated via the post-treatment process, to prevent the low-resistivity metal layer 342 of the source pattern from being corroded.
  • FIGS. 11 and 12 are cross-sectional views illustrating the method for manufacturing the display substrate using a fourth mask and a fifth mask.
  • a protective insulating layer 350 is formed on the base substrate 301 on which the channel portion CH is formed, and a contact hole 353 is formed using the fourth mask.
  • a transparent conductive material is deposited to make contact with the drain electrode DE through the contact hole 353 .
  • the transparent conductive material is patterned using the fifth mask, to form a pixel electrode PE.
  • the mixed gas including the chlorine based gas for example, C 12 or HCl
  • the additional gas having one of nitrogen gas (N 2 ), argon gas (Ar), helium gas (He) and sulfur hexafluoride gas (SF 6 ) is used for dry-etching of the upper layer including molybdenum formed on the aluminum layer, so that the stringer remaining on the metal layer due to the etching gas including oxygen gas may be removed.
  • the etching condition is that the mixed gas including nitrogen gas (N 2 ), argon gas (Ar) or helium gas (He) is used, the source power density is between about 1 W/cm 2 and about 2 W/cm 2 , and the bias power density is between about 0.3 W/cm 2 and about 0.6 W/cm 2 , the stringer remaining on the metal layer may be remarkably enhanced. Accordingly, the line stringer of the low-resistivity line including aluminum is removed, so that the metal line may be more accurate.
  • N 2 nitrogen gas
  • Ar argon gas
  • He helium gas

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JP2015173159A (ja) * 2014-03-11 2015-10-01 東京エレクトロン株式会社 プラズマ処理装置、薄膜トランジスターの製造方法及び記憶媒体
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US10573669B2 (en) * 2017-12-14 2020-02-25 Boe Technology Group Co., Ltd. Method for fabricating array substrate, array substrate, and display device
JP2020128567A (ja) * 2019-02-07 2020-08-27 キオクシア株式会社 半導体製造装置および半導体装置の製造方法
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US20050173732A1 (en) * 2002-01-15 2005-08-11 Seung-Hee Yu Wire for a display device, a method for manufacturing the same, a thin film transistor array panel including the wire, and a method for manufacturing the same
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US20080081534A1 (en) * 2006-09-29 2008-04-03 Samsung Electronics Co., Ltd. Method for forming metal line and method for manufacturing display substrate by using the same
US7833075B2 (en) * 2006-09-29 2010-11-16 Samsung Electronics Co., Ltd. Method for forming metal line and method for manufacturing display substrate by using the same
US20110145801A1 (en) * 2009-12-14 2011-06-16 International Business Machines Corporation Using appropriate level of code to be executed in runtime environment using metadata describing versions of resources being used by code
JP2015173159A (ja) * 2014-03-11 2015-10-01 東京エレクトロン株式会社 プラズマ処理装置、薄膜トランジスターの製造方法及び記憶媒体
US9812501B2 (en) 2015-01-05 2017-11-07 Samsung Electronics Co., Ltd. Variable resistance memory devices and methods of manufacturing the same
TWI767002B (zh) * 2017-06-05 2022-06-11 日商東京威力科創股份有限公司 蝕刻方法及蝕刻裝置
US10573669B2 (en) * 2017-12-14 2020-02-25 Boe Technology Group Co., Ltd. Method for fabricating array substrate, array substrate, and display device
JP2020128567A (ja) * 2019-02-07 2020-08-27 キオクシア株式会社 半導体製造装置および半導体装置の製造方法
JP7166950B2 (ja) 2019-02-07 2022-11-08 キオクシア株式会社 半導体製造装置および半導体装置の製造方法

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