US20080018357A1 - Automatic termination circuit - Google Patents

Automatic termination circuit Download PDF

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Publication number
US20080018357A1
US20080018357A1 US11/458,320 US45832006A US2008018357A1 US 20080018357 A1 US20080018357 A1 US 20080018357A1 US 45832006 A US45832006 A US 45832006A US 2008018357 A1 US2008018357 A1 US 2008018357A1
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US
United States
Prior art keywords
termination
termination resistance
automatic
resistance
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/458,320
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English (en)
Inventor
James F. Peterson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell International Inc
Original Assignee
Honeywell International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell International Inc filed Critical Honeywell International Inc
Priority to US11/458,320 priority Critical patent/US20080018357A1/en
Assigned to HONEYWELL INTERNATIONAL INC. reassignment HONEYWELL INTERNATIONAL INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PETERSON, JAMES F.
Priority to DE602007004036T priority patent/DE602007004036D1/de
Priority to EP07112476A priority patent/EP1881604B1/fr
Priority to JP2007186454A priority patent/JP2008042901A/ja
Publication of US20080018357A1 publication Critical patent/US20080018357A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/38—Impedance-matching networks
    • H03H7/40—Automatic matching of load impedance to source impedance

Definitions

  • every PCB trace can effectively become a transmission line. It is not uncommon that each trace (that is, each corresponding load point) requires termination in order to prevent noise problems such as signal reflection, ringing, and signal overshoot or undershoot. In a point-to-point topology, a series termination at the source (driver) is an ideal way to terminate the circuit.
  • the impedance value of a terminating resistor is selected depending on the associated electronic component's buffer technology, signal driver strength, and PCB trace impedance levels.
  • the signal's driver strength can be represented by a source impedance or source resistance.
  • signal reflection occurs when the impedance of the signal driver does not effectively match an impedance level of the PCB trace connected to the signal driver.
  • these “source” terminations are typically placed as close as possible to a signal driver within the electronic component.
  • the impedance matching calculations are performed in early stages of the component design. Evaluations of preliminary designs are conducted in a laboratory setting by manual adjustments, often with experimental circuitry that attempts to simulate actual operating conditions. Configuring certain components, such as an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA), typically occurs during fabrication (for ASICs), startup, or reset events (for FPGAs) and is typically not adjustable during component operation. Further, adding termination circuitry is not always required, depending on the length of the transmission line (that is, PCB trace). When termination circuitry is included where it is not required, the termination circuitry may create an unnecessary burden on the operation of the electronic component.
  • ASIC application-specific integrated circuit
  • FPGA field-programmable gate array
  • an automatic termination circuit for electronic data transmission lines.
  • the automatic termination circuit includes an adjustable termination resistance device having an output terminal for connecting the adjustable termination resistance device to a transmission line, wherein the adjustable termination resistance device has an associated termination resistance.
  • the automatic termination circuit is operable to automatically adjust the termination resistance associated with the adjustable termination resistance device using feedback, wherein the feedback is based on at least an output voltage at the output terminal.
  • FIG. 1 is a block diagram of an embodiment of an electronic circuit incorporating at least one automatic termination circuit
  • FIG. 2 is a block diagram of an embodiment of an automatic termination circuit
  • FIG. 3 is a flow diagram illustrating a method of an embodiment for configuring at least one termination circuit in an electronic device.
  • FIG. 4 is a block diagram of an alternate embodiment of an electronic circuit.
  • FIG. 1 is a block diagram of an embodiment of an electronic circuit 100 , incorporating at least one automatic termination circuit.
  • the electronic circuit 100 comprises a logic device 102 and a load point 110 .
  • the logic device 102 further comprises a data signal source 108 , a device manager 106 , and an automatic termination circuit (ATC) 104 .
  • Examples of the logic device 102 include, without limitation, any programmable logic device such as an ASIC, an FPGA, a field-programmable object array (FPOA).
  • the device manager 106 resides within the logic device 102 and is responsible for the configuration and control of logic device 102 .
  • the data signal source 108 resides within the logic device 102 and maintains at least one source of data.
  • the ATC 104 is in communication with the device manager 106 and the data signal source 108 .
  • the ATC 104 is described further in connection with FIG. 2 .
  • the ATC 104 is coupled to a load point 110 by a transmission line (T LINE ) 112 .
  • the load point 110 receives one data signal on the T LINE 112 from the logic device 102 .
  • the load point 110 comprises at least one common logic receiver point for the logic device 102 .
  • the load point 110 receives any type of electronic signal data from a plurality of electronic devices, including any additional logic devices 102 , mounted on a printed wiring assembly board (PWBA; not shown).
  • PWBA printed wiring assembly board
  • the device manager 106 determines when and how to configure the ATC 104 for limiting signal reflections while the logic device 102 is in use.
  • the ATC 104 determines when and how to configure the ATC 104 for limiting signal reflections while the logic device 102 is in use.
  • several options are available. Operating the ATC 104 in an “automatic” or “auto” mode ensures that an optimum terminal resistance value is present at an output of the ATC 104 at all times. The optimum terminal resistance substantially matches a load impedance of the T LINE 112 . Additional options include disabling the ATC 104 if the trace length of the T LINE 112 does not introduce a significant amount of signal reflection.
  • Operating in a “command” mode sets the ATC 104 to one or more fixed terminal resistance values. The option of operating in “command” mode affords the opportunity to evaluate termination effectiveness and quality of the T LINE 112 .
  • FIG. 2 is a block diagram 200 of an embodiment of the ATC 104 of FIG. 1 .
  • ATC 104 comprises at least one output buffer 204 , an adjustable termination resistance device 202 having an associated termination resistance R TERM. , and a bias adjust circuit 206 .
  • the at least one output buffer 204 acts as a signal driver and has as an input to receive logical ones and zeros provided on a signal input line 220 .
  • the at least one output buffer 204 includes or has a drive strength that is accurately represented with a source resistance R S .
  • R S defines the drive strength provided to an input terminal of the ATC 104 from the data signal source 108 of FIG. 1 .
  • the bias adjust circuit 206 includes a configuration logic block 208 and a feedback logic block 210 .
  • the adjustable termination resistance device 202 comprises a field effect transistor (FET).
  • a source terminal of the FET used to implement the adjustable termination resistance device 202 is coupled to the at least one output buffer 204 .
  • a drain (output) terminal of such FET is coupled to a transmission line (T LINE ) 222 .
  • Z 0 represents a resistor to ground impedance of the T LINE 222 .
  • a gate terminal of the FET (used to implement the adjustable termination resistance device 202 ) is connected to the feedback logic 210 .
  • a feedback signal line is coupled between the output terminal of the adjustable termination resistance device 202 and the feedback logic block 210 in order to provide feedback to the bias adjust circuit 206 .
  • such feedback is based on at least the output voltage at an output terminal of the adjustable termination resistance device 202 (that is, V PORCH as described below).
  • Configuration logic block 208 receives several input signals from the device manager 106 of FIG. 1 , namely an enable input signal 212 , a fixed value input signal 214 , a trigger input signal 216 , and a mode input signal 218 .
  • a logical input signal (Logic IN) is supplied to the at least one output buffer 204 on the signal input line 220 .
  • the bias adjust circuit 206 receives at least one operating mode instruction from the device manager 106 on the mode input signal 218 .
  • the bias adjust circuit 206 enters either an “auto” mode or a “command” mode depending on the at least one operating mode instruction received from the device manager 106 .
  • trigger input 216 identifies when to evaluate V PORCH and is set by the device manager 102 .
  • V PORCH signifies a voltage level present at the output terminal of the adjustable termination resistance device 202 .
  • V PORCH When both enable input 212 and trigger input 216 each provide an active input signal, V PORCH is evaluated as a feedback signal to the feedback logic block 210 . Based on the value of V PORCH , the feedback logic block 210 supplies a biased voltage value to the adjustable termination resistance device 202 .
  • the feedback logic block 210 comprises a feedback amplifier. The biased voltage value is applied to the gate terminal of the adjustable termination resistance device 202 .
  • the adjustable termination resistance device 202 automatically adjusts a source to drain resistance (R SD ) across the source and the drain terminals of the adjustable termination resistance device 202 .
  • R SD source to drain resistance
  • the adjustable termination resistance device 202 retains a previously adjusted R TERM value.
  • the bias adjust circuit 206 regulates an amount by which the R TERM value of the adjustable termination resistance device 202 is adjusted. In one implementation, the bias adjust circuit 206 regulates R TERM until V PORCH is substantially half of the Logic IN signal on the signal input line 220 . At this point, an impedance level at the output terminal of the ATC 104 (that is, R TERM +R S ) substantially matches the load point impedance Z 0 of the T LINE 222 , and the T LINE 222 is considered ideally terminated (with respect to the load point 110 of FIG. 1 ).
  • the enable input signal 212 will be issued a disable (inactive) command from the device manager 106 of FIG. 1 .
  • the configuration logic 208 sets R TERM to a minimum value, and the ATC 104 is placed in a “non-terminated” state.
  • the device manager 106 issues at least one fixed value word on the fixed value input signal 214 .
  • the at least one fixed value word represents at least one fixed value for R TERM .
  • the configuration logic 208 instructs the feedback logic 210 to convert the at least one fixed value word to a corresponding biased voltage value for the gate terminal of the adjustable termination resistance device 202 .
  • the source to drain resistance across the source and drain terminals of the adjustable termination resistance device 202 automatically adjusts to substantially equal the at least one fixed value for R TERM .
  • the fixed value input signal 214 comprises at least three input lines. The at least three input lines provide at least eight possible combinations of fixed value words (that is, at least eight different options for fixed values of R TERM ).
  • FIG. 3 is a flow diagram illustrating a method 300 for configuring at least one termination circuit in an electronic device.
  • the particular embodiment of method 300 is described in connection with the electronic circuit 100 of FIG. 1 and the ATC 104 of FIG. 2 (though other embodiments are implemented in other ways).
  • at least a portion of the processing of the method 300 is performed by the bias adjust circuit 206 .
  • a primary function of the method 300 is to automatically adjust the value of R TERM as instructed by the mode input signal 218 .
  • the method 300 establishes a current state of the ATC 104 based on the enable input signal 212 (block 302 ). If the ATC 104 is not enabled, the adjustable termination resistance device 202 is placed in a Bypass Mode at block 306 . In one implementation, the FET of the adjustable termination resistance device 202 is fully turned on, which makes R TERM substantially equal to zero ohms. If the ATC 104 is enabled, then the method 300 determines if the ATC 104 has an Automatic Mode enabled (block 304 ). If the Automatic Mode is enabled, the method 300 waits for a trigger event (block 310 ). If the trigger input signal 216 is active and enabled, the method 300 continues at block 314 .
  • V PORCH (or some value indicative thereof) is evaluated by the bias adjust circuit 206 at block 314 .
  • the adjustable termination resistance device 202 automatically adjusts R TERM at block 316 until V PORCH is substantially half of the Logic IN signal present on the signal input line 220 .
  • the bias adjust circuit 206 automatically adjusts R TERM until the drive strength impedance R S +R TERM substantially match the load point impedance Z 0 of the T LINE 222 . If the Automatic Mode is enabled but the trigger input signal 216 is not active, R TERM retains its previous value. If the Automatic mode was not selected at block 304 , a fixed value is read from the fixed value input signal 214 at block 308 .
  • the ATC 104 is in Command Mode, and the bias adjust circuit 206 adjusts the R TERM value of the adjustable termination resistance device 202 based on the fixed value read from the fixed value input signal 214 .
  • FIGS. 1 through 3 illustrate one embodiment of the electronic circuit 100 , the ATC 104 , and the at least one associated method 300 , respectively. It is to be understood that other embodiments are implemented in other ways. Indeed, the ATC 104 illustrated in FIGS. 1 through 3 is adaptable for a wide variety of applications.
  • FIG. 4 is a block diagram of an alternative embodiment of the electronic circuit 100 , an electronic circuit 400 .
  • the embodiment of the electronic circuit 400 shown in FIG. 4 includes three or more ATCs 404 , three or more load points 410 , and three or more T LINES 412 .
  • the three ATCs 404 are individually referenced in FIG. 4 as ATC 404 1 , 404 2 , and 404 N , respectively.
  • the three load points 410 are individually referenced in FIG. 4 as load point 410 1 (load point 1 ), 410 2 (load point 2 ), and 410 N (load point N), respectively.
  • the three T LINES 412 are individually referenced in FIG. 4 as T LINE 412 1 , T LINE 412 2 , and T LINE 410 N , respectively. It is understood that the electronic circuit 400 is capable of accommodating any appropriate number of the ATCs 404 , the load points 410 , and the T LINES 412 (for example, at least three ATCs 404 , at least three load points 410 , and at least three T LINES 412 ) in a single electronic circuit 400 .
  • electronic circuit 400 further comprises a logic device 402 .
  • the logic device 402 includes a device manager 406 and three or more data signal sources 408 1 to 408 N . Similar to the electronic circuit 100 , the device manager 406 is responsible for the configuration and control of logic device 402 .
  • Each of the three or more data signal sources 408 1 to 408 N maintain at least one source of data for each of the ATCs 104 1 to 104 N .
  • Each of the ATCs 104 1 to 104 N are coupled to each of the load points 410 1 to 410 N by a respective T LINE 412 1 to T LINE 412 N .

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  • Dc Digital Transmission (AREA)
  • Logic Circuits (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
US11/458,320 2006-07-18 2006-07-18 Automatic termination circuit Abandoned US20080018357A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US11/458,320 US20080018357A1 (en) 2006-07-18 2006-07-18 Automatic termination circuit
DE602007004036T DE602007004036D1 (de) 2006-07-18 2007-07-13 Automatische Abschlussschaltung
EP07112476A EP1881604B1 (fr) 2006-07-18 2007-07-13 Circuit de terminaison automatique
JP2007186454A JP2008042901A (ja) 2006-07-18 2007-07-18 自動終端回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/458,320 US20080018357A1 (en) 2006-07-18 2006-07-18 Automatic termination circuit

Publications (1)

Publication Number Publication Date
US20080018357A1 true US20080018357A1 (en) 2008-01-24

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US11/458,320 Abandoned US20080018357A1 (en) 2006-07-18 2006-07-18 Automatic termination circuit

Country Status (4)

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US (1) US20080018357A1 (fr)
EP (1) EP1881604B1 (fr)
JP (1) JP2008042901A (fr)
DE (1) DE602007004036D1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013095567A1 (fr) * 2011-12-22 2013-06-27 Intel Corporation Terminaison non linéaire pour architecture d'entrée/sortie sur boîtier
US20130318266A1 (en) * 2011-12-22 2013-11-28 Thomas P. Thomas On-package input/output architecture
US9306390B2 (en) 2011-12-22 2016-04-05 Intel Corporation Distributed electrostatic discharge protection for an on-package input/output architecture

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5347538A (en) * 1991-03-14 1994-09-13 Bull S.A. Transceiver for bidirectional link, integrated circuit including the transceiver, and application to communication between units of a system
US6292028B1 (en) * 1998-08-25 2001-09-18 Takashi Tomita Output circuit for a transmission system
US6489837B2 (en) * 2000-10-06 2002-12-03 Xilinx, Inc. Digitally controlled impedance for I/O of an integrated circuit device
US6762620B2 (en) * 2002-05-24 2004-07-13 Samsung Electronics Co., Ltd. Circuit and method for controlling on-die signal termination
US6894543B2 (en) * 2003-04-22 2005-05-17 Broadcom Corporation Series terminated CMOS output driver with impedance calibration
US6980020B2 (en) * 2003-12-19 2005-12-27 Rambus Inc. Calibration methods and circuits for optimized on-die termination
US7196567B2 (en) * 2004-12-20 2007-03-27 Rambus Inc. Systems and methods for controlling termination resistance values for a plurality of communication channels
US7679397B1 (en) * 2005-08-05 2010-03-16 Altera Corporation Techniques for precision biasing output driver for a calibrated on-chip termination circuit

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19639230C1 (de) * 1996-09-24 1998-07-16 Ericsson Telefon Ab L M Ausgangspufferschaltkreis zur Ansteuerung einer Übertragungsleitung
DE10120070A1 (de) * 2001-04-24 2002-11-07 Siemens Ag Vorrichtung und Verfahren zum Anpassen der Leitungseigenschaften bei hochbitratigen Datenübertragungen
ATE415739T1 (de) * 2004-11-19 2008-12-15 Koninkl Philips Electronics Nv Einrichtung mit einer an einem ausgang einer verstärkerstufe angekoppelten lastleitung

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5347538A (en) * 1991-03-14 1994-09-13 Bull S.A. Transceiver for bidirectional link, integrated circuit including the transceiver, and application to communication between units of a system
US6292028B1 (en) * 1998-08-25 2001-09-18 Takashi Tomita Output circuit for a transmission system
US6489837B2 (en) * 2000-10-06 2002-12-03 Xilinx, Inc. Digitally controlled impedance for I/O of an integrated circuit device
US6762620B2 (en) * 2002-05-24 2004-07-13 Samsung Electronics Co., Ltd. Circuit and method for controlling on-die signal termination
US6894543B2 (en) * 2003-04-22 2005-05-17 Broadcom Corporation Series terminated CMOS output driver with impedance calibration
US6980020B2 (en) * 2003-12-19 2005-12-27 Rambus Inc. Calibration methods and circuits for optimized on-die termination
US7196567B2 (en) * 2004-12-20 2007-03-27 Rambus Inc. Systems and methods for controlling termination resistance values for a plurality of communication channels
US7679397B1 (en) * 2005-08-05 2010-03-16 Altera Corporation Techniques for precision biasing output driver for a calibrated on-chip termination circuit

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013095567A1 (fr) * 2011-12-22 2013-06-27 Intel Corporation Terminaison non linéaire pour architecture d'entrée/sortie sur boîtier
US20130318266A1 (en) * 2011-12-22 2013-11-28 Thomas P. Thomas On-package input/output architecture
CN104115086A (zh) * 2011-12-22 2014-10-22 英特尔公司 用于封装件上输入/输出架构的非线性端接
US9306390B2 (en) 2011-12-22 2016-04-05 Intel Corporation Distributed electrostatic discharge protection for an on-package input/output architecture
US9384163B2 (en) 2011-12-22 2016-07-05 Intel Corporation Non-linear termination for an on-package input/output architecture
US9519609B2 (en) * 2011-12-22 2016-12-13 Intel Corporation On-package input/output architecture
US10374419B2 (en) 2011-12-22 2019-08-06 Intel Corporation Distributed electrostatic discharge protection for an on-package input/output architecture

Also Published As

Publication number Publication date
EP1881604A1 (fr) 2008-01-23
DE602007004036D1 (de) 2010-02-11
JP2008042901A (ja) 2008-02-21
EP1881604B1 (fr) 2009-12-30

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AS Assignment

Owner name: HONEYWELL INTERNATIONAL INC., NEW JERSEY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PETERSON, JAMES F.;REEL/FRAME:017953/0404

Effective date: 20060718

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION