US20070257652A1 - Booster Circuit with Protection Function and Electric Device - Google Patents

Booster Circuit with Protection Function and Electric Device Download PDF

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Publication number
US20070257652A1
US20070257652A1 US11/739,269 US73926907A US2007257652A1 US 20070257652 A1 US20070257652 A1 US 20070257652A1 US 73926907 A US73926907 A US 73926907A US 2007257652 A1 US2007257652 A1 US 2007257652A1
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Prior art keywords
voltage
circuit
booster
switch
comparison
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US11/739,269
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English (en)
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Daiki Yanagishima
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Rohm Co Ltd
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Rohm Co Ltd
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Publication of US20070257652A1 publication Critical patent/US20070257652A1/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection

Definitions

  • the present invention relates to a booster circuit and an electric device, and particularly to a booster circuit having a protection function as well as an electric device provided with the booster circuit.
  • FIG. 10 is a circuit diagram showing a structure of a conventional booster circuit.
  • a booster circuit 102 includes a main unit 106 , capacitors C 1 and C 2 , and a clock circuit 105 .
  • Main unit 106 includes diodes D 1 and D 2 , and a level shift circuit 107 .
  • Booster circuit 102 shown in FIG. 10 is generally referred to as a charge pump circuit.
  • Main unit 106 further has terminals T 1 , T 2 , CP 1 and CP 2 .
  • Terminal T 1 is connected to a power supply node.
  • Terminal T 1 is supplied with a voltage VCC.
  • the “voltage” represents a potential difference with respect to a ground potential unless otherwise specified.
  • Capacitor C 1 is connected between terminals T 1 and T 2 .
  • Capacitor C 2 is connected between terminals CP 1 and CP 2 .
  • Diode D 1 has an anode and a cathode connected to terminals T 1 and CP 2 , respectively.
  • Diode D 2 has an anode and a cathode connected to terminals CP 2 and T 2 , respectively.
  • Level shift circuit 107 receives a clock signal from clock circuit 105 .
  • Level shift circuit 107 converts a voltage (e.g., 3 V) of the received clock signal to a higher voltage (e.g., 15 V), and provides the converted signal to terminal CP 1 .
  • level shift circuit 107 provides a voltage, e.g., of 15 V
  • terminal CP 2 attains the voltage of (VCC+15 ⁇ V 1 ) volts, where ⁇ V 1 represents a forward voltage (about 0.7 V) of diode D 1 .
  • a voltage VG on terminal T 2 is lower by a forward voltage (about 0.7 V) of diode D 2 than the voltage on terminal CP 2 .
  • ⁇ V 2 represents the forward voltage of diode D 2
  • voltage VG becomes equal to (VCC+15 ⁇ V 1 ⁇ V 2 ). Therefore, voltage VG is higher than voltage VCC.
  • Voltage VG is supplied to the load (not shown).
  • Capacitor C 1 functions to smoothen voltage VG. Therefore, voltage VG is kept higher than voltage VCC.
  • Japanese Patent Laying-Open No. 2002-204569 has disclosed a switching power supply provided with a charge pump circuit.
  • This switching power supply adjusts a voltage supplied from a battery to attain a predetermined magnitude.
  • the switching power supply boosts the adjusted input voltage by a predetermined gain rate to provide a desired voltage.
  • booster circuit 102 shown in FIG. 10 an excessive current flows through diodes D 1 and D 2 , e.g., when terminal T 2 (terminal CP 2 ) is short-circuited. This may damage diodes D 1 and D 2 .
  • Japanese Patent Laying-Open No. 2002-204569 has not disclosed a manner of protecting a charge pump circuit when an output voltage lowers due to, e.g., grounding of an output terminal of the charge pump circuit.
  • An object of the invention is to provide a booster circuit having a protection function as well as an electric device with this booster circuit.
  • a booster circuit of the invention includes a booster, a switch and a control circuit.
  • the booster boosts a first voltage supplied from a voltage power supply to a first node, and provides the boosted first voltage as a second voltage to a second node.
  • the switch is arranged between the voltage power supply and the first node, and is on at least during an operation of the booster.
  • the control circuit monitors the second voltage during the operation of the booster, and changes the switch from an on state to an off state when the control circuit detects abnormal lowering of the second voltage.
  • the control circuit includes a detecting unit and a switch setting circuit.
  • the detecting unit provides a first detection result indicative of detection of the abnormal lowering when the second voltage becomes lower than a first threshold voltage.
  • the switch setting circuit starts measurement of an elapsed time according to the first detection result, and changes the switch from the on state to the off state when the elapsed time exceeds a predetermined time.
  • the switch setting circuit stops the measurement of the elapsed time and keeps the switch in the on state when the second voltage rises to or above the first threshold voltage before the elapsed time exceeds the predetermined time.
  • the detecting unit provides a second detection result when the detecting unit detects that the second voltage becomes lower than a second threshold voltage lower than the first threshold voltage.
  • the switch setting circuit turns off the switch when the switch setting circuit receives the second detection result before the elapsed time exceeds the predetermined time.
  • the booster circuit further includes a first capacitor connected between the voltage power supply and the second node, and a second capacitor connected between third and fourth nodes.
  • the booster includes a first diode having an anode and a cathode connected to the first and third nodes, respectively, a second diode having an anode and a cathode connected to the third and second nodes, respectively, and a level shift circuit receiving a clock signal, changing an amplitude of the clock signal, and outputting the clock signal to the fourth node.
  • the detecting unit includes a first voltage divider circuit dividing the first voltage to produce a first comparison voltage, a second voltage divider circuit dividing a third voltage on the third node to produce a second comparison voltage, a third voltage divider circuit dividing the second voltage to produce a third comparison voltage, a first comparator making a comparison between the first and second comparison voltages to provide a result of the comparison as the first detection result, and a second comparator making a comparison between the first and third comparison voltages to provide a result of the comparison as the second detection result.
  • the first threshold voltage is lower than the second voltage appearing at a start of an operation of the booster.
  • an electric device includes a booster circuit.
  • the booster circuit includes a booster, a switch and a control circuit.
  • the booster boosts a first voltage supplied from a voltage power supply to a first node, and provides the boosted first voltage as a second voltage to a second node.
  • the switch is arranged between the voltage power supply and the first node, and is on at least during an operation of the booster.
  • the control circuit monitors the second voltage during the operation of the booster, and changes the switch from an on state to an off state when the control circuit detects abnormal lowering of the second voltage.
  • the control circuit includes a detecting unit and a switch setting circuit.
  • the detecting unit provides a first detection result indicative of detection of the abnormal lowering when the second voltage becomes lower than a first threshold voltage.
  • the switch setting circuit starts measurement of an elapsed time according to the first detection result, and changes the switch from the on state to the off state when the elapsed time exceeds a predetermined time.
  • the switch setting circuit stops the measurement of the elapsed time and keeps the switch in the on state when the second voltage rises to or above the first threshold voltage before the elapsed time exceeds the predetermined time.
  • the detecting unit provides a second detection result when the detecting unit detects that the second voltage becomes lower than a second threshold voltage lower than the first threshold voltage.
  • the switch setting circuit turns off the switch when the switch setting circuit receives the second detection result before the elapsed time exceeds the predetermined time.
  • the booster circuit further includes a first capacitor connected between the voltage power supply and the second node, and a second capacitor connected between third and fourth nodes.
  • the booster includes a first diode having an anode and a cathode connected to the first and third nodes, respectively, a second diode having an anode and a cathode connected to the third and second nodes, respectively, and a level shift circuit receiving a clock signal, changing an amplitude of the clock signal and outputting the clock signal to the fourth node.
  • the detecting unit includes a first voltage divider circuit dividing the first voltage to produce a first comparison voltage, a second voltage divider circuit dividing a third voltage on the third node to produce a second comparison voltage, a third voltage divider circuit dividing the second voltage to produce a third comparison voltage, a first comparator making a comparison between the first and second comparison voltages to provide a result of the comparison as the first detection result, and a second comparator making a comparison between the first and third comparison voltages to provide a result of the comparison as the second detection result.
  • the first threshold voltage is lower than the second voltage appearing at a start of an operation of the booster.
  • a major advantage of the invention is that damage to the booster circuit can be prevented when abnormality such as grounding of the output terminal occurs.
  • the invention can improve operation reliability of the electric device.
  • FIG. 1 is a schematic block diagram of an electric device with a booster circuit of an embodiment.
  • FIG. 2 is a circuit diagram showing a structure of a booster circuit 2 in FIG. 1 .
  • FIG. 3 shows a specific example of a structure of a switch SW in FIG. 2 .
  • FIG. 4 is a flowchart schematically illustrating a control operation of switch SW performed by a switch control circuit 8 shown in FIG. 2 .
  • FIG. 5 is a circuit diagram showing an example of a structure of switch control circuit 8 shown in FIG. 2 .
  • FIG. 6 is a waveform diagram illustrating an operation performed when switch SW is on in booster circuit 2 shown in FIG. 2 .
  • FIG. 7 is a waveform diagram illustrating an operation performed by switch control circuit 8 in FIG. 5 when a voltage VG in FIG. 2 abnormally lowers.
  • FIG. 8 is another waveform diagram illustrating an operation performed by switch control circuit 8 in FIG. 5 when voltage VG lowers.
  • FIG. 9 illustrates an operation waveform appearing when booster circuit 2 in FIG. 2 starts the operation.
  • FIG. 10 is a circuit diagram showing a structure of a conventional booster circuit.
  • FIG. 1 is a schematic block diagram of an electric device provided with a booster circuit of the embodiment.
  • an electric device 100 includes N-channel MOS transistors Q 1 and Q 2 , a control circuit 1 , a booster circuit 2 , drive circuits 3 and 4 , and a clock circuit 5 .
  • N-channel MOS transistor Q 1 has a drain connected to a power supply node, and receives on its drain a voltage VCC, e.g., of 50 V. Also, N-channel MOS transistor Q 1 has a source connected to a terminal TA, and has a gate receiving a drive signal provided from drive circuit 3 .
  • N-channel MOS transistor Q 2 has a drain connected to terminal TA as well as a source connected to a ground node. N-channel MOS transistor Q 2 receives on its gate a drive signal provided from drive circuit 4 .
  • Terminal TA is connected to a load, which is, e.g., a coil of a motor, a coil of a switching power supply or the like.
  • N-channel MOS transistor Q 1 When N-channel MOS transistor Q 1 is on and N-channel MOS transistor Q 2 is off, the voltage on terminal TA is substantially equal to voltage VCC. For turning on N-channel MOS transistor Q 1 , it is necessary that a voltage VG placed on the gate of N-channel MOS transistor Q 1 is higher than the voltage of terminal TA (nearly equal to voltage VCC) by a threshold voltage of N-channel MOS transistor Q 1 .
  • Booster circuit 2 boosts voltage VCC to voltage VG, e.g., of 60 V, and supplies voltage VG as the power supply voltage to drive circuit 3 .
  • control circuit 1 provides a signal to drive circuit 3
  • drive circuit 3 changes the voltage level (e.g., of several volts) of the input signal to the level of voltage VG, and outputs it.
  • N-channel MOS transistor Q 1 receives voltage VG on its gate.
  • Control circuit 1 provides a signal at a voltage level of several volts to drive circuit 4 .
  • Drive circuit 4 outputs a signal, e.g., at the same voltage level as the input signal, and thereby drives N-channel MOS transistor Q 2 .
  • Clock circuit 5 produces a clock signal CLK, and provides it to control circuit 1 and booster circuit 2 .
  • Clock signal CLK serves as a reference of operations of control circuit 1 and booster circuit 2 .
  • Control circuit 1 transmits a signal EN to booster circuit 2 .
  • signal EN at an H-level, e.g., of 3 V
  • booster circuit 2 operates.
  • signal EN is at an L-level, e.g., of 0 V, booster circuit 2 stops.
  • FIG. 2 is a circuit diagram showing a structure of booster circuit 2 in FIG. 1 .
  • booster circuit 2 includes capacitors C 1 and C 2 , and a main unit 6 .
  • Main unit 6 is, e.g., one semiconductor integrated circuit.
  • Main unit 6 has terminals T 1 , T 2 , CP 1 and CP 2 .
  • Capacitor C 1 is connected between terminals T 1 and T 2 .
  • Capacitor C 2 is connected between terminals CP 1 and CP 2 .
  • Main unit 6 includes a booster 9 , a switch SW and a switch control circuit 8 .
  • Booster 9 includes diodes D 1 and D 2 as well as a level shift circuit 7 .
  • Booster 9 and capacitors C 1 and C 2 form a so-called “charge pump circuit”.
  • Terminal T 1 receives voltage VCC from a power supply node (voltage supply).
  • Booster 9 boosts voltage VCC to provide voltage VG to terminal T 2 .
  • Switch SW is connected between terminal T 1 and an anode (node N 1 ) of diode D 1 .
  • Switch SW receives a signal CTRL from switch control circuit 8 , and performs switching between on and off states.
  • Diode D 1 has a cathode connected to terminal CP 2 .
  • Diode D 2 has an anode and a cathode connected to terminals CP 2 and T 2 , respectively.
  • Level shift circuit 7 receives clock signal CLK, and provides a clock signal CLK 1 to terminal CP 1 .
  • the voltage of clock signal CLK changes between zero and a voltage V 0 .
  • the voltage of clock signal CLK 1 changes between zero and a voltage VREG, which is higher than voltage V 0 . In this manner, level shift circuit 7 changes an amplitude of clock signal CLK.
  • Switch control circuit 8 receives voltages VCC, VD 1 and VG, and controls on and off of switch SW. For turning on switch SW, switch control circuit 8 sets signal CTRL to the H-level. For turning off switch SW, switch control circuit 8 sets signal CTRL to the L-level.
  • switch control circuit 8 When abnormal lowering of voltage VG is detected during the boosting of voltage VCC by booster 9 , switch control circuit 8 changes switch SW from the on state to the off state. Thereby, the anode of diode D 1 is electrically cut off from the power supply node. For example, when terminal T 2 (or terminal CP 2 ) is grounded, voltages VG and VD 1 lower. At this time, switch control circuit 8 changes switch SW from the on state to the off state. This can prevent flowing of excessive currents through diodes D 1 and D 2 when terminal T 2 (or terminal CP 2 ) is grounded.
  • Switch control circuit 8 receives signal EN. When signal EN is at the H-level, switch control circuit 8 performs the foregoing operation of controlling switch SW. When signal EN is at the L-level, switch control circuit 8 always sets signal CTRL at the L-level to keep switch SW in the off state.
  • FIG. 3 shows an example of a specific structure of switch SW in FIG. 2 .
  • switch SW includes a P-channel MOS transistor Q 3 , an N-channel MOS transistor Q 4 , resistances R 1 and R 2 , and a Zener diode ZD.
  • P-channel MOS transistor Q 3 has a source and a drain connected to terminal T 1 and an anode of diode D 1 , respectively.
  • One of ends of resistance R 1 and a cathode of Zener diode ZD are connected to terminal T 1 .
  • the other end of resistance R 1 and an anode of Zener diode ZD are connected to a gate of P-channel MOS transistor Q 3 .
  • Resistance R 2 is connected between a gate of P-channel MOS transistor Q 3 and a drain of N-channel MOS transistor Q 4 .
  • N-channel MOS transistor Q 4 has a source connected to a ground node, and receives signal CTRL provided from switch control circuit 8 on its gate.
  • N-channel MOS transistor Q 4 When signal CTRL is at the H-level, N-channel MOS transistor Q 4 is turned on. Therefore, the voltage on the gate of P-channel MOS transistor Q 3 becomes lower than voltage VCC. In this state, since a difference between the voltage on the gate of P-channel MOS transistor Q 3 and voltage VCC is larger than a threshold voltage of P-channel MOS transistor Q 3 , P-channel MOS transistor Q 3 is turned on. Therefore, the power supply node is electrically connected to the anode of diode D 1 .
  • N-channel MOS transistor Q 4 When signal CTRL is at the L-level, N-channel MOS transistor Q 4 is off. Since the voltage on the gate of P-channel MOS transistor Q 3 becomes equal to voltage VCC, P-channel MOS transistor Q 3 is off. Therefore, the power supply node is electrically cut off from the anode of diode D 1 .
  • Switch control circuit 8 shown in FIG. 2 will now be described in greater detail.
  • FIG. 4 is a flowchart schematically illustrating a control operation for switch SW performed by switch control circuit 8 shown in FIG. 2 .
  • switch control circuit 8 when processing starts, switch control circuit 8 first detects abnormality in voltage VG in step S 1 .
  • the abnormality in voltage VG means that voltage VG becomes lower than a certain threshold voltage (first threshold voltage).
  • switch control circuit 8 measures, based on clock signal CLK, a time elapsed since voltage VG becomes lower than the first threshold voltage. Thus, switch control circuit 8 performs a timer operation.
  • switch control circuit 8 determines whether the state in which voltage VG is abnormal has continued for a predetermined time or not. When the elapsed time exceeds the predetermined time, switch control circuit 8 determines that the abnormal state of voltage VG is continuing. In this case (YES in step S 3 ), switch control circuit 8 changes the level of a signal CTLR from the H-level to the L-level in step S 4 , and thereby turns off switch SW. Therefore, voltage VCC is not supplied to the anode of diode D 1 . Thus, booster circuit 2 stops the boosting operation in step S 4 .
  • switch control circuit 8 likewise executes the processing of steps S 1 and S 2 .
  • switch control circuit 8 detects that voltage VG rises to or above the first threshold during the time measurement, it determines that the abnormal state ends. In this case (NO in step S 3 ), switch control circuit 8 stops the measurement of the elapsed time, and controls switch SW to continue the on state.
  • switch control circuit 8 turns off switch SW only when voltage VG continuously keeps the level lower than the first threshold voltage for a certain time. Since switch control circuit 8 controls switch SW as described above, switch control circuit 8 can correctly detect the abnormal state.
  • FIG. 5 is a circuit diagram showing an example of a structure of switch control circuit 8 shown in FIG. 2 .
  • switch control circuit 8 includes a detecting unit 8 A and a timer latch circuit 8 B.
  • the timer latch circuit corresponds to the “switch setting circuit” in the invention.
  • Detecting unit 8 A includes resistance voltage divider circuits RA, RB and RC, and comparators 11 and 12 .
  • Resistance voltage divider circuit RA includes resistances R 11 and R 12 , which are connected in series between terminal T 1 and the ground node. Resistances R 11 and R 12 divide voltage VCC to generate a voltage VA (first comparison voltage).
  • Resistance voltage divider circuit RB includes resistances R 13 and R 14 , which are connected in series between terminal T 3 and the ground node. Resistances R 13 and R 14 divide voltage VD 1 to generate a voltage VB (second comparator voltage).
  • Resistance voltage divider circuit RC includes resistances R 15 and R 16 , which are connected in series between terminal T 2 and the ground node. Resistances R 15 and R 16 divide voltage VG to generate a voltage VC (third comparison voltage).
  • Comparator 11 makes a comparison between voltages VA and VB to provide a signal COMP 1 .
  • voltage VA is smaller than voltage VB
  • signal COMP 1 is at the L-level.
  • voltage VA is larger than voltage VB
  • signal COMP 1 is at the H-level.
  • Voltage VA is larger than voltage VB when voltage VG is lower than the first threshold voltage.
  • Comparator 12 makes a comparison between voltages VA and VC to provide a signal COMP 2 .
  • voltage VA is smaller than voltage VC
  • signal COMP 2 is at the L-level.
  • voltage VA is larger than voltage VC
  • signal COMP 2 is at the H-level.
  • Voltage VA is larger than voltage VC when voltage VG is lower than the second threshold voltage.
  • the second threshold voltage is lower than the first threshold voltage.
  • Timer latch circuit 8 B includes timers 13 and 14 , NAND circuit 15 , inverters 16 and 17 , an RS latch 18 and an NOR circuit 19 .
  • Timer 13 becomes active in response to reception of signal COMP 1 at the H-level, and thereby switches a signal TM 1 between the H- and L-levels in a cycle equal to an integral multiple of a period of clock signal CLK.
  • Timer 14 becomes active in response to reception of signal COMP 2 at the H-level, and thereby switches a signal TM 2 between the H- and L-levels in a cycle equal to an integral multiple of the period of clock signal CLK.
  • each of timers 13 and 14 is a frequency divider, and may have the same division ratio as the other.
  • Timers 13 and 14 are deactivated in response to reception of signals COMP 1 and COMP 2 , respectively. Thus, each of timers 13 and 14 stops time measurement when it receives corresponding signal COMP 1 or COMP 2 at the L-level.
  • NAND circuit 15 receives signals TM 1 and TM 2 .
  • Inverter 16 inverts the signal provided from NAND circuit 15 , and outputs the inverted signal.
  • Inverter 17 inverts signal EN provided from control circuit 1 in FIG. 1 , and outputs the inverted signal. As described above, signal EN is always at the H-level while switch control circuit 8 is operating.
  • RS latch 18 receives on its terminal /S the signal provided from inverter 16 , and receives on its terminal /R signal EN, where “/” represents inversion.
  • NOR circuit 19 receives a signal provided from a terminal Q of RS latch 18 and a signal provided from inverter 17 , and outputs signal CTRL.
  • detecting unit 8 A detects that voltage VG becomes lower than the first threshold voltage, it provides signal COMP 1 (i.e., a first detection result) at the H-level.
  • Timer latch circuit 8 B starts measurement of the elapsed time in response to signal COMP 1 at the H-level.
  • timer latch circuit 8 B changes switch SW shown in FIG. 2 from the on state to the off state.
  • timer latch circuit 8 B receives signal COMP 1 at the L-level. In this case, timer latch circuit 8 B stops measurement of the elapsed time, and keeps switch SW in the on state.
  • detecting unit 8 A provides signal COMP 2 (second detection result) at the H-level when it detects that voltage VG becomes lower than the second threshold voltage lower than the first threshold voltage.
  • Timer latch circuit 8 B turns off switch SW when it receives signal COMP 2 at the H-level before the elapsed time exceeds the predetermined time.
  • booster circuit 2 of this embodiment Operations of booster circuit 2 of this embodiment will now be described in greater detail. First, description will be given on an operation performed when booster circuit 2 is normal. Then, description will be given on an operation of switch control circuit 8 performed when voltage VG lowers.
  • FIG. 6 is a waveform diagram illustrating an operation performed when switch SW is on in booster circuit 2 in FIG. 2 .
  • the voltage of clock signal CLK changes from zero to voltage V 0 at time t 1 .
  • the voltage of clock signal CLK 1 also changes from zero to voltage VREG in response to change in voltage of clock signal CLK.
  • voltage V 0 is 3 V
  • voltage VREG is 15 V.
  • VD 1 on terminal CP 2 is equal to (VCC ⁇ V 1 ) where ⁇ V 1 represents the forward voltage of diode D 1 , and is about 0.7 V. Since capacitor C 2 is connected between terminals CP 1 and CP 2 , level shift circuit 7 changes the voltage on terminal CP 1 , and thereby changes the voltage on terminal CP 2 .
  • voltage VD 1 on terminal CP 2 changes from a voltage (VCC ⁇ V 1 ) to a voltage (VCC+VREG ⁇ V 1 ) at time t 1 .
  • voltage VD 1 rises a magnitude of voltage VREG from voltage (VCC ⁇ V 1 ) at time t 1 .
  • capacitor C 1 is connected between terminals T 1 and T 2 . Therefore, the rising of voltage VG between times t 1 and t 2 as well as the lowering of voltage VG between times t 2 and t 3 occur only to a small extent. Therefore, voltage VG is kept at the voltage higher than voltage VCC.
  • clock signals CLK and CLK 1 as well as voltages VD 1 and VG repeat the changes similar to those between times t 1 and t 3 . Therefore, description of the changes of clock signals CLK and CLK 1 as well as voltages VD 1 and VG after time t 3 is not repeated.
  • FIG. 7 is a waveform diagram illustrating an operation of switch control circuit 8 in FIG. 5 what is performed when voltage VG in FIG. 2 abnormally lowers.
  • the abnormal lowering of voltage VG occurs, e.g., due to grounding of terminal CP 2 , grounding of terminal T 2 and the like. In this case, voltage VG becomes lower than the lowest value of voltage VG illustrated in FIG. 6 .
  • both voltages VD 1 and VG lower after time t 10 .
  • Voltage VB lowers with lowering of voltage VD 1 .
  • voltage VC lowers with lowering of voltage VG. Since voltage VCC is constant, voltage VA is constant.
  • Voltage VG at time t 11 is represented as a voltage Vth 1 , which corresponds to the “first threshold voltage” in the invention.
  • clock signal CLK changes from the H-level to the L-level.
  • Timer 13 starts the measurement of time elapsed from time t 12 .
  • Timer 13 changes signal TM 1 from the H-level to the L-level at time t 14 after 4 T from time t 12 , where T in FIG. 7 represents one period of clock signal CLK.
  • voltage VG lowers more slowly than voltage VD 1 . Therefore, voltage VC changes more slowly than voltage VB. At time t 13 , voltage VC is lower than voltage VA. Therefore, signal COMP 2 changes from the L-level to the H-level at time t 13 . At time t 13 , voltage VG is equal to a voltage Vth 2 , which corresponds to a “second threshold voltage” in the invention.
  • Timer 14 starts the time measurement at time t 14 when clock signal CLK falls first after time t 13 .
  • the signal provided from terminal /S of RS latch 18 changes from the H-level to the L-level.
  • the signal provided from terminal Q of RS latch 18 changes from the L-level to the H-level at time t 14 .
  • NOR circuit 19 receives the signal at the L-level from inverter 17 (i.e., it receives the signal produced by inverting the logic level of signal EN). Therefore, signal CTRL changes from the H-level to the L-level at time t 14 . Thus, the switch shown in FIG. 2 changes from the on state to the off state at time t 14 . After signal CTRL once changes from the H-level to the L-level, it will keep the L-level.
  • timer latch circuit 8 B starts the measurement of the elapsed time in response to the change of signal COMP 1 from the L-level to the H-level.
  • timer latch circuit 8 B changes signal CTRL from the H-level to the L-level, and thereby changes switch SW from the on state to the off state.
  • FIG. 8 is another waveform diagram illustrating an operation that is performed by switch control circuit 8 in FIG. 5 when voltage VG lowers.
  • the time required for lowering the voltage value of voltage VG from Vth 1 to Vth 2 in FIG. 8 is shorter than the time required for lowering the voltage value of voltage VG from Vth 1 to Vth 2 in FIG. 7 .
  • the change in voltage VD 1 illustrated in FIG. 8 differs from the change in voltage VD 1 illustrated in FIG. 7 .
  • the change in voltage VD 1 in FIG. 8 is equal to that in FIG. 7 , for the sake of illustration.
  • Voltage VG reaches voltage Vth 2 at time t 1 A preceding time t 13 .
  • Signal COMP 2 changes from the L-level to the H-level at time t 1 A.
  • Timer 14 starts the time measurement at time t 1 B when first falling of clock signal CLK occurs after time t 1 A.
  • Signal TM 2 changes from the H-level to the L-level at time t 1 C when first falling of clock signal CLK occurs after time t 1 B.
  • the signal provided to terminal /S of RS latch 18 changes from the H-level to the L-level.
  • the signal provided from terminal Q of RS latch 18 changes from the L-level to the H-level at time t 1 C. Therefore, signal CTRL changes from the H-level to the L-level at time t 1 C preceding time t 14 .
  • timer latch circuit 8 B shown in FIG. 5 operates according to signal COMP 2 , and changes signal CTRL from the H-level to the L-level to turn off switch SW when voltage VC becomes lower than voltage VA during the measurement of the elapsed time from time t 12 (i.e., when voltage VC becomes lower than voltage VA at time t 1 A between times t 11 and t 14 ).
  • switch control circuit 8 turns off the switch in a short time after the lowering of voltage VG. Therefore, it is possible to minimize the time during which the overcurrents flow through diodes D 1 and D 2 . Therefore, damage to diodes D 1 and D 2 can be prevented.
  • switch control circuit 8 may erroneously detect that voltage VG is abnormal, at the start of the operation of booster circuit 2 .
  • FIG. 9 illustrates operation waveforms at the start of the operation of booster circuit 2 in FIG. 2 .
  • voltage VD 1 is lower than voltage VCC during periods between times t 21 and t 22 , between times t 23 and t 24 , and between times t 25 and t 26 .
  • Voltage VG is lower than voltage VCC during a period between times t 21 and t 24 , and changes to exceed voltage VCC during a period between times t 24 and t 25 .
  • Resistances R 11 -R 16 shown in FIG. 5 may be configured such that a resistance ratio between resistances R 13 and R 14 and a resistance ratio between resistances R 15 and R 16 are equal to that between resistances R 11 and R 12 , in which case voltages VB and VC are lower than voltage VA at the start of the operation of booster circuit 2 .
  • the resistance ratio between resistances R 13 and R 14 and the resistance ratio between resistances R 15 and R 16 are set such that voltages VB and VC are always higher than voltage VA when booster circuit 2 is normally operating.
  • the resistance ratio between resistances R 13 and R 14 and the resistance ratio between resistances R 15 and R 16 are set in view of the lowest values of voltages VD 1 and VG.
  • This setting of the resistance ratios means that the first threshold voltage (voltage Vth 1 ) is set lower than voltage VG appearing at the start of the operation of booster circuit 2 . Thereby, at the start of the operation of booster circuit 2 , switch control circuit 8 is prevented from erroneously determining that voltage VG is abnormal.
  • This embodiment employs a manner of changing the resistance ratios so that voltages VB and VC may exceed voltage VA.
  • comparators 11 and 12 may internally give offsets to voltages VB and VC.
  • the booster circuit includes the switch between the power supply node and the diode, and includes the control circuit controlling the switch. Therefore, the flow of overcurrents through the diodes can be prevented when the output terminal of the booster circuit is grounded.
  • the electric device since the electric device includes the booster circuit having the protection function described above, the reliability of operation can be further increased.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
US11/739,269 2006-05-02 2007-04-24 Booster Circuit with Protection Function and Electric Device Abandoned US20070257652A1 (en)

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JP2006-128212 2006-05-02
JP2006128212A JP2007300760A (ja) 2006-05-02 2006-05-02 昇圧回路および電気機器

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Cited By (4)

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Publication number Priority date Publication date Assignee Title
US20110006747A1 (en) * 2009-06-03 2011-01-13 Panasonic Corporation Step-up circuit and step-up circuit device
US20140092656A1 (en) * 2012-09-28 2014-04-03 Asahi Kasei Microdevices Corporation Power supply circuit
US8866515B2 (en) 2011-06-02 2014-10-21 Toyota Jidosha Kabushiki Kaisha Drive unit for driving voltage-driven element
US10403374B2 (en) * 2016-06-29 2019-09-03 Toshiba Memory Corporation Reduction of output voltage ripple in booster circuit

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102684180B (zh) * 2012-05-23 2015-07-01 乐鑫信息科技（上海）有限公司 一种用于nfc发射装置的电荷泵输出保护驱动装置
US11459061B2 (en) * 2019-01-12 2022-10-04 Sram, Llc Bicycle component motion control
JP7325352B2 (ja) * 2020-02-07 2023-08-14 エイブリック株式会社 基準電圧回路

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Publication number Priority date Publication date Assignee Title
US5151631A (en) * 1990-10-19 1992-09-29 Koito Manufacturing Co., Ltd. Lighting circuit for vehicular discharge lamp
US5485059A (en) * 1992-07-03 1996-01-16 Koito Manufacturing Co., Ltd. Lighting circuit for vehicular discharge lamp
US5629588A (en) * 1994-09-08 1997-05-13 Koito Manufacturing Co., Ltd. Lighting circuit utilizing DC power for a discharge lamp utilizing AC power
US6960903B2 (en) * 2003-07-30 2005-11-01 Favess Co., Ltd. Trouble determining apparatus for DC boosting circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5151631A (en) * 1990-10-19 1992-09-29 Koito Manufacturing Co., Ltd. Lighting circuit for vehicular discharge lamp
US5485059A (en) * 1992-07-03 1996-01-16 Koito Manufacturing Co., Ltd. Lighting circuit for vehicular discharge lamp
US5629588A (en) * 1994-09-08 1997-05-13 Koito Manufacturing Co., Ltd. Lighting circuit utilizing DC power for a discharge lamp utilizing AC power
US6960903B2 (en) * 2003-07-30 2005-11-01 Favess Co., Ltd. Trouble determining apparatus for DC boosting circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110006747A1 (en) * 2009-06-03 2011-01-13 Panasonic Corporation Step-up circuit and step-up circuit device
US7932710B2 (en) 2009-06-03 2011-04-26 Panasonic Corporation Step-up circuit and step-up circuit device
US8866515B2 (en) 2011-06-02 2014-10-21 Toyota Jidosha Kabushiki Kaisha Drive unit for driving voltage-driven element
US20140092656A1 (en) * 2012-09-28 2014-04-03 Asahi Kasei Microdevices Corporation Power supply circuit
US9853540B2 (en) * 2012-09-28 2017-12-26 Asahi Kasei Microdevices Corporation Power supply circuit
US10403374B2 (en) * 2016-06-29 2019-09-03 Toshiba Memory Corporation Reduction of output voltage ripple in booster circuit

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CN101068096A (zh) 2007-11-07

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