US20070035716A1 - Exposure method - Google Patents

Exposure method Download PDF

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US20070035716A1
US20070035716A1 US11/460,663 US46066306A US2007035716A1 US 20070035716 A1 US20070035716 A1 US 20070035716A1 US 46066306 A US46066306 A US 46066306A US 2007035716 A1 US2007035716 A1 US 2007035716A1
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exposure
electrical characteristic
parameter
exposure parameter
plural
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Hiroto Yoshii
Kenichiro Mori
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Canon Inc
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Assigned to CANON KABUSHIKI KAISHA reassignment CANON KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MORI, KENICHIRO, YOSHII, HIROTO
Publication of US20070035716A1 publication Critical patent/US20070035716A1/en
Priority to US12/402,095 priority Critical patent/US7771906B2/en
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70653—Metrology techniques
    • G03F7/70658—Electrical testing
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70058—Mask illumination systems
    • G03F7/70141—Illumination system adjustment, e.g. adjustments during exposure or alignment during assembly of illumination system
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70216—Mask projection systems
    • G03F7/70258—Projection system adjustments, e.g. adjustments during exposure or alignment during assembly of projection system
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/705—Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/70525—Controlling normal operating mode, e.g. matching different apparatus, remote control or prediction of failure

Definitions

  • the present invention relates generally to an exposure method, and more particularly to an optimization of an exposure condition.
  • a conventional projection exposure apparatus uses a projection optical system to expose a reticle (or mask) pattern onto a plate, such as a single crystal substrate for a semiconductor wafer, and a glass plate for a liquid crystal display.
  • a method for manufacturing a device such as a semiconductor chip (e.g., an LSI, a VLSI), a CCD, an LCD, a magnetic sensor, and a thin-film magnetic head), needs to improve the yield rate.
  • This device manufacturing method includes various processes, such as exposure, development, and etching.
  • a conventional exposure apparatus considers not only the resolution at which the reticle pattern precisely resolve on a plate to be exposed, but also the influence on the other processes in the device manufacturing method.
  • a reticle pattern is optimized, for example, through an optical proximity correction (“OPC”).
  • OPC optical proximity correction
  • CD critical dimension
  • a critical dimension (“CD”) uniformity is known as a general conventional evaluation index of the resolution.
  • JPC process proximity control
  • a simulation or a simulator may be used instead of actually exposing the plate for effective optimizations.
  • SPIE 5379-15 Design rule optimization for 65-nm-node (CMOS5) BEOL using process and layout decomposition methodology and Evert Seevinck, Frans J. List, and Jan Lohstroh, “Static-Noise Margin Analysis of MOS SRAM Cells,” IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, October (1987).
  • the above SPIE reference discloses a via chain as a test pattern under various design rules, measures the resistance, and determines whether the design rules and the OPC are properly set.
  • the device is defective as an electronic component depends upon the electrical characteristic of the device.
  • a typical example of the electrical characteristic is a power supply voltage characteristic that is defined as a voltage change of the device to the power supply, but the electrical characteristic may be durability, resistance, electric capacity, etc.
  • an illustrative electrical characteristic includes a static noise margin (“SNM”) (see the above IEEE reference), V TH difference in a transistor gate, etc.
  • SNM static noise margin
  • the electrical characteristic to be verified differs according to device types.
  • the evaluation index relating to the resolution does not always correspond to the electrical characteristic. For example, even when the CD uniformity is bad, the device is not defective in view of the electrical characteristic, and even when satisfying a predetermined CD uniformity, the device is defective in view of the electrical characteristic.
  • the present invention is directed to an exposure method that can manufacture a device as a final product with a good yield rate.
  • a database that stores a relationship used for the above exposure method, and a program for enabling a computer to implement the exposure method also constitute one aspect of the present invention.
  • FIG. 1 is a flowchart of an optimization algorithm according to the present invention.
  • FIG. 2 is a flowchart for explaining a device manufacturing method according to the present invention.
  • FIG. 3 is a flowchart of a step 4 shown in FIG. 2 .
  • FIG. 4 is a schematic block diagram of an exposure system that executes the optimization method shown in FIG. 1 .
  • FIG. 5 is a schematic block diagram as a variation of the exposure system shown in FIG. 4 .
  • FIG. 6 is a circuit diagram of an SRAM as one illustrative device manufactured in FIGS. 2 and 3 .
  • FIG. 7 is a graph for explaining a characteristic of static noise margin (“SNM”) in the SRAM shown in FIG. 6 .
  • SNM static noise margin
  • FIG. 8 is a circuit diagram of the SRAM shown in FIG. 6 that assumes a switching noise equivalent circuit.
  • FIG. 9 is a graph for explaining a size of SNM when a cell ratio is changed.
  • FIG. 10 shows a cell structure of the SRAM shown in FIG. 6 .
  • FIG. 11A to 11 E are layer structures in the SRAM shown in FIG. 10 .
  • FIGS. 12A to 12 D show a relationship between the gate line end shorting (“LES”) and NA.
  • FIGS. 13A-13C show a relationship between the gate LES and exposure dose.
  • FIGS. 14A and 14B show an overlay between a gate layer and a source/drain layer.
  • FIG. 1 is a flowchart of an optimization algorithm of this embodiment.
  • FIG. 4 shows an exposure system 1 that executes the optimization algorithm shown in FIG. 1 .
  • the exposure system 1 includes, as shown in FIG. 4 , a processing system 10 in a FAB (factory), input parts 20 a - 20 c , an operating system 30 , and exposure apparatuses 40 a - 40 d.
  • the processing system 10 obtains reticle data and exposure condition from the input parts 20 a to 20 c , and selects an appropriate one of the exposure apparatuses 40 a to 40 d .
  • the exposure apparatuses 40 a to 40 d have different characteristic data and specifications, such as a light source (ArF, KrF, EUV etc.), an exposure method (scanner, stepper, etc.), an illumination condition (polarization illumination, effective light source, etc.), and a projection optical system (dioptric, catadioptric, immersion system, etc.).
  • the processing system 10 has difference data among the same type of exposure apparatuses.
  • the processing system 10 previously obtains the characteristic data of the exposure apparatuses 40 a to 40 d , and stores them in a memory.
  • the operating system 30 is a computer that executes the optimization algorithm shown in FIG. 1 .
  • the operating system 30 obtains the characteristic data of the exposure apparatus selected from the processing system, and optimizes the exposure parameter based on the electrical characteristic of the device, if necessary.
  • the processing system 10 obtains the optimization information of the exposure parameter from the operating system 30 , and sets it in the exposure apparatus.
  • the processing system in the FAB and the operating system may be a single computer system inside or outside the FAB, or only the operating system may be located outside the FAB.
  • the optimization algorithm of this embodiment first obtains a relationship between an exposure parameter that determines a mode to expose a plate and an electrical characteristic of a device derived from the plate (step 1002 ).
  • This embodiment utilizes, for the electrical characteristic, a power supply voltage characteristic that is a voltage change of the device to the power supply.
  • the exposure parameter includes, for example, a numerical aperture (“NA”) of a projection optical system, an exposure dose, a focus, a Zernike coefficient, a pupil transmittance, an effective light source distribution, a telecentricity, a polarization degree, a polarization degree difference among image heights, a slit profile, a spectrum distribution of the light source, a longitudinal magnification, a lateral magnification, a shot rotation, and a decentering distortion.
  • NA numerical aperture
  • the electrical characteristic can be evaluated by utilizing a Monte Carlo simulation and sensitivity analysis (“MCSS”) as described later, without actually completing the device.
  • the device's electrical characteristic is likely to dramatically affect the yield rate as a memory cell size reduces in the future fine processing.
  • the following primary causes are influential to the electrical characteristic: Firstly, a difference amount due to the manufacturing factor can increase relative to the design size of the gate width and the gate length. Secondly, an ion implantation dose difference cannot be negligible as the gate size reduces. Thirdly, a difference of the gate film thickness and the gate film dielectric constant cannot be negligible.
  • a certain electrical characteristic relates to a specific evaluation index.
  • the line end shorting (“LES”), etc. deteriorate the yield rate.
  • the LES is a phenomenon of a non-resolution of a tip of a line pattern due to the focusing fluctuation.
  • the LES occurs with an insufficient OPC due to the device layout limitation.
  • a relationship between the LES and the electrical characteristic is, for example, such that the LES in the gate layer changes the electrical characteristic, such as resistance, due to the gate length.
  • Other factors for this type of phenomenon are a line edge roughness (LER) and a sidewall angle (“SWA”) relating to the SNM, and commonly influential on the electrical characteristic because they are likely to change the circuit shape.
  • LER line edge roughness
  • SWA sidewall angle
  • Step 1002 obtains the above relationship, for example, by measuring the electrical characteristic after producing the actual device with various different exposure parameters.
  • FIGS. 2 and 3 a description will be given of an embodiment of a device manufacturing method.
  • FIG. 2 is a flowchart for explaining how to manufacture semiconductor devices, such as semiconductor chips (ICs and LSIs), liquid crystal panels, and CCDs.
  • Step 1 circuit design
  • Step 2 reticle fabrication
  • Step 3 wafer preparation
  • Step 4 (wafer process), which is also referred to as a pretreatment, forms the actual circuitry on the wafer through lithography using the reticle and wafer.
  • Step 5 (assembly), which is also referred to as a posttreatment, forms into a semiconductor chip the wafer formed in Step 4 and includes an assembly step (e.g., dicing, bonding), a packaging step (chip sealing), and the like.
  • Step 6 (inspection) performs various tests on the semiconductor device made in Step 5 , such as a validity test and a durability test. Through these steps, a semiconductor device is finished and shipped (Step 7 ).
  • FIG. 3 is a detailed flowchart of the wafer process in Step 4 .
  • Step 11 oxidation
  • Step 12 CVD
  • Step 13 electrode formation
  • Step 14 ion implantation
  • Step 15 resist process
  • Step 16 exposure
  • Step 17 development
  • Step 18 etching
  • Step 19 resist stripping
  • Step 20 electrical characteristic measurement
  • an initial state of the exposure parameter is set (step 1004 ).
  • the initial state of the exposure parameter may be set such that a large exposure margin is secured.
  • step 1006 it is determined whether the device obtained from the exposure parameter has a predetermined electrical characteristic. For this determination, a test chip may be actually manufactured and its electrical characteristic may be measured. The simulation may use, for example, the MCSS for each layer of the device.
  • the SRAM is used for a cash memory that connects the CPU to the DRAM, accelerating the processing speed, and enhancing the high speed and efficiency of the entire system.
  • the DRAM needs refreshing at regular time periods, whereas the SRAM uses an electronic circuit called “flip-flop.” As long as the power is supplied, the data can be statically stored without refreshing.
  • FIG. 6 shows a general circuit diagram of the SRAM.
  • a word line WL is turned to H (high: voltage is applied), and NMOS transistors Qn 3 and Qn 4 turn on.
  • a switch turns on in the NMOS transistor Qn 2 and a PMOS transistor Op 1 .
  • “1” is written down in a left node and “0” is written down in a right node.
  • BL 1 is in the L state and BL 2 is in the H state
  • “0” is written down in a left node and “1” is written down in a right node.
  • the state of the word line WL is turned to L, and thereby Qn 3 and Qn 4 are turned off.
  • the write information is maintained as long as Vcc (or the power) is maintained, because the SRAM cell serves as a capacitor and charges accumulate.
  • the state of the word line WL is again turned to H, and thereby Qn 3 and Qn 4 are turned on.
  • the voltage is applied to BL 1 .
  • a detection of the voltage enables the data to be read out.
  • a sensing amplifier detects this voltage.
  • the sensing amplifier is a circuit that amplifies the voltage from the memory cell.
  • FIG. 6 does not specifically show the sensing amplifier, it is located on the bit line BL.
  • the SRAM memory cell can be regarded as a very small capacitor, and the voltage read out to the bit line is as small as several hundred mV. Thus, the sense amplifier amplifies this voltage up to the processible decibel level.
  • FIG. 7 is a graph of the SNM of the SRAM.
  • a curve in FIG. 7 is called a spectacle characteristic or butterfly curve.
  • the butterfly curve can be obtained from a numerical formula by utilizing the fact that the inflow current amounts to the outflow current in ND 1 (Kirchhoff's law) by taking physical effects of respective transistors Qn 1 , Qn 2 , Qn 3 , Qn 4 , Op 1 , and Op 2 .
  • a stable point 1 represents the state of the left node of “0” and the right node of “1,” whereas a stable point 2 represents the state of the left node of “1” and the right node of “0.”
  • a node's voltage characteristic is at one of the stable points.
  • the state of the stable point is turned from L to H in the word line WL, the voltage V A of the node 1 and the voltage V B of the node 2 are instantly transferring to the state of the stable 2 , and return to the state of the stable point 1 .
  • the sensing amplifier is likely to erroneously detect a change of the stage from the stable point 1 to the stable point 2 due to unexpected charged particle's influence. Therefore, the SRAM having a large SNM is preferable.
  • r in Equation 1 represents a cell ratio expressed by ⁇ d that is (gate width)/(gate length) in a driver transistor, divided by ⁇ a that is (gate width)/(gate length) in an access transistor.
  • the driver transistor corresponds to Qn 1 and Qn 2 in FIG. 6 .
  • the access transistor corresponds to Qn 3 and Qn 4 in FIG. 6 .
  • FIG. 9 shows that a cell ratio of four provides a larger SNM, and thus is preferable in view of the device.
  • V TH is a gate threshold voltage, and when the voltage applied to the gate exceeds a threshold voltage, the source and drain are electrically connected to each other.
  • the different V TH values in the cell influence the yield rate of the device. Control over V TH would improve the yield rate of the device, but V TH varies due to various manufacturing process factors.
  • the yield rate degrades when the gate threshold voltage V TH scatter between the transistors Qn 1 and Qn 2 , between the transistors Op 1 and Op 2 , and/or between the transistors Qn 3 and Qn 4 , when each pair of transistors are designed to have the same characteristic.
  • V TH difference is significantly influenced by not only a non-exposure-apparatus factor, such as a gate film thickness, an ion implantation dose, and a gate electrode material, but also an exposure-apparatus-factor, such as a different gate width and gate length, and the overlay between upper and lower layers.
  • a non-exposure-apparatus factor such as a gate film thickness, an ion implantation dose, and a gate electrode material
  • an exposure-apparatus-factor such as a different gate width and gate length
  • FIG. 10 shows a structure of the cell 100 in the SRAM.
  • the SRAM cell 100 shown in FIG. 10 includes a device separating layer shown by a broken line, a source/drain layer (including p-type active areas 101 a - b , n-type active areas 102 a - b ), a gate layer (including common gate lines 103 a - b ), a contact layer, wiring layers (including supply lines 105 a - b and bit lines 106 a - b ).
  • FIG. 11A shows the gate layer.
  • FIG. 11B shows the device separating layer.
  • FIG. 11C shows the contact layer.
  • FIG. 11D shows the source/drain layer.
  • FIG. 11E shows a wiring layer.
  • the source/drain layer and the gate layers are formed, and the wiring layer and the contact layer are formed according to the device structure.
  • step 1006 determines that the device does not have the predetermined electrical characteristic
  • the exposure parameter set in step 1004 based on the relationship obtained in step 1002 is adjusted (step 1008 ).
  • This embodiment adjusts the exposure parameter (or condition) instead of the reticle pattern as in step 1008 .
  • the exposure parameter or condition
  • each device since each device has its own electrical characteristic to be verified, it is preferable to optimize exposure of the plate such that the electrical characteristic to be verified improves in each device.
  • the reticle pattern is optimized based on the device's electrical characteristic.
  • this SPIE reference merely optimizes the reticle pattern through the OPC and PPC, and does not weigh the exposure apparatus's characteristics or the reticle's manufacturing errors. Thus, the method proposed in this reference is insufficient in improving the yield rate of the device.
  • the reticle pattern is optimized for a specific exposure apparatus difference, it is difficult to apply the reticle pattern to another exposure apparatus different from the specific exposure apparatuses and the flexible application to any exposure application is lost. Therefore, in optimizing the exposure condition, it is necessary that the former seek the yield rate improvement and the latter improve the flexible application.
  • one of the electrical characteristics to be controlled for the device is the gate threshold voltage VTH.
  • VTH the gate threshold voltage
  • different V TH causes failure of the cell.
  • the exposure process controls V TH by taking into account a size effect, such as a gate length, a gate width, a gate area, and a junction area between the source/drain layer, and needs such an exposure condition as reduces differences among them.
  • An illustrative exposure condition that reduces a different size effect is to restrain the LES caused by the defocus by adjusting the NA of the projection optical system, and the effective light source shape in the modified illumination.
  • FIGS. 12A to 12 D show the NA, the focus, and the line end quality.
  • FIG. 12B shows part in the gate layer enclosed by a broken line in FIG. 12A .
  • FIG. 12C shows the LES with a high NA in both the best focus state and the defocus state.
  • FIG. 12D shows the LES with a low NA in both the best focus state and the defocus state.
  • the CD in the best focus state becomes clear with a high NA, and unclear with a low NA.
  • the LES in the defocus state becomes large with a high NA, and small with a low NA.
  • the future fine processing will emphasize the yield rate viewed from the electrical characteristic stronger than the yield rate viewed from the pattern transfer characteristic. In this case, the NA should be made small.
  • Another embodiment optimizes the exposure condition of the gate layer such that the SNM becomes maximum in the SRAM cell structure.
  • the cell ratio r and V TH influence the SNM in Equation 1.
  • a designed value sets a parameter, such as V DD , and the exposure process must weigh values of the cell ratio r and transistor's V TH so as to improve the SNM. Since the SNM improvement in the exposure process weighs the V TH and r values, a reset of the exposure condition is necessary by weighing the size effect of the driver transistor.
  • the cell ratio r is a ratio between the ⁇ value of the driver transistor Qn 2 and the ⁇ value of the access transistor Qn 4 .
  • FIGS. 13B and 13C show part of the gate layer shown in FIG. 13A enclosed by a broken line. More specifically, FIG. 13B shows the LES with a large exposure dose in both the best focus state and the defocus state, whereas FIG. 13C shows the LES with a small exposure dose in both the best focus state and the defocus state.
  • the gate length can be shortened, as shown in FIGS. 13B and 13C , by increasing the exposure dose up to a permissible LES amount as an upper limit, making the driver transistor's V TH small, and improving the cell ratio and SNM.
  • the reason why the cell ratio varies depending upon the exposure dose attributes to an exposure dose sensitivity difference between the access transistor and the driver transistor.
  • Still another embodiment resets the exposure condition for the SRAM cell so as to improve two electrical characteristics, such as SNM and a V TH difference.
  • two electrical characteristics such as SNM and a V TH difference.
  • the device may be still defective when the V TH difference is large. It is therefore necessary to set the exposure dose by weighing a difference amount of the size effect in the driver transistor.
  • step 1008 selects the most influential exposure parameter on the predetermined electrical characteristic (or the exposure parameter that varies the predetermined electrical characteristic most significantly when changed) among the plural exposure parameter. For example, the exposure parameter is slightly varied and the electrical characteristic deterioration is verified through the MCSS of V TH .
  • Step 1002 stores, as the relationship, the influence of the exposure parameter on the electrical characteristic. The electrical characteristic is effectively corrected with the exposure parameters in order of influence.
  • FIG. 14B shows a pair of parts each enclosed by a broken line in FIG. 14A .
  • the aberrational adjustment in the projection optical system reduces the overlay error and difference of V TH when giving the priority to distortion and permitting other aberrations.
  • the NA adjustment of the projection optical system and the effective light source adjustment would indirectly change the distortion parameter.
  • the SRAM cell structure shown in FIG. 10 is less likely to be adopted in the 90 nm node or subsequent designs, because an overlay between the gate line and the active area greatly influences a circuit characteristic. However, it is noted that the above embodiment is applicable to such a fine node.
  • a diffraction optical element (“DOE”) is effective to form a desired effective light source shape.
  • Use of the DOE would contain an error caused by the manufacturing error of the DOE. In that case, another DOE would improve the electrical characteristic. The electrical characteristic improves when an optimal DOE is selected to a combination of the mask data and the exposure apparatus.
  • an exposure system 1 A is used.
  • the exposure system 1 A is different from the exposure system 1 in that the exposure system 1 A has input parts 50 a to 50 C.
  • the input parts 50 a to 50 c enter the effective light source shape data into the processing system 10 A.
  • the DOE forms the effective light source shape.
  • step 1006 selects the most influential electrical characteristic on the device yield rate in the plural electrical characteristics.
  • each electrical characteristic is weighed based on a contribution degree to the final yield rate.
  • the optimal outer ⁇ to SNM improvement and the optimal outer ⁇ to the V TH improvement exist.
  • a relationship between the SRAM device structure in FIG. 6 and the electrical characteristic depends upon the transistor's V TH of Qn 4 , Qn 2 and Op 1 and the cell ratio r for SNM.
  • the relationship between the SRAM device structure in FIG. 6 and the electrical characteristic depends upon the transistor's gate length, gate width, area, etc. for V TH . Therefore, an optimal gate shape and exposure condition exit for each electrical characteristic. Accordingly, when there are plural electrical characteristics, they are weighed based on the influence on the final yield rate in determining the outer ⁇ .
  • step 1008 adjusts the exposure parameter such that SNM improves most.
  • An embodiment that weighs the electrical characteristics based on the contribution degree to the final yield rate can weigh the electrical characteristics based on the fraction defective of the electrical characteristics of the transistors Qn 1 and Qn 2 in the SRAM cell.
  • step 1008 selects one of the plural exposure parameters, which one has the largest value when the set exposure parameter is substituted for a differential function of the function.
  • the electrical characteristic is SNM
  • these three functions are differentiated by the NA, annular ratio, and the spherical aberration, into the three differential functions are obtained, such as d(SNM)/d(NA), d(SNM)/d(outer ⁇ ), and d(SNM)/d(spherical aberration).
  • values of the NA, outer ⁇ , and the spherical aberration set in step 1004 are substituted in these differential functions and the largest differentiated values are obtained. If the differentiated values are arranged in order of NA>outer ⁇ >spherical aberration, the NA is selected as an exposure parameter for optimization.
  • the outer ⁇ is optimized while the optimal value of the NA is maintained. Even when the outer ⁇ is optimized, fed back step 1006 determines that SNM is still outside the predetermined range, the spherical aberration is optimized while the optimal value of the NA and outer ⁇ are maintained.
  • the exposure parameters can be effectively optimized by adjusting the parameters in order of higher influence on SNM.
  • Step 1008 may include the step of adjusting an exposure parameter that depends upon an optical system (e.g., an illumination optical system and a projection optical system by using an optical simulation, and the step of adjusting an exposure parameter that does not depend upon the optical system without an optical simulation.
  • the optical simulation is one necessary type of simulation in simulating the device's electrical characteristic from the plate to be exposed.
  • the optical simulation has a heavy calculational load. Therefore, the simulation that varies the NA, effective light source shape, and the aberrational parameter to verify the electrical characteristic needs a long calculation time period.
  • a parameter/exposure condition such as scanning directions and rotations of wafer and reticle stages, is a parameter relating to slicing level setting, a focus position, and overlay, and involves after the optical image is determined.
  • the exposure apparatus parameter that does not depend upon the optical system includes an exposure apparatus parameter that can approximately calculate an optical image using an overlay of the optical image.
  • the parameters include a light source's spectrum distribution, a chromatic aberration, and a stage vibration (MSDz).
  • MSDz stage vibration
  • An optical image can be formed by superposing defocus images of a reference wavelength, when the light source has a spectrum distribution. Since the optical image superposition has a small calculational load, the parameter adjustment in case of the spectrum distribution etc., may be adjusted after the optical simulation that determines the parameter that depends upon the optical system, such as an illumination shape and the aberration.
  • the exposure parameter depending upon the optical system such as an NA, an illumination shape, and an aberration
  • the exposure parameter that does not depend upon the optical system such as an exposure dose and a focus position, is optimized for effective parameter setting.
  • step 1006 determines that the device has the predetermined electrical characteristic
  • the plate is exposed with the set exposure parameter (step 1010 ).
  • an exposure apparatus parameter based on a factor implicated with the electrical characteristic, such as LES, SWA, and LER.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
US11/460,663 2005-07-29 2006-07-28 Exposure method Abandoned US20070035716A1 (en)

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