US20060267098A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US20060267098A1
US20060267098A1 US11/277,933 US27793306A US2006267098A1 US 20060267098 A1 US20060267098 A1 US 20060267098A1 US 27793306 A US27793306 A US 27793306A US 2006267098 A1 US2006267098 A1 US 2006267098A1
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Prior art keywords
opening
insulation film
semiconductor device
conductive film
film
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US11/277,933
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English (en)
Inventor
Hirokazu Fujimaki
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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Assigned to OKI ELECTRIC INDUSTRY CO., LTD. reassignment OKI ELECTRIC INDUSTRY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUJIMAKI, HIROKAZU
Publication of US20060267098A1 publication Critical patent/US20060267098A1/en
Priority to US11/905,679 priority Critical patent/US7663241B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/957—Making metal-insulator-metal device

Definitions

  • the present invention relates to a semiconductor device which in particular is provided with a capacitive element having a MIM (Metal-Insulator-Metal) structure. Moreover, the present invention also relates to a method of manufacturing such semiconductor device.
  • MIM Metal-Insulator-Metal
  • a common LSI (Large Scale integration) semiconductor is composed of various basic elements integrated to high density.
  • the basic elements incorporated in a LSI semiconductor can be classified into two prominent categories, which are active elements and inactive elements.
  • One typical active element would be a transistor.
  • transistors such as a bipolar junction transistor (BJT), a junction field effect transistor (JFET), a metal oxide semiconductor field effect transistor (MOSFET), and so forth.
  • silicon which is commonly used as a material for forming a transistor, it is also possible to use a compound semiconductor such as gallium arsenide (GaAs), indium phosphide (InP) or the like.
  • a typical inactive element would be a resistive element or a capacitive element.
  • such inactive element is formed using various conductive films and insulation films formed in the processes of forming a transistor.
  • a capacitive element is usually formed having two layers of polysilicon electrodes and an interlayer of a silicon nitride film between the two layers of polysilicon electrodes.
  • a delay of an electric signal is generated due to the coupling of a resistance (R) and a capacitance (C).
  • the amount of delay in a signal is determined based on a time constant that can be obtained by C ⁇ R.
  • the capacitance (C) of a capacitive element With respect to the capacitance (C) of a capacitive element, the capacitive element itself is an unchangable function. Accordingly, in order to prevent unnecessary signal delay, it is necessary to reduce the resistance (R) of the capacitive element.
  • a conventional capacitive element uses polysilicon, for instance, as its electrode, the parasitic resistance tends to become large, and thereby, an unnecessary time constant has to be added.
  • a capacitive element having an MIM structure using a metal wiring as an electrode such as the one disclosed in Washio, et al., “A 0.2- ⁇ m 180-GHz-fmax 6.7-ps-ECL SOI/HRS Self-Aligned SEG SiGe HBT/CMOS Technology for Microwave and High-Speed Digital Applications”, IEEE International Electron Devices Meeting (IEDM), pp. 741-742, 2000 (hereinafter referred to as Non-Patent Reference 1), has come to be widely used.
  • Prior Art Technology 1 conventional technology relating to such capacitive element will be referred to as Prior Art Technology 1.
  • a semiconductor wafer (hereinafter to be referred to simply as a wafer) having an insulation film formed on a surface thereof is prepared, and a metal film is formed on the entire upper surface of this wafer. Then the metal film is processed using known photolithographic and etching processes. By these processes, a first metal pattern including a lower electrode of the capacitive element and other metal patterns is formed.
  • an insulator is deposited over the entire surface of the wafer to form an insulation film, after which a surface of the insulation film is planarized by CMP (Chemical and Mechanical Polishing) to form an interlayer insulation film in which the thickness from the surface of the first metal pattern is about 6000 ⁇ (angstrom), for instance.
  • CMP Chemical and Mechanical Polishing
  • an opening having a diameter slightly smaller than that of the lower electrode is formed.
  • an HDP (High-Density Plasma) film which is an insulation film, is formed on the entire surface of the wafer, i.e., on the interlayer insulation film and inside the opening, with a thickness of about 2000 ⁇ .
  • a contact hole with an opening diameter about 0.5 ⁇ m is formed over a region where the capacitive element is not formed, and tungsten (W) is deposited over the entire surface of the wafer to the thickness of about 8000 ⁇ , in order to form contact plugs.
  • W tungsten
  • the inside of the contact hole will be filled with tungsten (W) while the inside of the opening covered with the HDP film will also be filled up with tungsten.
  • the tungsten film over the interlayer insulation film is removed while leaving the tungsten inside the contact hole.
  • the tungsten remaining inside the contact hole functions as the contact plug for electrically connecting the upper and lower layers sandwiching the interlayer insulation film in between.
  • a metal film is formed over the entire surface of the wafer, after which the metal film is processed using known photolithographic and etching processes to form a second metal pattern having an upper electrode of the capacitive element and other metal patterns.
  • a capacitive element having an MIM structure can be formed.
  • the diameter of the opening formed for the capacitive element is considerably larger than the diameter of the contact hole. Therefore, in the process of removing the tungsten film over the interlayer insulation film, a portion of the tungsten will remain on the inner surface of the opening in the form of sidewalls. Such residual tungsten film may be a factor leading to problems such as the peeling off of a film formed on the tungsten film, and the like. As a result, this may cause other problems, such as defects in manufacturing processes and a decrease in a yield ratio.
  • Patent Reference 1 Japanese Laid-Open Patent Application No. 2003-31691
  • Patent Reference 2 the opening normally used in the capacitive element is replaced with multiple contact holes in order to prevent unnecessary tungsten film from remaining in the form of sidewalls.
  • this technology will be referred to as Prior Art Technology 2.
  • Patent Reference 2 Japanese Laid-Open Patent Application No. 2003-133414
  • Patent Reference 2 the opening normally used in the capacitive element is replaced with a liner opening trench having the same width as the diameter of the contact hole in order to prevent unnecessary tungsten film from remaining in the form of sidewalls.
  • this technology will be referred to as Prior Art Technology 3.
  • a semiconductor device comprises a substrate, a first conductive film, a first insulation film, a second insulation film, a second conductive film, and a third conductive film.
  • the first conductive film is formed on the substrate.
  • the first insulation film is formed on the first conductive film and has a first opening.
  • the first opening is formed to have multiple crossing trenches each having a predetermined width.
  • the second insulation film is formed on the side and the bottom of the first opening.
  • the second conductive film is formed on the second insulation film inside the first opening.
  • the third conductive film formed on the second insulation film and the second conductive film.
  • a semiconductor device comprises a substrate, a first conductive film, a first insulation film, a second insulation film, a second conductive film, and a third conductive film.
  • the first conductive film is formed on the substrate and has a first opening.
  • the first opening has a predetermined width.
  • the first insulation film is formed on the first conductive film and has a second opening over the first opening.
  • the second opening has a predetermined width.
  • the second insulation film is formed on the sides of the first and second openings.
  • the second conductive film is formed on the second insulation film inside the first and second openings.
  • the third conductive film formed on the second insulation film and the second conductive film.
  • a method of manufacturing a semiconductor device comprises the steps of: preparing a substrate; forming a first conductive film on the substrate; forming a first insulation film on the substrate and the first conductive film; forming a first opening having a predetermined width in the first insulation film formed on the first conductive film; forming a second insulation film on the side surface and the bottom of the first opening; forming a second conductive film on the second insulation film inside the first opening; and forming a third conductive film over the first insulation film and on the second insulation film and the second conductive film.
  • a method of manufacturing a semiconductor comprises the steps of: preparing a substrate; forming a first conductive film on the substrate; forming a first insulation film on the substrate and the first conductive film; forming a first opening having a predetermined width in the first insulation film formed on the first conductive film; forming a second opening, of which bottom does not contact with the substrate, in the first conductive film exposed by the first opening; forming a second conductive film on a side of the first opening and on a side and a bottom of the second opening; forming a second conductive film on the second insulation film inside the first and second openings; and forming a third conductive film over the first insulation film and on the second insulation film and the second conductive film.
  • FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention
  • FIG. 2 is a sectional view showing the structure of a horizontal plane section of a capacitive element according to the first embodiment of the present invention taken along line I-I′ shown in FIG. 1 ;
  • FIG. 3A is a sectional view of a comparative example of a semiconductor device according to the first embodiment of the present invention.
  • FIG. 3B is a sectional view showing the structure of a horizontal plane section of a capacitive element taken along a line III-III′ in FIG. 3A ;
  • FIG. 4A is a sectional view of another comparative example of a semiconductor device according to the first embodiment of the present invention.
  • FIG. 3B is a sectional view showing the structure of a horizontal plane section of a capacitive element taken along line V-V′ in FIG. 4A ;
  • FIG. 5A to FIG. 7B are diagrams showing processes of manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 8A is a sectional view of a semiconductor device according to a second embodiment of the present invention.
  • FIG. 8B is an enlarged sectional view of a region A in FIG. 8A ;
  • FIG. 9A to FIG. 10B are diagrams showing processes of manufacturing the semiconductor device according to the second embodiment of the present invention.
  • FIG. 11A is a sectional view of a semiconductor device according to a third embodiment of the present invention.
  • FIG. 11B is a sectional view showing the structure of a horizontal plane section of a capacitive element according to the third embodiment of the present invention taken along line VII-VII′ shown in FIG. 11A ;
  • FIG. 12A is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 12B is a sectional view showing the structure of a horizontal plane section of a capacitive element according to the fourth embodiment of the present invention taken along line IX-IX′ shown in FIG. 12A .
  • This embodiment will show a semiconductor device having a capacitive element and a second element formed on a single support substrate, as an example of the present invention.
  • FIG. 1 is a sectional view of a semiconductor device 1 according to the first embodiment of the present invention.
  • FIG. 1 shows a sectional structure of the semiconductor device 1 cut off at a plane which is perpendicular to a support substrate 11 , and includes a capacitive element 10 and a first element 80 .
  • the semiconductor device 1 has a structure in which the capacitive element 10 and a first element 80 are formed on the support substrate 11 .
  • the first element 80 might be a transistor, a resistive element or the like.
  • the first element 80 is has one or more contact plugs 84 which fill the interior of one or more contact holes.
  • the capacitive element 10 has a lower electrode (i.e. first conductive film) 13 formed on the support substrate 11 , an interlayer insulation film (i.e. first insulation film) 12 formed on the lower electrode 13 and on the support substrate 11 , an insulation film (i.e. second insulation film) 15 formed on the interlayer insulation film 12 and on the sides and bottom of an opening 12 a formed in the interlayer insulation film 12 over the lower electrode 13 , an electrode (i.e. second conductive film) (hereinafter to be referred to as an intra-opening electrode) 14 formed inside an opening 13 a over the lower electrode 13 after the insulation film 15 is formed, and an upper electrode (i.e.
  • the third conductive film) 16 formed in a region opposite to the lower electrode 13 with the interlayer insulation film 12 formed therebetween, and the insulation film 15 and the intra-opening electrode 14 formed between the upper electrode 16 and the lower electrode 13 .
  • the intra-opening electrode 14 is electrically connected to the upper electrode 16 .
  • the intra-opening electrode 14 functions as a portion of the upper electrode 16 of the capacitive element 10 .
  • there is an insulation film between the support substrate 11 and the lower electrode 13 and this insulation film serves to prevent the lower electrode 13 from electrically connecting with the support substrate 11 . This condition remains the same in the other embodiments of the present invention which will be described later on.
  • the support substrate 11 is a semiconductor substrate such as a p-type silicon substrate, for instance.
  • a semiconductor substrate such as a p-type silicon substrate, for instance.
  • this is not a limiting factor in this embodiment, and various types of substrates are also applicable.
  • the lower electrode 13 formed on the support substrate 11 is composed of, from the bottom layer, a titanium nitride (TiN) layer with a thickness of about 1000 ⁇ , a titanium (Ti) layer with a thickness of about 500 ⁇ , an aluminum silicon (AlSi) layer with a thickness of about 5000 ⁇ , a titanium (TiN) layer with a thickness of about 500 ⁇ and a titanium nitride (TiN) layer with a thickness of about 1000 ⁇ .
  • the lower electrode 13 is a multilayer conductive film (TiN/Ti/AlSi/Ti/TiN) having a total thickness of about 8000 ⁇ .
  • the lower electrode 13 may be a single layer conductive film or a single layer or multilayer conductive film using other materials.
  • the shape of an upper surface of the lower electrode 13 may be a right quadrangle which is 10 to 100 ⁇ m on one side, for instance.
  • the interlayer insulation film 12 formed on the support substrate 11 and the lower electrode 13 is a so-called CVD film which is formed by depositing silicon oxide (Si x O y ), for instance, using a CVD method.
  • silicon oxide Si x O y
  • various kinds of insulators such as silicon oxide, silicon nitride, and the like are applicable.
  • a portion thereof included in a region where the capacitive element 10 is supposed to be formed, i.e. a portion thereof sandwiched between the lower electrode 13 and the upper electrode 16 functions as a capacitive insulation film of the capacitive element 10 .
  • a surface of the interlayer insulation film 12 is planarized by a CMP method, for instance, and the interlayer insulation film 12 after being planarized has a thickness of about 6000 ⁇ from the surface of the lower electrode 13 , for instance.
  • This interlayer insulation film 12 has an opening 12 a in a region over the lower electrode 13 .
  • This opening 12 a is formed by arranging multiple linear trenches in a lattice pattern, one trench having a width of about 0.9 ⁇ m and a length equal to or shorter than the length of one side of the lower electrode 13 , for instance. More details on the shape of the opening 12 a will be described later on with reference to FIG. 2 .
  • the opening 12 a exposes a portion of the upper surface of the lower electrode 13 formed underneath the interlayer insulation film 12 , i.e., the opening 12 a penetrates the interlayer insulation film 12 .
  • the insulation film 15 is formed on the interlayer insulation film 12 .
  • the insulation film 15 extends from an upper portion of the interlayer insulation film 12 to the inside of the opening 12 a , and covers a portion of the lower electrode 13 exposed by the opening 12 a at the bottom of the opening 12 a . That is, the insulation film 15 in the region where the capacitive element 10 is supposed to be formed functions as a capacitive insulation film of the capacitive element 10 .
  • This insulation film 15 is a so-called HDP film, which is formed by depositing silicon oxide (Si x O y ), for instance, using the plasma CVD method. By forming the insulation film 15 , the opening over the lower electrode 13 changes from the opening 12 a to the opening 13 a .
  • the thickness of the insulation film 15 is considered to be 0.2 ⁇ m, for instance. Accordingly, the width of each linear trench constructing the opening 13 a can be determined by subtracting double the thickness of the insulation film 15 from the width of the opening 12 a . That is, the thickness of the opening 13 a becomes about 0.5 ⁇ m. This is approximately the same as the diameter of contact holes 82 a in the first element 80 which will be described later on.
  • a predetermined conductor is filled into the opening 13 a to form the intra-opening electrode 14 .
  • Tungsten (W), copper (Cu), or the like may be used for the predetermined conductor for forming the intra-opening electrode 14 .
  • this is not a limiting factor in this embodiment, and various kinds of conductors are also applicable.
  • the following describes a situation in which tungsten (W) is used as the conductor for forming the intra-opening electrode 14 .
  • the upper electrode 16 is formed while the interlayer insulation film 12 , the insulation film 15 , and the intra-opening electrode 14 are sandwiched between the lower electrode 13 and the upper electrode 16 .
  • the structure and material of the upper electrode 16 may be the same as the lower electrode 13 .
  • the upper electrode 16 is electrically connected with the intra-opening electrode 14 by contacting with the intra-opening electrode 14 as mentioned above. That is, the upper electrode 16 in the capacitive element 10 is made to electrically extend to the side of the lower electrode 13 by the intra-opening electrode 14 .
  • the capacitive element 10 can have increased capacitance, and as a result, the desired capacitance can be obtained with a small sized device.
  • the first element 80 has a lower layer conductive film 83 formed on the support substrate 11 , the interlayer insulation film 12 formed on the lower layer conductive film 83 and the support substrate 11 , the insulation film 15 formed on the interlayer insulation film 12 , contact plugs 84 formed inside contact holes 82 a that are formed in the interlayer insulation film 12 over the lower layer conductive film 83 , and an upper layer conductive film 86 formed on the insulation film 15 and the contact plugs 84 .
  • the support substrate 11 , the interlayer insulation film 12 and the insulation film 15 are common to the first element 80 and the capacitive element 10 .
  • the insulation film 15 is not supposed to be formed inside the contact holes 82 a that are formed in the interlayer insulation film 12 .
  • the lower layer conductive film 83 formed on the support substrate 11 has the same layer structure as the lower electrode 13 or the upper electrode 16 in the capacitive element 10 .
  • the above-mentioned contact holes 82 a are formed in the interlayer insulation film 12 on this lower layer conductive film 83 .
  • the contact holes 82 a have a cylindrical shape of about 0.5 ⁇ m in diameter, for instance.
  • a predetermined conductor is filled into each contact hole 82 a to form the contact plug 84 .
  • the predetermined conductor for forming the contact plugs 84 it is possible to apply the same material as used in forming the intra-opening electrode 14 in the capacitive element 10 .
  • the upper layer conductive film 86 is formed, and the contact hole 84 and the inter layer insulation film 12 are sandwiched between the lower layer conductive film 83 and the upper layer conductive film 86 .
  • the upper layer conductive film 86 has the same layer structure as the lower electrode 13 or the upper electrode 16 in the capacitive element 10 .
  • the upper layer conductive film 86 is electrically connected with the lower layer conductive film 83 via the contact plugs 84 . That is, the lower layer conductive film 83 in the first element 80 is electrically drawn out up to the upper layer conductive film 86 on the interlayer insulation film 12 by the contact plugs 84 .
  • FIG. 2 is a sectional view showing a structure of a horizontal plane section of the capacitive element 10 taken along line I-I′ shown in FIG. 1 . That is, FIG. 2 is a sectional view showing a horizontal plane section between the lower electrode 13 and the upper electrode 16 in the capacitive element 10 .
  • FIG. 1 shows the sectional structure of the semiconductor device 1 which includes a plane II-II′ shown in FIG. 2 .
  • the opening 12 a has a lattice structure made up of multiple linear trenches arranged in predetermined intervals, three of which being vertical and three of which being horizontal.
  • each linear trench is about 0.9 ⁇ m in width and about 8 ⁇ m in length. Since the opening 12 a penetrates the interlayer insulation film 12 , the depth of each of the opening trenches is the same as the thickness of the interlayer insulation film 12 . Furthermore, in this embodiment, since the shape of the upper surface of the lower electrode 13 is supposed to be a right quadrangle which is about 10 ⁇ m on one side, the opening 12 a will have a 1 ⁇ m margin from each edge of the lower electrode 13 .
  • the inner sides and the bottom of the opening 12 a have the insulation film 15 formed to a thickness of about 0.2 ⁇ m. Therefore, by forming the insulation film 15 , the width of the opening (corresponding to the opening 13 a ) over the lower electrode 13 will narrow to about 0.5 ⁇ m. Accordingly, the intra-opening electrode 14 formed by filling tungsten (W) inside the opening 13 a will be about 0.5 ⁇ m in width. In other words, in this embodiment, the width of the intra-opening electrode 14 formed for the capacitive element 10 is about the same as the diameter of each contact holes 84 in the first element 80 . Thus, no large depression will be formed in the upper portion of the intra-opening electrode 14 in the manufacturing processes.
  • FIG. 3A and FIG. 3B a semiconductor device 2 , in which openings over the lower electrode 13 after an insulation film 25 is formed to have the same shape as the contact holes 82 a in terms of a horizontal plane section, is shown as a comparative example 1 with respect to the semiconductor device 1 according to the first embodiment of the present invention. Furthermore, in FIG. 4A and FIG. 4B , a semiconductor device 3 , in which openings over the lower electrode 13 after an insulation film 35 is formed are formed as liner trenches, is shown as a comparative example 2 with respect to the semiconductor device 1 according to the first embodiment of the present invention.
  • FIG. 3 a semiconductor device 2 , in which openings over the lower electrode 13 after an insulation film 25 is formed to have the same shape as the contact holes 82 a in terms of a horizontal plane section, is shown as a comparative example 1 with respect to the semiconductor device 1 according to the first embodiment of the present invention.
  • FIG. 4A and FIG. 4B a semiconductor device 3 , in which openings over the lower electrode
  • FIG. 3A is a sectional view showing a sectional structure of the semiconductor device 2 cut off at a plane perpendicular to the support substrate 11 , while including a capacitive element 20 of the comparative example 1 and the first element 80
  • FIG. 3B is a sectional view showing the structure of a horizontal plane section of the capacitive element 20 taken along a line III-III′ shown in FIG. 3A
  • FIG. 4A is a sectional view showing a sectional structure of the semiconductor device 3 cut off at a plane perpendicular to the support substrate 11 , while including a capacitive element 30 of the comparative example 2 and the first element 80
  • FIG. 3B is a sectional view showing the structure of a horizontal plane section of the capacitive element 30 taken along a line IV-IV′ shown in FIG. 4A .
  • intra-opening electrodes 24 to be formed inside the openings 23 a after the insulation film 25 is being formed will have a cylindrical shape about 0.5 ⁇ m in diameter, respectively.
  • the total area of the horizontal plane section of the intra-opening electrodes 24 q.v. FIG.
  • the area of the intra-opening electrode 14 of the first embodiment of the present invention is larger.
  • a larger area of the intra-opening electrode 14 electrically extends toward the lower electrode 13 from the upper electrode 16 .
  • intra-opening electrodes 34 to be formed inside the openings 33 a after the insulation film 15 is formed will have a linear shape about 0.5 ⁇ m in width, respectively.
  • the total area of the horizontal plane section of the intra-opening electrodes 34 q.v. FIG. 4B
  • the area of the horizontal plane section of the intra-opening electrode 14 q.v. FIG.
  • the area of the intra-opening electrode 14 of the first embodiment of the present invention is larger.
  • the larger area of the intra-opening electrode 14 electrically extends toward the lower electrode 13 from the upper electrode 16 .
  • the first embodiment of the present invention adopts a structure in which the opening has multiple linear trenches crossing one another, each linear trench having a width that is about the same as a diameter of the contact hole 82 a in the first element 80 .
  • this structure it is possible to prevent tungsten film from remaining inside the opening in a form of sidewalls, wherein such residual tungsten film may be a factor leading to problems such as the peeling off of a film formed on the tungsten film, and at the same time, it is possible to obtain a higher capacitive density.
  • possible defects in the manufacturing processes and a decrease in the yield ratio can be prevented, and at the same time, it is possible to prevent the semiconductor device 1 from becoming larger in size.
  • a support substrate 11 is prepared.
  • a conductive film (which is also referred to as a multilayer conductive film) 13 A having a multilayer structure is formed on the support substrate 11 by sequentially depositing a titanium nitride (TiN) layer 13 b with a thickness of about 1000 ⁇ , a titanium (Ti) layer 13 c with a thickness of about 500 ⁇ , an aluminum silicon (AlSi) layer 13 d with a thickness of about 5000 ⁇ , a titanium layer 13 e with a thickness of about 500 ⁇ and a titanium nitride layer 13 f with a thickness of about 1000 ⁇ .
  • TiN titanium nitride
  • Ti titanium
  • AlSi aluminum silicon
  • a resist pattern R 1 having the same upper shape as a lower electrode 13 (which will be formed in a post process) and a lower layer conductive film 83 (which will be formed in a post process) is formed on the multilayer conductive film 13 A, as shown in FIG. 5A .
  • the multilayer conductive film 13 A is processed into the lower electrode 13 and the lower layer conductive film 83 , as shown in FIG. 5B .
  • the resist pattern R 1 is removed.
  • silicon oxide is deposited on the support substrate 11 and the lower electrode 13 using the CVD method, for instance, after which the upper surface of the deposited silicon oxide film is planarized using the CMP method.
  • an interlayer insulation film 12 having a thickness of about 6000 ⁇ from the upper surface of the lower electrode 13 , is formed on the lower electrode 13 , the lower layer conductive film 83 and the support substrate 11 , as shown in FIG. 5C .
  • a resist pattern R 2 having an opening which has the same opening shape as an opening 12 a (which will be formed in a post process) is formed on the interlayer insulation film 12 .
  • the opening 12 a which is constructed as having multiple linear trenches arranged in a lattice pattern, is formed over the lower electrode 13 , with the width of each linear trench being about 0.9 ⁇ m, as shown in FIG. 6A .
  • the resist pattern R 2 is removed.
  • an insulation film 15 A which is an HDP film having a thickness of about 0.2 ⁇ m, is formed on the interlayer insulation film 12 and on the sides and bottom of the opening 12 a , as shown in FIG. 6B .
  • the opening 12 a will become an opening 13 a which is constructed to have multiple linear trenches arranged in a lattice pattern, with the width of each linear trench being narrower than the opening 12 a by double the thickness of the insulation film 15 A (i.e. the insulation film 15 ).
  • a resist pattern R 3 having openings formed over a region where the first element 80 will be formed is formed on the insulation film 15 A, the openings having the same upper shape as contact holes 82 a (which will be formed in the post process).
  • contact holes 82 a each having a diameter of about 0.5 ⁇ m are formed over the lower layer conductive film 83 , as shown in FIG. 6C .
  • the insulation film 15 A is processed into an insulation film 15 .
  • the resist pattern R 3 is removed.
  • tungsten (W) is deposited over the entire surface of the support substrate 11 using the CVD method or a sputtering method, for instance, a tungsten film 14 A is formed on the insulation film 15 and inside the opening 13 a and the contact holes 83 a , as shown in FIG. 7A .
  • the tungsten film 14 A over the interlayer insulation film 12 is removed while leaving parts of the tungsten film 14 A inside the opening 13 a and the contact holes 83 a .
  • an intra-opening electrode 14 is formed inside the opening 13 a
  • contact plugs 84 are formed inside the contact holes 83 a , as shown in FIG. 7B .
  • a multilayer conductive film having the same structure as the multilayer conductive film 13 A is formed on the intra-opening electrode 14 , the contact plugs 84 , and the insulation film 15 . Then, by conducting known photolithographic processes on the multilayer conductive film, a resist pattern having the same upper shape as an upper electrode 16 (which will be formed in a post process) and an upper layer conductive film 86 (which will be formed in a post process) is formed. Then, by etching the multilayer conductive film while using the resist pattern as a mask, the upper electrode 16 and the upper layer conductive film 86 are formed.
  • the semiconductor device 1 shown in FIG. 1 can be acquired.
  • the semiconductor device 1 has the support substrate ( 11 ) which is a semiconductor substrate, the lower electrode ( 13 ) formed on the support substrate ( 11 ), the insulation film ( 12 ) formed on the lower electrode ( 13 ) and which includes the opening ( 12 a ) formed over the lower electrode ( 13 ) having multiple trenches crossing one another, each multiple trench having a predetermined width, the insulation film ( 15 ) formed on the sides and the bottom of the opening ( 12 a ), the intra-opening electrode ( 14 ) formed on the insulation film ( 15 ) inside the opening ( 12 a ), and the upper electrode ( 16 ) formed on the insulation film ( 15 ) and the intra-opening electrode ( 14 ).
  • the opening 12 a by forming the opening 12 a to have a structure in which multiple trenches each having a predetermined width cross one another, it is possible to enlarge the area of the opening 12 a in terms of a horizontal plane section without enlarging the width of each trench. Therefore, it is possible to obtain higher capacitive density for the capacitive element 10 , and as a result, it is possible to obtain the desired capacitance with a small sized device. This means that it is possible to prevent the semiconductor device 1 from becoming larger in size.
  • the insulation film 15 functioning as a capacitive insulation film is formed after the opening 12 a is formed in the interlayer insulation film 12 , the etching process for forming the opening 12 a will be made easier.
  • an insulation film that is a capacitive insulation film is supposed to be formed before forming the opening 12 a
  • the insulation film 15 is supposed to be formed after the opening 12 a is formed, and therefore, it is not necessary to have any such particular control for stopping the etching.
  • FIG. 8A is a sectional view of a semiconductor device 4 according to the second embodiment of the present invention.
  • FIG. 8A shows a sectional structure of the semiconductor device 4 cut off at a plane perpendicular to a support substrate 11 , and includes a capacitive element 40 and the first element 80 .
  • FIG. 8B is an enlarged sectional view of a region A in FIG. 8A .
  • the semiconductor device 4 has the same structure as the semiconductor device 1 of the first embodiment, except that the capacitive element 10 constructed with the lower electrode 13 , the opening 12 a , the opening 13 a , the intra-opening electrode 14 , and the insulation film 15 is replaced with a capacitive element 40 constructed with a lower electrode 43 , an opening 42 a , an opening 43 a , an intra-opening electrode 44 , and an insulation film 45 .
  • the opening 42 a extends to the interior of the lower electrode 43 but the bottom thereof does not contact with the support substrate 11 . Since the rest of the structure is the same as the structure of the semiconductor device 1 of the first embodiment, a detailed description thereof will be omitted.
  • the lower electrode 43 is composed of, from the bottom layer, a titanium nitride (TiN) layer 13 b with a thickness of about 1000 ⁇ , a titanium (Ti) layer 13 c with a thickness of about 500 ⁇ , an aluminum silicon (AlSi) layer 13 d with a thickness of about 5000 ⁇ , a titanium (TiN) layer 13 e with a thickness of about 500 ⁇ and a titanium nitride (TiN) layer 13 f with a thickness of about 10000 ⁇ .
  • TiN titanium nitride
  • TiN titanium nitride
  • the lower electrode 43 is a multilayer conductive film (TiN/Ti/AlSi/Ti/TiN) having a total thickness of about 8000 ⁇ (shown in FIG. 8B ), as with the lower electrode 13 in the first embodiment.
  • the opening 42 a extends to the interior of the lower electrode 43 .
  • the opening 42 a extends to the interior of the titanium layer 13 c located at a lower portion of the lower electrode 43 .
  • the insulation film 45 of this embodiment has the same film as the insulation film 15 of the first embodiment. However, in this embodiment, since the opening 42 a extends to the interior of the lower electrode 43 , the insulation film 45 is formed to extend from the interior of the insulation film 12 to the interior of the lower electrode 43 , and seals the opening 42 a at the bottom of the opening 42 a .
  • the opening 43 a over the lower electrode 43 after the insulation film 45 is formed extends from the interior of the interlayer insulation film 12 to the interior of the lower electrode 43 .
  • the depth of the opening 43 a should preferably be set to be larger than the thickness of the interlayer insulation film 12 .
  • the intra-opening electrode 44 is a conductive film formed by filling the interior of the opening 43 a with a predetermined conductor such as tungsten (W).
  • a predetermined conductor such as tungsten (W).
  • the intra-opening electrode 44 formed inside the opening 43 a also extends to the interior of the lower electrode 43 .
  • the shape of the horizontal plane section of the opening 42 a has a lattice structure made up of multiple linear trenches arranged in predetermined intervals, some of which being vertical and the other of which being horizontal.
  • each linear trench is about 0.9 ⁇ m in width and about 8 ⁇ m in length.
  • the support substrate 11 is prepared as with the first embodiment.
  • the multilayer conductive film 13 A is formed on the support substrate 11 by sequentially depositing a titanium nitride (TiN) layer 13 b with a thickness of about 1000 ⁇ , a titanium (Ti) layer 13 c with a thickness of about 500 ⁇ , an aluminum silicon (AlSi) layer 13 d with a thickness of about 5000 ⁇ , a titanium layer 13 e with a thickness of about 500 ⁇ and a titanium nitride layer 13 f with a thickness of about 1000 ⁇ .
  • TiN titanium nitride
  • Ti titanium
  • AlSi aluminum silicon
  • a resist pattern R 1 having the same upper shape as a lower electrode 43 (which will be formed in a post process) and an under layer conductive film 83 (which will be formed in a post process) is formed on the multilayer conductive film 13 A (q.v. FIG. 5A ).
  • the multilayer conductive film 13 A is processed into the lower electrode 13 and the under layer conductive film 83 (q.v. FIG. 5B ). After forming the lower electrode 13 and the under layer conductive film 83 , the resist pattern R 1 is removed.
  • silicon oxide is deposited on the support substrate 11 and the lower electrode 13 using the CVD method, for instance, after which the upper surface of the deposited silicon oxide film is planarized using a CMP method.
  • the interlayer insulation film 12 having a thickness of about 6000 ⁇ from the upper surface of the lower electrode 13 to the upper surface of the interlayer insulation film 12 , is formed on the lower electrode 13 , the under layer conductive film 83 , and the support substrate 11 (q.v. FIG. 5C ).
  • a resist pattern R 2 having an opening which has the same opening shape as an opening 42 a (which has the same shape as the opening 12 a and formed in a post process) is formed on the interlayer insulation film 12 .
  • the opening 12 a which is constructed as having multiple linear trenches arranged in a lattice pattern, is formed over the lower electrode 13 , a width of each linear trench being about 0.9 ⁇ m (q.v. FIG. 6A ).
  • etching the interlayer insulation film 12 As for the conditions of etching the interlayer insulation film 12 , it is possible to use a mixed gas of C 4 F 8 , CO, and O 2 as an etching gas. In this case, RF power may be set to 500 W (watt) and the pressure inside the chamber may be set to 40 mTorr. By etching the interlayer insulation film 12 under such conditions, portions of the lower electrode 13 are exposed. In addition, in this process, the resist pattern R 2 is not removed.
  • the titanium nitride film (TiN) 13 f , the titanium layer 13 e , the aluminum silicon (AlSi) layer 13 d , and the titanium (Ti) layer 13 c of the lower electrode 13 are etched sequentially while using the remaining resist pattern R 2 as a mask, as shown in FIG. 9A .
  • the etching of the lower electrode 13 is conducted so that a portion of the titanium layer 13 c remains, and the entirety of the lowest titanium nitride layer 13 b remains.
  • ECR Electrode
  • a mixed gas of BCl 3 and Cl 2 may be used as an etching gas, Mg power may be set to 700 W, PF power may be set to 70 W, and the pressure inside the chamber may be set to 1 Pa.
  • Mg power may be set to 700 W
  • PF power may be set to 70 W
  • the pressure inside the chamber may be set to 1 Pa.
  • an insulation film 45 A which is an HDP film having a thickness of about 0.2 ⁇ m, is formed on the interlayer insulation film 12 and on the sides and bottom of the opening 42 a , as shown in FIG. 9B .
  • the opening 42 a becomes an opening 43 a which is constructed to have multiple linear trenches arranged in a lattice pattern, with the width of each linear trench being narrower than the opening 42 a by double the thickness of the insulation film 45 A (i.e. the insulation film 45 ).
  • a resist pattern R 3 having openings formed over a region where the first element 80 will be formed is formed on the insulation film 45 A, the openings having the same upper shape as contact holes 82 a (which will be formed in the post process).
  • contact holes 82 a each having a diameter of about 0.5 ⁇ m are formed over the under layer conductive film 83 , as shown in FIG. 9C .
  • the insulation film 45 A is processed into an insulation film 45 .
  • the resist pattern R 3 is removed.
  • tungsten (W) is deposited over the entire surface of the support substrate 11 using the CVD method or a sputtering method, for instance, a tungsten film 44 A is formed on the insulation film 45 and the inside of the opening 43 a and the contact holes 83 a , as shown in FIG. 10A .
  • the tungsten film 44 A over the interlayer insulation film 12 is removed while leaving portions of the tungsten film 44 A inside the opening 43 a and the contact holes 83 a .
  • the intra-opening electrode 44 is formed inside the opening 43 a
  • the contact plugs 84 are formed inside the contact holes 83 a , as shown in FIG. 10B .
  • a multilayer conductive film having the same structure as the multilayer conductive film 13 A is formed on the intra-opening electrode 44 , the contact plugs 84 , and the insulation film 45 . Then, by conducting known photolithographic processes on the multilayer conductive film, the resist pattern having the same upper shape as the upper electrode 16 (which will be formed in a post process) and the upper layer conductive film 86 (which will be formed in a post process) is formed. Then, by etching the multilayer conductive film while using the resist pattern as a mask, the upper electrode 16 and the upper layer conductive film 86 are formed.
  • the semiconductor device 4 shown in FIG. 8 can be acquired.
  • the semiconductor device 4 has the support substrate ( 11 ) which is a semiconductor substrate, the lower electrode ( 43 ) formed on the support substrate ( 11 ) having the opening (i.e., the lower portion of the opening 42 a ) formed therein having multiple trenches crossing one another, each having a predetermined width, the insulation film ( 12 ) formed on the lower electrode ( 43 ) having the opening (i.e.
  • the opening 42 a extend to the interior of the lower electrode 43 , it is possible to enlarge the area between the lower electrode 43 and the intra-opening electrode 44 . Therefore, it is possible to obtain a higher capacitive density for the capacitive element 40 , and as a result, it is possible to obtain the desired capacitance with a small sized device. This means that it is possible to prevent the semiconductor device 4 from becoming larger in size.
  • the opening 42 a by forming the opening 42 a to have a structure in which multiple trenches each having a predetermined width cross one another, it is possible to enlarge the area of the opening 42 a in terms of a horizontal plane section, while maintaining the width of each trench. Therefore, it is possible to obtain an even higher capacitive density for the capacitive element 40 , and as a result, it is possible to obtain a desired capacitance with a small sized device. This means that it is possible to further prevent the semiconductor device 4 from becoming larger in size.
  • the insulation film 45 functioning as a capacitive insulation film is formed after the opening 42 a is formed in the interlayer insulation film 12 and the lower electrode 43 , the etching process for forming the opening 42 a will be made easier.
  • an insulation film that is a capacitive insulation film is supposed to be formed before forming the opening 42 a
  • the insulation film 45 is supposed to be formed after the opening 42 a are formed, and therefore, it is not necessary to have any such particular control for stopping the etching.
  • FIG. 1A is a sectional view of a semiconductor device 5 according to the third embodiment of the present invention.
  • FIG. 11A shows a sectional structure of the semiconductor device 5 cut off at a plane which is perpendicular to a support substrate 11 , and includes a capacitive element 50 and a second element 80 .
  • FIG. 11B is a sectional view showing the structure of a horizontal plane section of the capacitive element 50 taken along line VII-VII′ shown in FIG. 11A . That is, FIG. 11B is a sectional view showing a horizontal plane section between a lower electrode 53 and an upper electrode 16 in the capacitive element 50 .
  • FIG. 11A shows the sectional structure of the semiconductor device 5 which includes a plane VIII-VIII′ shown in FIG. 11B .
  • the semiconductor device 5 of this embodiment has the same structure as the semiconductor device 4 of the second embodiment, except that the capacitive element 40 constructed with the lower electrode 43 , the opening 42 a , the opening 43 a , the intra-opening electrode 44 , and the insulation film 45 is replaced with a capacitive element 50 constructed with a lower electrode 53 , an opening 52 a , an opening 53 a , an intra-opening electrode 54 , and an insulation film 55 . Since the rest of the structure is the same as the structure of the semiconductor device 4 of the second embodiment, a detailed description thereof will be omitted.
  • the opening 52 a extends to the interior the lower electrode 53 , but the bottom thereof does not contact with the support substrate 11 . That is, a lower portion of the opening 52 a is formed in the interior of the lower electrode 53 . Therefore, the insulation film 55 , the opening 53 a , and the intra-opening electrode 54 also extend to the interior of the lower electrode 53 .
  • the openings 52 a are columnar trenches each of which having a diameter about 0.9 ⁇ m.
  • the semiconductor device 5 of this embodiment has a structure in which the opening 42 a in the semiconductor device 4 of the second embodiment, which is the lattice-shape trench, is replaced with one or more columnar trenches.
  • the semiconductor device 5 of this embodiment has a structure in which the opening 43 a in the second embodiment is replaced with one or more columnar trenches (i.e., the openings 53 a ), and the intra-opening electrode 44 in the second embodiment is replaced with one or more columnar electrodes (i.e., the intra-opening electrodes 54 ).
  • the intra-opening electrodes 54 fill the interior of the openings 53 a , each of which having the same shape as the contact hole 82 a . Even if separate intra-opening electrodes 54 are used as portions of the upper electrode extending toward the lower electrode 54 in the capacitive element 50 , by having the intra-opening electrodes 54 extending into the interior of the lower electrode 53 as in this embodiment, it is possible to increase the effective area which functions as a capacitive element, and thereby, it is possible to achieve a higher capacitive density of the capacitive element 50 . Accordingly, it is possible to obtain a semiconductor device 5 which is capable of obtaining the desired capacitance with a small sized device.
  • a method of manufacturing the semiconductor device 5 according to the third embodiment of the present invention has the same processes as the method of manufacturing the semiconductor device 4 according to the second embodiment of the present invention, except that the resist pattern R 2 is replaced with a resist pattern having an opening which has the same opening shape as the opening 52 a . Note that in the following, redundant explanations will be omitted.
  • the semiconductor device 5 has the support substrate ( 11 ) which is a semiconductor substrate, the lower electrode ( 53 ) formed on the support substrate ( 11 ) having the openings (i.e., the lower portion of the openings 52 a ) formed therein, the insulation film ( 12 ) formed on the lower electrode ( 53 ) having the openings (i.e., the upper portion of the opening 52 a ) formed over the lower electrode 53 , the insulation film ( 55 ) formed on the sides and the bottoms of the openings ( 52 a ), the intra-opening electrodes ( 54 ) formed on the insulation film ( 55 ) inside the openings ( 52 a ), and the upper electrode ( 16 ) formed on the insulation film ( 55 ) and the intra-opening electrodes ( 54 ).
  • the openings 52 a extend to the inside of the lower electrode 53 , it is possible to enlarge the area between the lower electrode 53 and the intra-opening electrodes 54 . Therefore, it is possible to obtain a higher capacitive density for the capacitive element 50 , and as a result, it is possible to obtain a desired capacitance with a small sized device. This means that it is possible to prevent the semiconductor device 5 from becoming larger in size.
  • the insulation film 55 functioning as a capacitive insulation film is formed after the openings 52 a are formed in the interlayer insulation film 12 and in the lower electrode 53 , the etching process for forming the openings 52 a will be made easier.
  • an insulation film that is a capacitive insulation film is supposed to be formed before forming the openings 52 a
  • the insulation film 55 is supposed to be formed after the openings 52 a are formed, and therefore, it is not necessary to have any such particular control for stopping the etching.
  • FIG. 12A is a sectional view of a semiconductor device 6 according to the fourth embodiment of the present invention.
  • FIG. 12A shows a sectional structure of the semiconductor device 6 cut off at a plane which is perpendicular to a support substrate 11 , and includes a capacitive element 60 and a second element 80 .
  • FIG. 12B is a sectional view showing the structure of a horizontal plane section of the capacitive element 60 taken along a line IX-IX′ shown in FIG. 12A . That is, FIG. 12B is a sectional view showing a horizontal plane section between a lower electrode 63 and an upper electrode 16 in the capacitive element 60 .
  • FIG. 12A shows the sectional structure of the semiconductor device 6 which includes a plane X-X′ shown in FIG. 12A .
  • the semiconductor device 6 of this embodiment has the same structure as the semiconductor device 4 of the second embodiment except that the capacitive element 40 constructed with the lower electrode 43 , the opening 42 a , the opening 43 a , the intra-opening electrode 44 , and the insulation film 45 is replaced with a capacitive element 60 constructed with a lower electrode 63 , an opening 62 a , an opening 63 a , an intra-opening electrode 64 , and an insulation film 65 . Since the rest of the structure is the same as the structure of the semiconductor device 4 of the second embodiment, a detailed description thereof will be omitted.
  • the opening 62 a extends to the interior of the lower electrode 63 but the bottom thereof does not contact with the support substrate 11 . That is, a lower portion of the opening 62 a is formed in the interior of the lower electrode 63 . Therefore, the insulation film 65 , the opening 63 a , and the intra-opening electrode 64 also extend to the interior of the lower electrode 63 .
  • the openings 62 a are linear trenches, each of which having a width of about 0.9 ⁇ m and a length of about 8 ⁇ m.
  • the semiconductor device 6 of this embodiment has a structure in which the opening 42 a in the semiconductor device 4 of the second embodiment, which is the lattice-shape trench, is replaced with one or more linear trenches.
  • the semiconductor device 6 of this embodiment has a structure in which the opening 43 a in the second embodiment is replaced with one or more linear trenches (i.e., the openings 63 a ), and the intra-opening electrode 44 in the second embodiment is replaced with one or more linear electrodes (i.e., the intra-opening electrodes 64 ).
  • the intra-opening electrodes 64 fill the interior of the openings 63 a . Even if separate intra-opening electrodes 64 are used as portions of the upper electrode that extend toward the lower electrode 64 in the capacitive element 60 , by having the intra-opening electrodes 64 extend to the interior of the lower electrode 63 as in this embodiment, it is possible to increase the effective area which functions as a capacitive element, and thereby, it is possible to achieve a higher capacitive density of the capacitive element 60 . Accordingly, it is possible to obtain a semiconductor device 6 which is capable of obtaining the desired capacitance with a small sized device.
  • a method of manufacturing the semiconductor device 6 according to the fourth embodiment of the present invention has the same processes as the method of manufacturing the semiconductor device 4 according to the second embodiment of the present invention, except that the resist pattern R 2 is replaced with a resist pattern having an opening which has the same opening shape as the opening 62 a . Note also that in the following, redundant explanations will be omitted.
  • the semiconductor device 6 has the support substrate ( 11 ) which is a semiconductor substrate, the lower electrode ( 63 ) formed on the support substrate ( 11 ) having the openings (i.e. the lower portion of the openings 62 a ) formed therein, the insulation film ( 12 ) formed on the lower electrode ( 63 ) having the openings (i.e.
  • the openings 62 a extend to the interior of the lower electrode 63 , it is possible to enlarge the area between the lower electrode 63 and the intra-opening electrodes 64 . Therefore, it is possible to obtain a higher capacitive density for the capacitive element 60 , and as a result, it is possible to obtain the desired capacitance with a small sized device. This means that it is possible to prevent the semiconductor device 6 from becoming larger in size.
  • the insulation film 65 functioning as a capacitive insulation film is formed after the openings 62 a are formed in the interlayer insulation film 12 and the lower electrode 63 , the etching process for forming the openings 62 a will be made easier.
  • an insulation film that is a capacitive insulation film is supposed to be formed before forming the openings 62 a
  • the insulation film 65 is supposed to be formed after the openings 62 a are formed, and therefore, it is not necessary to have any such particular control for stopping the etching.
  • the present invention is not limited to this situation.
  • the present invention can be applied to a structure in which the lower electrode of a capacitive element is formed on an insulation film (e.g. an interlayer insulation film) formed over a support substrate.
  • an insulation film e.g. an interlayer insulation film
  • each of the trenches constructing the opening is about the same as the diameter of the contact holes 82 a
  • the present invention is not limited to this factor.
  • each trench of the opening ( 13 a , 23 a , 33 a , 43 a , 53 a or 63 a ) has an appropriate width which will not allow the conductor such as tungsten (W) that fills the interior of the opening to remain unnecessarily in a form of sidewalls, i.e., as long as each trench of the opening has an appropriate width which will allow only an appropriate amount of conductor to remain inside the opening to seal the opening at the bottom, the trenches of the opening may be changed in various ways.
  • W tungsten

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US11393801B2 (en) * 2019-10-16 2022-07-19 Samsung Electronics Co., Ltd. Discrete decoupling capacitor and integrated circuit chip package including same

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US7663241B2 (en) 2010-02-16
US20080042286A1 (en) 2008-02-21

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