US20060223308A1 - Apparatus for manufacturing a semiconductor device and method of forming the same - Google Patents
Apparatus for manufacturing a semiconductor device and method of forming the same Download PDFInfo
- Publication number
- US20060223308A1 US20060223308A1 US11/421,672 US42167206A US2006223308A1 US 20060223308 A1 US20060223308 A1 US 20060223308A1 US 42167206 A US42167206 A US 42167206A US 2006223308 A1 US2006223308 A1 US 2006223308A1
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- substrate
- oxide layer
- forming
- gate
- process module
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- 238000000034 method Methods 0.000 title claims abstract description 126
- 239000004065 semiconductor Substances 0.000 title abstract description 28
- 238000004519 manufacturing process Methods 0.000 title abstract description 15
- 239000000758 substrate Substances 0.000 claims description 92
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 7
- 229910000040 hydrogen fluoride Inorganic materials 0.000 claims description 4
- 238000011065 in-situ storage Methods 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 100
- 238000012546 transfer Methods 0.000 abstract description 39
- 238000004891 communication Methods 0.000 abstract description 20
- 238000000231 atomic layer deposition Methods 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 239000002245 particle Substances 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000004151 rapid thermal annealing Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 229910007245 Si2Cl6 Inorganic materials 0.000 description 4
- 229910003910 SiCl4 Inorganic materials 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 4
- 229910021341 titanium silicide Inorganic materials 0.000 description 4
- LXEXBJXDGVGRAR-UHFFFAOYSA-N trichloro(trichlorosilyl)silane Chemical compound Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl LXEXBJXDGVGRAR-UHFFFAOYSA-N 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 description 4
- 239000000356 contaminant Substances 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000011109 contamination Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000032258 transport Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3141—Deposition using atomic layer deposition techniques [ALD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67196—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the transfer chamber
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
Definitions
- the present invention relates to an apparatus for manufacturing a semiconductor device. It also relates to a method of forming the same. More particularly, the present invention relates to an apparatus for manufacturing a semiconductor device and to a method of manufacturing the same.
- a gate insulating layer is required to have a thin thickness and a small width in semiconductor devices such as a highly integrated dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, etc.
- DRAM highly integrated dynamic random access memory
- SRAM static random access memory
- flash memory etc.
- a gate oxide layer having a thickness of below about 10 ⁇ is demanded in a logic circuit that drives a memory circuit.
- process integration has been promoted in the semiconductor industry to meet technological and economical requirements.
- the process integration is defined as carrying out complex processes performed in different process chambers in a single cluster tool.
- the single cluster tool includes several chambers that are interconnected by a platform to continuously perform different processes.
- a method of forming a gate oxide layer of a semiconductor device is disclosed in Korean Patent Laid Open Publication No. 2001-0004969.
- a sheet-off process is performed on a surface of an active region provided on a substrate to remove a native oxide layer formed on the surface of the active region.
- An aluminum oxide layer is formed on the surface of the active region in an atomic layer deposition (ALD) chamber.
- the aluminum oxide layer is annealed in a reacting furnace under an N 2 O atmosphere to remove defects in the aluminum oxide layer, and to form an oxide nitride layer between the substrate and the aluminum oxide layer.
- a polysilicon layer is formed on the aluminum oxide layer.
- a word line including tungsten silicide, titanium silicide or tungsten is formed on the polysilicon layer.
- a cluster tool having high-pressure and heat-treatment chamber includes a polyhedral transfer chamber for providing an isolated space in which a substrate is transferred.
- a load-lock chamber is connected to a first side face of the transfer chamber.
- Process chambers are connected to second side faces of the transfer chamber.
- a batch type high-pressure and heat-treatment chamber is connected to a third face of the transfer chamber.
- the substrate that is processed in the process chambers is loaded into the high-pressure and heat-treatment chamber.
- a substrate transferring member transports the substrate between the load-lock chamber, the process chambers and the high-pressure and heat-treatment chamber.
- a native oxide layer grows on a gate oxide layer formed on the substrate to a thickness of above about 10 ⁇ .
- a gate electrode formed on the gate oxide layer having a thicker thickness may deteriorate the reliability of a semiconductor. It may be difficult to form a gate oxide layer having a thickness of below about 15 ⁇ using the conventional cluster tool.
- the substrate may be transported to another chamber for forming a gate electrode or a contact electrode. Accordingly, even though a gate oxide layer having a thickness of below about 15 ⁇ may be formed using the conventional cluster tool, a native oxide layer may grow on the gate oxide layer during transportation of the substrate.
- the gate oxide layer may not have a desired thickness owing to the native oxide layer.
- the native oxide layer may include particles that deteriorate performance and reliability of a semiconductor.
- an apparatus for manufacturing a semiconductor comprises a polyhedral transfer chamber a first process module for forming a gate dielectric layer by ALD, and a second process module for thermally treating the gate dielectric layer.
- the first process module is in communication with a first side of the transfer chamber.
- the second process module in communication with a second side of the transfer chamber.
- the apparatus further includes at least one load-lock chamber in communication with a third side of the transfer chamber.
- the apparatus further comprises another module for forming a first gate electrode on the gate dielectric layer using ALD.
- a method for forming a gate electrode comprises loading a substrate into a clustered apparatus; forming a gate dielectric layer on the substrate using an ALD method in the clustered apparatus; thermally treating the substrate having the gate dielectric layer formed thereon to densify the gate dielectric layer in the clustered apparatus; and forming a first gate electrode on the thermally treated gate oxide layer in the clustered apparatus.
- FIG. 1 is a plan view illustrating an apparatus for manufacturing a semiconductor device in accordance with an embodiment of the present invention.
- FIG. 2 is a plan view illustrating an apparatus for forming a gate electrode in accordance with another embodiment of the present invention
- FIG. 3 is a plan view illustrating an apparatus for forming a contact electrode in accordance with yet another embodiment of the present invention.
- FIG. 4 is a flow chart illustrating a method of forming a gate electrode in accordance with a still another embodiment of the present invention.
- FIG. 5 is a flow chart illustrating a method of forming a contact electrode in accordance with an embodiment of the present invention.
- an apparatus 100 for manufacturing a semiconductor device includes a polyhedral transfer chamber 110 , a first and a second process modules 120 and 130 , and load-lock chambers 50 and 70 .
- the transfer chamber 110 , the first and the second process modules 120 and 130 , and the load-lock chambers 50 and 70 are interconnected via a single platform.
- the apparatus 100 may perform complex processes for manufacturing a semiconductor device in continuous vacuum so that growth of a native oxide layer on a substrate may be suppressed and contaminants, such as particles, may be not created.
- the first and the second process modules 120 and 130 , and the load-lock chambers 50 and 70 are connected to sides of, and are in communication with, the polyhedral transfer chamber 110 , respectively.
- the numbers of the polyhedral sides may be determined in accordance with the complexity of the processes.
- a substrate 10 is transferred to the transfer chamber 110 subsequently through a substrate cassette 30 , a substrate transfer unit 40 and the load-lock chamber 50 .
- the substrate 10 is transferred to the second process module 130 through the transfer chamber 110 by a substrate transporting member such as a robot arm 115 .
- the interior of the apparatus 100 is maintained under vacuum so that growth of a native oxide layer on the substrate 10 may be suppressed and particles may be not created.
- the first process module 120 is connected to, and is in communication with, a first side of the transfer chamber 110 .
- the first process module 120 may include diverse process chambers in accordance with a process carried out therein.
- the first process module 120 may include a module for forming a gate oxide layer, such as an atomic layer deposition (ALD) chamber or a chemical vapor deposition (CVD) chamber.
- the first process module 120 may include the ALD chamber for forming an oxide layer having a thickness of not more than about 15 ⁇ .
- the gate oxide layer may include a silicon oxide layer or a silicon oxynitride layer.
- a silicon source including SiCl 4 , Si 2 Cl 6 or SiH 4 can be reacted with an oxygen source including H 2 O, O 2 , N 2 O or O 3 to form the silicon oxide layer.
- a silicon source including SiCl 4 , Si 2 Cl 6 or SiH 4 is reacted with an oxygen source including H 2 O, O 2 , N 2 O or O 3 and a nitrogen source including NH 4 or N 2 H 4 to form the silicon oxynitride layer.
- the first process module 120 may include a chamber for performing complex processes that include the removal of a native oxide layer and the formation of a gate oxide layer. That is, a wet cleaning process is performed on a substrate 10 using a chemical such as hydrogen fluoride (HF) in the first process module 120 to remove any native oxide layer formed on the substrate 10 .
- HF hydrogen fluoride
- a gate oxide layer is formed on the substrate 10 in the first process module 120 . Since the complex processes are carried out in the first process module 120 , the numbers of chambers may be decreased. Additionally, since the time for transferring the substrate 10 to another chamber is not needed, the amount of the substrate 10 treated per unit time may be increased. In particular, the gate oxide layer having a thickness of not more than about 15 ⁇ may be formed using the first process module 120 because the native oxide layer is removed from the substrate 10 .
- the second process module 130 is preferably connected to, and in communication with, a second side of the transfer chamber 110 .
- the second process module 130 may include a chamber for depositing polysilicon used as a first gate electrode.
- the first process module 120 may be used for forming a gate dielectric layer such as a gate oxide layer, or for removing a native oxide layer and forming a gate oxide layer
- the second process module 130 may be used for forming a gate electrode
- the complex processes are performed in the single-substrate type clustered apparatus 100 so that a gate structure having a thin gate oxide layer may be formed.
- the gate structure may be employed in a memory device, for example, a DRAM, an SRAM and a flash memory, to improve reliability of a semiconductor device.
- a third process module 140 for forming a second gate electrode may be further connected to, and in communication with, a third side of the transfer chamber 110 .
- the third process module 140 may include a chamber for depositing metal.
- the second gate electrode may include a material used for reducing a resistance of the first gate electrode such as tungsten, tungsten silicide or titanium silicide.
- the second process module 130 may include a chamber for performing complex processes that include a heat treatment of a gate oxide layer and the formation of a gate electrode. That is, a gate oxide layer formed on the substrate 10 is thermally treated using a rapid thermal annealing (RTA) process at a temperature of about 500° C. to about 1,100° C. A gate electrode may be formed on the annealed gate oxide layer. Since the complex processes are carried out in the second process module 130 , the numbers of chambers required for manufacturing a semiconductor device may be decreased. Additionally, since the time for transferring the substrate 10 to another chamber is not needed, the amount of the substrates 10 which can be treated per unit time may be increased.
- RTA rapid thermal annealing
- Separate chambers for performing the complex processes may be provided to the apparatus 100 .
- a fourth process module (not shown) for removing a native oxide layer may be connected to, and in communication with, a fourth side of the transfer chamber 110 .
- a fifth process module (not shown) for thermally treating a gate oxide layer may be connected to, and in communication with, the fourth side of the transfer chamber 110 .
- An RTA process may be carried out in the fifth process module at a temperature of about 500° C. to about 1,100° C.
- a single-substrate type clustered apparatus 200 for forming a gate electrode includes a polyhedral transfer chamber 210 , a first process module 220 for removing a native oxide layer, a second process module 230 for forming a gate oxide layer, a third process module 240 for thermally treating a gate oxide layer, a fourth process module for forming a first gate electrode, and load-lock chambers 50 and 70 .
- the load-lock chambers 50 , 70 and 210 and the modules 220 , 230 , 240 and 250 are interconnected via a single platform.
- the apparatus 200 may perform complex processes for manufacturing a semiconductor device under continuous vacuum so that growth of a native oxide layer may be suppressed and contaminants, such as particles, may be not created.
- the load-lock chambers 50 and 70 and the modules 220 , 230 , 240 and 250 are preferably connected to sides of and are in communication with, the polyhedral transfer chamber 210 , respectively.
- a substrate 10 is transferred to the transfer chamber 210 subsequently through a substrate cassette 30 , a substrate transfer unit 40 and the load-lock chamber 50 .
- the substrate 10 is transferred to another module through the transfer chamber 210 by a substrate transporting member such as a robot aim 215 .
- the interior of the apparatus 200 is maintained under vacuum so that growth of a native oxide layer may be suppressed and particles may be not created.
- the first process module 220 is preferably connected to, and is in communication with, a first side of the transfer chamber 210 .
- a wet cleaning process is performed on a substrate 10 using a chemical such as hydrogen fluoride (HF) in the first process module 220 to remove a native oxide layer formed on the substrate.
- HF hydrogen fluoride
- a gate oxide layer having a thickness of below about 15 ⁇ may be formed using the apparatus 200 because the native oxide layer is removed from the substrate 10 .
- the second process module 230 is preferably connected to, and is in communication with, a second side of the transfer chamber 210 .
- the second process module 230 may include an ALD chamber or a CVD chamber.
- the gate oxide layer may include silicon oxide or silicon oxynitride.
- the third process module 240 is preferably connected to, and is in communication with, a third side of the transfer chamber 210 .
- An RTA process may be performed in the third process module 240 at a temperature of about 500° C. to about 1,100° C.
- the gate oxide layer is thermally treated to improve its property.
- the fourth process module 250 for forming the first gate electrode is connected to, and is in communication with, a fourth side of the transfer chamber 210 .
- the fourth process module 250 may include a chamber for depositing polysilicon.
- the apparatus 200 may further include a fifth process module (not shown) for forming a second gate electrode.
- the fifth process module may be connected to, and is in communication with, a side of the transfer chamber 210 .
- the fifth process module may include a chamber for depositing metal.
- the second gate electrode may include a material used for reducing a resistance of the first gate electrode, for example, tungsten, tungsten silicide or titanium silicide.
- a single-substrate type clustered apparatus 300 for forming a contact electrode includes a polyhedral transfer chamber 310 , a first process module 320 for removing a native oxide layer, a second process module 330 for forming a contact electrode, and load-lock chambers 50 and 70 .
- the load-lock chambers 50 , 70 and 210 and the first and second modules 320 and 330 are interconnected via a single platform.
- the apparatus 300 may perform complex processes for manufacturing a semiconductor device under continuous vacuum so that growth of a native oxide layer may be suppressed and contaminants, such as particles, may be not created.
- the load-lock chambers 50 and 70 and the first and second modules 320 and 330 are connected to sides of the polyhedral transfer chamber 310 , respectively.
- a substrate 10 having a lower structure is transferred to the transfer chamber 310 subsequently through a substrate cassette 30 , a substrate transfer unit 40 and the load-lock chamber 50 .
- the lower structure may include a gate oxide layer pattern and first and second gate electrode patterns.
- the contact electrode may be electrically connected to source/drain regions on the substrate 10 .
- the first process module 320 is preferably connected to, and is in communication with, a first side of the transfer chamber 310 .
- a wet cleaning process is performed on a substrate 10 using a chemical such as hydrogen fluoride (HF) in the first process module 320 to remove a native oxide layer formed on the lower structure.
- HF hydrogen fluoride
- a resistance of the contact electrode may be reduced because the native oxide layer is removed from the substrate 10 .
- the second process module 330 is preferably connected to, and is in communication with, a second side of the transfer chamber 310 .
- the second process module 330 may include an ALD chamber or a CVD chamber.
- the apparatuses 100 , 200 and 300 have a cluster type.
- the apparatuses 100 , 200 and 300 may perform complex processes for manufacturing a semiconductor device under continuous vacuum so that growth of a native oxide layer may be suppressed. Accordingly, a highly integrated semiconductor device having a thin gate oxide layer may be manufactured using the apparatuses 100 , 200 and 300 . Further, the apparatuses 100 , 200 and 300 have a single-substrate type so that processing conditions of the complex process may be accurately controlled.
- step S 110 a substrate is loaded into the apparatus in accordance with an embodiment of the present invention.
- step S 120 a native oxide layer is removed from the substrate.
- step S 130 a gate oxide layer is formed on the substrate.
- step S 140 the substrate is thermally treated.
- step S 150 a first gate electrode is formed on the gate oxide layer.
- the method of forming the gate electrode in accordance with the first embodiment of the present invention may be carried out using the apparatus 200 .
- step S 110 the substrate 10 is loaded into the apparatus 200 .
- the substrate 10 is transported from the substrate cassette 30 to the substrate transferring unit 40 .
- the substrate 10 is transported to the load-lock chamber 50 using the substrate transferring unit 40 .
- Vacuum is provided into the apparatus 200 .
- the interior of the apparatus 200 may be maintained under vacuum, thereby preventing the growth of a native oxide layer and contamination by particles.
- step 120 the native oxide layer formed on the substrate 10 is removed.
- the substrate 10 is transported to the first process module 220 using the robot arm 215 .
- the native oxide layer is removed by a wet cleaning process using hydrogen fluoride.
- the gate oxide layer is formed on the substrate 10 .
- the substrate 10 is transported to the second process module 230 , using the robot arm 215 .
- the gate oxide layer is formed using an ALD process or a CVD process.
- the gate oxide layer may be formed by the ALD process.
- the gate oxide layer may include a silicon oxide layer or a silicon oxynitride layer.
- a silicon source including SiCl 4 , Si 2 Cl 6 or SiH 4 is reacted with an oxygen source including H 2 O, O 2 , N 2 O or O 3 to form the silicon oxide layer.
- a silicon source including SiCl 4 , Si 2 Cl 6 or SiH 4 is reacted with an oxygen source including H 2 O, O 2 , N 2 O or O 3 and a nitrogen source including NH 4 or N 2 H 4 to form the silicon oxynitride layer.
- step S 140 the substrate 10 is transported to the third process module 240 using the robot arm 215 .
- the substrate 10 is thermally treated by an RTA process at a temperature of about 500° C. to about 1,100° C.
- step S 150 the substrate 10 is transported to the fourth process module 250 using the robot arm 215 .
- a first gate electrode including polysilicon is formed on the gate oxide layer.
- a second gate electrode may be further formed on the first gate electrode.
- the second gate electrode may be formed in a chamber for depositing metal.
- the second gate electrode may include a material used for reducing a resistance of the first gate electrode, for example, tungsten, tungsten silicide or titanium silicide.
- the substrate 10 is unloaded from the apparatus 200 through the load-lock chamber 70 and the substrate transferring unit 50 .
- step S 210 a substrate having a lower structure is loaded into the apparatus in accordance with an embodiment of the present invention.
- step S 220 a native oxide layer is removed from the substrate.
- step S 230 a contact electrode is formed on the substrate.
- the method of forming the contact electrode may be carried out using the apparatus 300 in accordance with one embodiment of the present invention.
- the substrate 10 having the lower structure is loaded into the apparatus 300 using the robot arm 315 .
- the lower structure may include a gate oxide layer pattern and first and second gate electrode patterns.
- step 220 the substrate 10 is transported to the first process module 320 using the robot arm 315 .
- the native oxide layer may be removed by a wet cleaning process using hydrogen fluoride.
- the gate structure having the gate oxide layer that has a thickness of below about 15 ⁇ may be formed using the apparatus. Further, the method is performed on the single substrate so that processing conditions of the complex process may be accurately controlled.
- the single-substrate type clustered apparatus for forming a gate oxide layer that has a thickness of below about 15 ⁇ may be provided. Therefore, the single-substrate type clustered apparatuses for forming a gate electrode and a contact electrode, respectively, may be further provided.
- the gate oxide layer and the gate electrode or the lower structure and the contact electrode may be continuously formed under vacuum, a semiconductor device having a thin gate oxide layer on which a native oxide layer may grow by little may be manufactured, thereby improving reliability of the semiconductor device.
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- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
An apparatus for manufacturing a semiconductor includes a polyhedral transfer chamber, a first process module for forming a gate dielectric layer by ALD, and a second process module for thermally treating the gate dielectric layer. The first process module is in communication with a first side of the transfer chamber. The second process module in communication with a second side of the transfer chamber. The apparatus further includes at least one load-lock chamber in communication with a third side of the transfer chamber.
Description
- This application is a Divisional of U.S. patent application Ser. No. 10/835,372, filed on Apr. 28, 2004, now pending, which claims priority under 35 USC § 119 to Korean Patent Application No. 2003-27176, filed on Apr. 29, 2003, the contents of which are herein incorporated by reference in their entirety for all purposes.
- 1. Field of the Invention
- The present invention relates to an apparatus for manufacturing a semiconductor device. It also relates to a method of forming the same. More particularly, the present invention relates to an apparatus for manufacturing a semiconductor device and to a method of manufacturing the same.
- 2. Description of the Related Art
- As memory devices such as a computer has been widely used, a semiconductor device used for the memory device has been developed. From a functional point of view, it is required that a semiconductor device operates at a rapid speed and simultaneously has a great amount of storage capacitance. To meet these requirements, technologies for fabricating semiconductor devices have been developed to improve the degree of integration, reliability and response speed of semiconductor devices.
- In particular, as design rules have decreased for improving the degree of integration of semiconductor devices, a gate insulating layer is required to have a thin thickness and a small width in semiconductor devices such as a highly integrated dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, etc. A gate oxide layer having a thickness of below about 10 Å is demanded in a logic circuit that drives a memory circuit.
- On the other hand, process integration has been promoted in the semiconductor industry to meet technological and economical requirements. The process integration is defined as carrying out complex processes performed in different process chambers in a single cluster tool. The single cluster tool includes several chambers that are interconnected by a platform to continuously perform different processes.
- Various methods for manufacturing semiconductor devices using a cluster tool are known in the art. For instance, a method of forming a gate oxide layer of a semiconductor device is disclosed in Korean Patent Laid Open Publication No. 2001-0004969. According to the method, a sheet-off process is performed on a surface of an active region provided on a substrate to remove a native oxide layer formed on the surface of the active region. An aluminum oxide layer is formed on the surface of the active region in an atomic layer deposition (ALD) chamber. The aluminum oxide layer is annealed in a reacting furnace under an N2O atmosphere to remove defects in the aluminum oxide layer, and to form an oxide nitride layer between the substrate and the aluminum oxide layer. A polysilicon layer is formed on the aluminum oxide layer. A word line including tungsten silicide, titanium silicide or tungsten is formed on the polysilicon layer.
- When the substrate is, however, transported to the reacting furnace, vacuum may not be provided to the substrate. This causes growth of a native oxide layer on the aluminum oxide layer. As a result, it may be impossible to form a gate oxide layer having a thickness of below about 15 Å due to the native oxide layer.
- Further, a cluster tool having high-pressure and heat-treatment chamber, and a method of forming a thin layer using the same are disclosed in Korean Patent Laid Open Publication No. 2002-0030994. A cluster tool includes a polyhedral transfer chamber for providing an isolated space in which a substrate is transferred. A load-lock chamber is connected to a first side face of the transfer chamber. Process chambers are connected to second side faces of the transfer chamber. A batch type high-pressure and heat-treatment chamber is connected to a third face of the transfer chamber. The substrate that is processed in the process chambers is loaded into the high-pressure and heat-treatment chamber. A substrate transferring member transports the substrate between the load-lock chamber, the process chambers and the high-pressure and heat-treatment chamber.
- Since the batch type high-pressure and heat-treatment chamber is employed in the cluster tool, a native oxide layer grows on a gate oxide layer formed on the substrate to a thickness of above about 10 Å. A gate electrode formed on the gate oxide layer having a thicker thickness may deteriorate the reliability of a semiconductor. It may be difficult to form a gate oxide layer having a thickness of below about 15 Å using the conventional cluster tool. Furthermore, the substrate may be transported to another chamber for forming a gate electrode or a contact electrode. Accordingly, even though a gate oxide layer having a thickness of below about 15 Å may be formed using the conventional cluster tool, a native oxide layer may grow on the gate oxide layer during transportation of the substrate. The gate oxide layer may not have a desired thickness owing to the native oxide layer. The native oxide layer may include particles that deteriorate performance and reliability of a semiconductor.
- In one embodiment, an apparatus for manufacturing a semiconductor comprises a polyhedral transfer chamber a first process module for forming a gate dielectric layer by ALD, and a second process module for thermally treating the gate dielectric layer. The first process module is in communication with a first side of the transfer chamber. The second process module in communication with a second side of the transfer chamber. The apparatus further includes at least one load-lock chamber in communication with a third side of the transfer chamber.
- Preferably, the apparatus further comprises another module for forming a first gate electrode on the gate dielectric layer using ALD.
- In another embodiment, a method for forming a gate electrode comprises loading a substrate into a clustered apparatus; forming a gate dielectric layer on the substrate using an ALD method in the clustered apparatus; thermally treating the substrate having the gate dielectric layer formed thereon to densify the gate dielectric layer in the clustered apparatus; and forming a first gate electrode on the thermally treated gate oxide layer in the clustered apparatus.
- The above and other features and advantages of the invention will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings.
-
FIG. 1 is a plan view illustrating an apparatus for manufacturing a semiconductor device in accordance with an embodiment of the present invention. -
FIG. 2 is a plan view illustrating an apparatus for forming a gate electrode in accordance with another embodiment of the present invention; -
FIG. 3 is a plan view illustrating an apparatus for forming a contact electrode in accordance with yet another embodiment of the present invention; -
FIG. 4 is a flow chart illustrating a method of forming a gate electrode in accordance with a still another embodiment of the present invention; and -
FIG. 5 is a flow chart illustrating a method of forming a contact electrode in accordance with an embodiment of the present invention. - The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like reference numbers refer to similar or identical elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or “onto” another element, it can be directly on the other element or intervening elements may also be present.
- Hereinafter, an apparatus for manufacturing a semiconductor device and a method of forming a gate structure according to the present invention are illustrated in detail.
- Referring to
FIG. 1 , anapparatus 100, e.g., a single-substrate type clustered apparatus[100], for manufacturing a semiconductor device includes apolyhedral transfer chamber 110, a first and asecond process modules lock chambers transfer chamber 110, the first and thesecond process modules lock chambers apparatus 100 may perform complex processes for manufacturing a semiconductor device in continuous vacuum so that growth of a native oxide layer on a substrate may be suppressed and contaminants, such as particles, may be not created. - The first and the
second process modules lock chambers polyhedral transfer chamber 110, respectively. The numbers of the polyhedral sides may be determined in accordance with the complexity of the processes. - A
substrate 10 is transferred to thetransfer chamber 110 subsequently through asubstrate cassette 30, asubstrate transfer unit 40 and the load-lock chamber 50. After a process is performed on thesubstrate 10 in thefirst process module 120, thesubstrate 10 is transferred to thesecond process module 130 through thetransfer chamber 110 by a substrate transporting member such as arobot arm 115. After thesubstrate 10 is loaded into the load-lock chamber 50, the interior of theapparatus 100 is maintained under vacuum so that growth of a native oxide layer on thesubstrate 10 may be suppressed and particles may be not created. - The
first process module 120 is connected to, and is in communication with, a first side of thetransfer chamber 110. Thefirst process module 120 may include diverse process chambers in accordance with a process carried out therein. Thefirst process module 120 may include a module for forming a gate oxide layer, such as an atomic layer deposition (ALD) chamber or a chemical vapor deposition (CVD) chamber. Preferably, thefirst process module 120 may include the ALD chamber for forming an oxide layer having a thickness of not more than about 15 Å. - The gate oxide layer may include a silicon oxide layer or a silicon oxynitride layer. A silicon source including SiCl4, Si2Cl6 or SiH4 can be reacted with an oxygen source including H2O, O2, N2O or O3 to form the silicon oxide layer. A silicon source including SiCl4, Si2Cl6 or SiH4 is reacted with an oxygen source including H2O, O2, N2O or O3 and a nitrogen source including NH4 or N2H4 to form the silicon oxynitride layer.
- Alternatively, the
first process module 120 may include a chamber for performing complex processes that include the removal of a native oxide layer and the formation of a gate oxide layer. That is, a wet cleaning process is performed on asubstrate 10 using a chemical such as hydrogen fluoride (HF) in thefirst process module 120 to remove any native oxide layer formed on thesubstrate 10. A gate oxide layer is formed on thesubstrate 10 in thefirst process module 120. Since the complex processes are carried out in thefirst process module 120, the numbers of chambers may be decreased. Additionally, since the time for transferring thesubstrate 10 to another chamber is not needed, the amount of thesubstrate 10 treated per unit time may be increased. In particular, the gate oxide layer having a thickness of not more than about 15 Å may be formed using thefirst process module 120 because the native oxide layer is removed from thesubstrate 10. - The
second process module 130 is preferably connected to, and in communication with, a second side of thetransfer chamber 110. Thesecond process module 130 may include a chamber for depositing polysilicon used as a first gate electrode. When thefirst process module 120 may be used for forming a gate dielectric layer such as a gate oxide layer, or for removing a native oxide layer and forming a gate oxide layer, and thesecond process module 130 may be used for forming a gate electrode, the complex processes are performed in the single-substrate type clusteredapparatus 100 so that a gate structure having a thin gate oxide layer may be formed. The gate structure may be employed in a memory device, for example, a DRAM, an SRAM and a flash memory, to improve reliability of a semiconductor device. - In addition, when the
second process module 130 may be used for forming a first gate electrode, athird process module 140 for forming a second gate electrode may be further connected to, and in communication with, a third side of thetransfer chamber 110. Thethird process module 140 may include a chamber for depositing metal. The second gate electrode may include a material used for reducing a resistance of the first gate electrode such as tungsten, tungsten silicide or titanium silicide. - Alternatively, the
second process module 130 may include a chamber for performing complex processes that include a heat treatment of a gate oxide layer and the formation of a gate electrode. That is, a gate oxide layer formed on thesubstrate 10 is thermally treated using a rapid thermal annealing (RTA) process at a temperature of about 500° C. to about 1,100° C. A gate electrode may be formed on the annealed gate oxide layer. Since the complex processes are carried out in thesecond process module 130, the numbers of chambers required for manufacturing a semiconductor device may be decreased. Additionally, since the time for transferring thesubstrate 10 to another chamber is not needed, the amount of thesubstrates 10 which can be treated per unit time may be increased. - Separate chambers for performing the complex processes, respectively, may be provided to the
apparatus 100. Namely, when thefirst process module 120 may be used for forming a gate oxide layer, a fourth process module (not shown) for removing a native oxide layer may be connected to, and in communication with, a fourth side of thetransfer chamber 110. - Further, when the
second process module 130 is used for forming a first gate electrode, a fifth process module (not shown) for thermally treating a gate oxide layer may be connected to, and in communication with, the fourth side of thetransfer chamber 110. An RTA process may be carried out in the fifth process module at a temperature of about 500° C. to about 1,100° C. - Referring to
FIG. 2 , a single-substrate type clusteredapparatus 200 for forming a gate electrode includes apolyhedral transfer chamber 210, afirst process module 220 for removing a native oxide layer, asecond process module 230 for forming a gate oxide layer, athird process module 240 for thermally treating a gate oxide layer, a fourth process module for forming a first gate electrode, and load-lock chambers lock chambers modules apparatus 200 may perform complex processes for manufacturing a semiconductor device under continuous vacuum so that growth of a native oxide layer may be suppressed and contaminants, such as particles, may be not created. - The load-
lock chambers modules polyhedral transfer chamber 210, respectively. Asubstrate 10 is transferred to thetransfer chamber 210 subsequently through asubstrate cassette 30, asubstrate transfer unit 40 and the load-lock chamber 50. After a process is performed on thesubstrate 10 in any module among themodules substrate 10 is transferred to another module through thetransfer chamber 210 by a substrate transporting member such as arobot aim 215. After thesubstrate 10 is loaded into the load-lock chamber 50, the interior of theapparatus 200 is maintained under vacuum so that growth of a native oxide layer may be suppressed and particles may be not created. - The
first process module 220 is preferably connected to, and is in communication with, a first side of thetransfer chamber 210. A wet cleaning process is performed on asubstrate 10 using a chemical such as hydrogen fluoride (HF) in thefirst process module 220 to remove a native oxide layer formed on the substrate. A gate oxide layer having a thickness of below about 15 Å may be formed using theapparatus 200 because the native oxide layer is removed from thesubstrate 10. - The
second process module 230 is preferably connected to, and is in communication with, a second side of thetransfer chamber 210. Thesecond process module 230 may include an ALD chamber or a CVD chamber. The gate oxide layer may include silicon oxide or silicon oxynitride. - The
third process module 240 is preferably connected to, and is in communication with, a third side of thetransfer chamber 210. An RTA process may be performed in thethird process module 240 at a temperature of about 500° C. to about 1,100° C. The gate oxide layer is thermally treated to improve its property. - The
fourth process module 250 for forming the first gate electrode is connected to, and is in communication with, a fourth side of thetransfer chamber 210. Thefourth process module 250 may include a chamber for depositing polysilicon. - Additionally, the
apparatus 200 may further include a fifth process module (not shown) for forming a second gate electrode. The fifth process module may be connected to, and is in communication with, a side of thetransfer chamber 210. The fifth process module may include a chamber for depositing metal. The second gate electrode may include a material used for reducing a resistance of the first gate electrode, for example, tungsten, tungsten silicide or titanium silicide. - Referring to
FIG. 3 , a single-substrate type clusteredapparatus 300 for forming a contact electrode includes apolyhedral transfer chamber 310, afirst process module 320 for removing a native oxide layer, asecond process module 330 for forming a contact electrode, and load-lock chambers lock chambers second modules apparatus 300 may perform complex processes for manufacturing a semiconductor device under continuous vacuum so that growth of a native oxide layer may be suppressed and contaminants, such as particles, may be not created. - The load-
lock chambers second modules polyhedral transfer chamber 310, respectively. Asubstrate 10 having a lower structure is transferred to thetransfer chamber 310 subsequently through asubstrate cassette 30, asubstrate transfer unit 40 and the load-lock chamber 50. The lower structure may include a gate oxide layer pattern and first and second gate electrode patterns. In this embodiment, the contact electrode may be electrically connected to source/drain regions on thesubstrate 10. - The
first process module 320 is preferably connected to, and is in communication with, a first side of thetransfer chamber 310. A wet cleaning process is performed on asubstrate 10 using a chemical such as hydrogen fluoride (HF) in thefirst process module 320 to remove a native oxide layer formed on the lower structure. A resistance of the contact electrode may be reduced because the native oxide layer is removed from thesubstrate 10. - The
second process module 330 is preferably connected to, and is in communication with, a second side of thetransfer chamber 310. Thesecond process module 330 may include an ALD chamber or a CVD chamber. - In above-described embodiments, the
apparatuses apparatuses apparatuses apparatuses - Referring to
FIG. 4 , in step S110, a substrate is loaded into the apparatus in accordance with an embodiment of the present invention. In step S120, a native oxide layer is removed from the substrate. In step S130, a gate oxide layer is formed on the substrate. In step S140, the substrate is thermally treated. Finally, in step S150, a first gate electrode is formed on the gate oxide layer. - The method of forming the gate electrode in accordance with the first embodiment of the present invention may be carried out using the
apparatus 200. - Referring to
FIGS. 2 and 4 , in step S110, thesubstrate 10 is loaded into theapparatus 200. Thesubstrate 10 is transported from thesubstrate cassette 30 to thesubstrate transferring unit 40. Thesubstrate 10 is transported to the load-lock chamber 50 using thesubstrate transferring unit 40. Vacuum is provided into theapparatus 200. The interior of theapparatus 200 may be maintained under vacuum, thereby preventing the growth of a native oxide layer and contamination by particles. - In
step 120, the native oxide layer formed on thesubstrate 10 is removed. Particularly, thesubstrate 10 is transported to thefirst process module 220 using therobot arm 215. The native oxide layer is removed by a wet cleaning process using hydrogen fluoride. - In
step 130, the gate oxide layer is formed on thesubstrate 10. In particular, thesubstrate 10 is transported to thesecond process module 230, using therobot arm 215. The gate oxide layer is formed using an ALD process or a CVD process. Preferably, the gate oxide layer may be formed by the ALD process. The gate oxide layer may include a silicon oxide layer or a silicon oxynitride layer. A silicon source including SiCl4, Si2Cl6 or SiH4 is reacted with an oxygen source including H2O, O2, N2O or O3 to form the silicon oxide layer. A silicon source including SiCl4, Si2Cl6 or SiH4 is reacted with an oxygen source including H2O, O2, N2O or O3 and a nitrogen source including NH4 or N2H4 to form the silicon oxynitride layer. - In step S140, the
substrate 10 is transported to thethird process module 240 using therobot arm 215. Thesubstrate 10 is thermally treated by an RTA process at a temperature of about 500° C. to about 1,100° C. - In step S150, the
substrate 10 is transported to thefourth process module 250 using therobot arm 215. A first gate electrode including polysilicon is formed on the gate oxide layer. - In step S160, a second gate electrode may be further formed on the first gate electrode. The second gate electrode may be formed in a chamber for depositing metal. The second gate electrode may include a material used for reducing a resistance of the first gate electrode, for example, tungsten, tungsten silicide or titanium silicide.
- The
substrate 10 is unloaded from theapparatus 200 through the load-lock chamber 70 and thesubstrate transferring unit 50. - Referring to
FIG. 5 , in step S210, a substrate having a lower structure is loaded into the apparatus in accordance with an embodiment of the present invention. In step S220, a native oxide layer is removed from the substrate. In step S230, a contact electrode is formed on the substrate. - The method of forming the contact electrode may be carried out using the
apparatus 300 in accordance with one embodiment of the present invention. - Referring to
FIGS. 3 and 5 , in step S210, thesubstrate 10 having the lower structure is loaded into theapparatus 300 using therobot arm 315. The lower structure may include a gate oxide layer pattern and first and second gate electrode patterns. - In
step 220, thesubstrate 10 is transported to thefirst process module 320 using therobot arm 315. The native oxide layer may be removed by a wet cleaning process using hydrogen fluoride. - According to the method, the gate structure having the gate oxide layer that has a thickness of below about 15 Å may be formed using the apparatus. Further, the method is performed on the single substrate so that processing conditions of the complex process may be accurately controlled.
- According to an embodiment of the present invention, the single-substrate type clustered apparatus for forming a gate oxide layer that has a thickness of below about 15 Å may be provided. Therefore, the single-substrate type clustered apparatuses for forming a gate electrode and a contact electrode, respectively, may be further provided.
- Furthermore, since the gate oxide layer and the gate electrode or the lower structure and the contact electrode may be continuously formed under vacuum, a semiconductor device having a thin gate oxide layer on which a native oxide layer may grow by little may be manufactured, thereby improving reliability of the semiconductor device.
- Although the present invention has been described in connection with a single-substrate type clustered apparatus, one skilled in the art will appreciate that the principles of the present invention may be equally applied to other type of clustered apparatus.
- Having described the preferred embodiments of the present invention, it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiment of the present invention disclosed which is within the scope and the spirit of the invention outlined by the appended claims.
Claims (10)
1. A method for forming a gate electrode comprising:
loading a substrate into a clustered apparatus;
forming a gate dielectric layer on the substrate using an ALD method in the clustered apparatus;
thermally treating the substrate having the gate dielectric layer formed thereon to densify the gate dielectric layer in the clustered apparatus; and
forming a first gate electrode on the thermally treated gate oxide layer in the clustered apparatus.
2. The method of claim 1 , further comprising removing any native oxide layer formed on the substrate before forming the gate dielectric layer.
3. The method of claim 1 , wherein the forming the gate dielectric layer, thermally treating the substrate, and forming the first gate electrode are performed in situ and continuously under vacuum.
4. The method of claim 1 , wherein thermally treating the substrate is performed at a temperature of from about 500° C. to about 1,100° C.
5. The method of claim 1 , wherein any native oxide layer is removed using hydrogen fluoride.
6. The method of claim 1 , wherein forming the first electrode comprises performing ALD, further comprising forming a second gate electrode on the first gate electrode using CVD.
7. The method of claim 1 , wherein forming the first gate electrode is formed under vacuum.
8. A method for forming a contact electrode comprising:
loading a substrate having a lower structure into a single-substrate type clustered apparatus;
removing a native oxide layer formed on the substrate; and
forming a contact electrode on the substrate.
9. The method of claim 8 , wherein the native oxide layer is removed using hydrogen fluoride.
10. The method of claim 8 , wherein the apparatus is structured such that forming a gate dielectric layer by ALD, thermally treating the gate dielectric layer, and forming the first gate electrode are performed continuously under vacuum.
Priority Applications (1)
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US11/421,672 US20060223308A1 (en) | 2003-04-29 | 2006-06-01 | Apparatus for manufacturing a semiconductor device and method of forming the same |
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KR2003-27176 | 2003-04-29 | ||
KR10-2003-0027176A KR100524197B1 (en) | 2003-04-29 | 2003-04-29 | Single wafer type manufacturing device of semiconductor device and method of forming gate electrode and contact plug using the same |
US10/835,372 US7077929B2 (en) | 2003-04-29 | 2004-04-28 | Apparatus for manufacturing a semiconductor device |
US11/421,672 US20060223308A1 (en) | 2003-04-29 | 2006-06-01 | Apparatus for manufacturing a semiconductor device and method of forming the same |
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US10/835,372 Division US7077929B2 (en) | 2003-04-29 | 2004-04-28 | Apparatus for manufacturing a semiconductor device |
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US11/421,672 Abandoned US20060223308A1 (en) | 2003-04-29 | 2006-06-01 | Apparatus for manufacturing a semiconductor device and method of forming the same |
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Cited By (2)
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US20090104100A1 (en) * | 2006-03-07 | 2009-04-23 | Hiroshi Imamura | Method for detoxifying hcd gas and apparatus therefor |
CN102442550A (en) * | 2010-09-16 | 2012-05-09 | 东京毅力科创株式会社 | Transfer device, processing system, control method of transfer device |
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US7317229B2 (en) * | 2005-07-20 | 2008-01-08 | Applied Materials, Inc. | Gate electrode structures and methods of manufacture |
US20080132060A1 (en) * | 2006-11-30 | 2008-06-05 | Macronix International Co., Ltd. | Contact barrier layer deposition process |
US7695761B1 (en) * | 2006-12-21 | 2010-04-13 | Western Digital (Fremont), Llc | Method and system for providing a spin tunneling magnetic element having a crystalline barrier layer |
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US8194365B1 (en) | 2009-09-03 | 2012-06-05 | Western Digital (Fremont), Llc | Method and system for providing a read sensor having a low magnetostriction free layer |
FR2973159B1 (en) * | 2011-03-22 | 2013-04-19 | Soitec Silicon On Insulator | METHOD FOR MANUFACTURING BASE SUBSTRATE |
KR20140003154A (en) * | 2012-06-29 | 2014-01-09 | 에스케이하이닉스 주식회사 | Method for manufacturing semiconductor device |
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Also Published As
Publication number | Publication date |
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KR100524197B1 (en) | 2005-10-27 |
KR20040093302A (en) | 2004-11-05 |
US20040219772A1 (en) | 2004-11-04 |
US7077929B2 (en) | 2006-07-18 |
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