KR100309125B1 - Method of forming a gate oxide in a semiconductor device - Google Patents
Method of forming a gate oxide in a semiconductor device Download PDFInfo
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- KR100309125B1 KR100309125B1 KR1019990025748A KR19990025748A KR100309125B1 KR 100309125 B1 KR100309125 B1 KR 100309125B1 KR 1019990025748 A KR1019990025748 A KR 1019990025748A KR 19990025748 A KR19990025748 A KR 19990025748A KR 100309125 B1 KR100309125 B1 KR 100309125B1
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- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 239000010408 film Substances 0.000 claims abstract description 43
- 239000010409 thin film Substances 0.000 claims abstract description 41
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims abstract description 39
- 238000000151 deposition Methods 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 230000008021 deposition Effects 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910008484 TiSi Inorganic materials 0.000 claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 4
- 229920005591 polysilicon Polymers 0.000 claims abstract description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 4
- 239000010937 tungsten Substances 0.000 claims abstract description 4
- 230000007547 defect Effects 0.000 claims abstract description 3
- 150000004767 nitrides Chemical class 0.000 claims 1
- 238000000137 annealing Methods 0.000 abstract description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 abstract description 2
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 150000002926 oxygen Chemical class 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- 229910018516 Al—O Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- IUHFWCGCSVTMPG-UHFFFAOYSA-N [C].[C] Chemical compound [C].[C] IUHFWCGCSVTMPG-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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- H01L29/517—
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- H01L29/518—
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Abstract
본 발명은 필드 산화막에 의해 분리된 실리콘 기판 상부의 액티브 영역 표면을 시트-오프하여 자연산화막을 제거한 후 ALD 증착 장비에서 Al2O3박막을 증착하는 제 1 단계와, 상기 Al2O3박막을 반응로에서 N2O 분위기로 어닐 공정을 수행하여 상기 Al2O3박막 내의 결함 제거 및 상기 실리콘 기판과 상기 Al2O3박막사이에 옥시나이트라이드막을 형성하는 제 2 단계와, 상기 Al2O3박막 상부에 폴리 실리콘막을 증착한 후, 그 위에 WSix, TiSi2또는 텅스텐 막을 증착하여 워드라인을 형성하는 제 3 단계를 포함하여 이루어진 반도체 소자의 게이트 산화막 형성 방법을 제공한다.The present invention provides a first step of depositing an Al 2 O 3 thin film in an ALD deposition apparatus after removing a natural oxide film by sheet-offing an active region surface of an upper part of a silicon substrate separated by a field oxide film, and the Al 2 O 3 thin film. in a reaction with N 2 O atmosphere by performing the annealing process, the Al 2 O 3 and remove defects in the thin film, and a second step formed between the silicon substrate and the Al 2 O 3 thin film fluoride oxynitride, the Al 2 O A method of forming a gate oxide film of a semiconductor device, comprising: depositing a polysilicon film on an upper portion of a third thin film, and then depositing a WSix, TiSi 2, or tungsten film to form a word line.
Description
본 발명은 반도체 소자의 게이트 산화막 형성 방법에 관한 것으로, 특히ALD(Atomic layer deposition) 방법으로 증착한 Al2O3박막에 N2O 어닐(Anneal)공정을 수행하여 고신뢰도, 저누설전류의 Al2O3박막 형성 및 Al2O3박막과 실리콘 기판 사이에 핫 캐리어 인젝션(Hot carrier injection)에 대해 내성이 큰 옥시나이트라이드막을 형성하여 전체적으로 고신뢰도 및 저누설전류의 게이트 유전체를 얻을 수 있는 반도체 소자의 게이트 산화막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate oxide film of a semiconductor device. In particular, an Al 2 O 3 thin film deposited by an ALD (Atomic layer deposition) method is subjected to an N 2 O annealing process to perform high reliability and low leakage current. 2 O 3 thin film is formed, and Al 2 O 3 to form a thin film with a film fluoride large resistance oxynitride against hot carrier injection (hot carrier injection) between the silicon substrate and overall reliability and semiconductor to obtain a gate dielectric of a low leakage current A method of forming a gate oxide film of an element is provided.
게이트 산화막의 두께가 얇아짐에 따라 디렉트 터널링(Direct tunneling)등으로 인하여 게이트 산화막을 통한 누설 전류가 크게 증가하는 등의 문제로 인하여 게이트 산화막의 두께를 40Å 이하로 낮추는데 있어서 어려움이 있다.As the thickness of the gate oxide film becomes thinner, there is a difficulty in reducing the thickness of the gate oxide film to 40 kΩ or less due to a problem such that leakage current through the gate oxide film is greatly increased due to direct tunneling.
이러한 단점을 보완하기 위해 종래의 열산화막으로 게이트 산화막을 사용하는 대신에 열산화막에 비해 유전상수가 커서 같은 유효산화막 두께를 위해 물질의 두께가 두꺼운 박막을 증착하여 디렉트 터널링에 의한 게이트 누설 전류를 줄일 수 있는 Al2O3박막(K=약 8.5)이 개발되고 있는 실정이다.To compensate for this drawback, instead of using a gate oxide as a conventional thermal oxide, a thin film of thick material is deposited for effective oxide thickness, which is larger than that of thermal oxide, thereby reducing gate leakage current due to direct tunneling. Al 2 O 3 thin film (K = about 8.5) is being developed.
이러한 Al2O3박막에 의한 게이트 유전체 형성 방법 중 H2O와 TMA(Al(CH3)3)을 사용한 ALD 방법이 있는데, 이 방법은 TMA 에 포함되어 있는 C(탄소)가 Al2O3박막 증착 후 제거되지 않고 박막에 남아있기 때문에 주의 깊은 열처리가 필요한 실정이다.Among the gate dielectric formation methods using the Al 2 O 3 thin film, there is an ALD method using H 2 O and TMA (Al (CH 3 ) 3 ), in which the C (carbon) contained in the TMA is Al 2 O 3. Careful heat treatment is required because the film is not removed after the deposition and remains in the film.
또한, 실리콘 기판위에 Al2O3박막을 곧바로 증착할 경우 Si/Al2O3계면에 굉장히 많은 인터페이스 상태가 형성될 가능성이 있고, 디바이스 동작시 핫 캐리어스트레스에 대한 내성이 약화될 가능성이 매우 많다.In addition, if Al 2 O 3 thin films are directly deposited on the silicon substrate, there is a possibility that a large number of interface states are formed at the Si / Al 2 O 3 interface, and the resistance to hot carrier stress is weakened during device operation. .
따라서, 본 발명은 ALD 방법으로 증착한 Al2O3박막에 N2O 어닐 공정을 수행함으로써, 상술한 단점을 해결할 수 있는 반도체 소자의 게이트 산화막 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a gate oxide film of a semiconductor device capable of solving the above-described disadvantages by performing an N 2 O annealing process on an Al 2 O 3 thin film deposited by an ALD method.
상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 게이트 산화막 형성 방법은 필드 산화막에 의해 분리된 실리콘 기판 상부의 액티브 영역 표면을 시트-오프하여 자연산화막을 제거한 후 ALD 증착 장비에서 Al2O3박막을 증착하는 제 1 단계와, 상기 Al2O3박막을 반응로에서 N2O 분위기로 어닐 공정을 수행하여 상기 Al2O3박막 내의 결함 제거 및 상기 실리콘 기판과 상기 Al2O3박막사이에 옥시나이트라이드막을 형성하는 제 2 단계와, 상기 Al2O3박막 상부에 폴리 실리콘막을 증착한 후, 그 위에 WSix, TiSi2또는 텅스텐 막을 증착하여 워드라인을 형성하는 제 3 단계를 포함하여 이루어진 것을 특징으로 한다.In the method for forming a gate oxide film of a semiconductor device according to the present invention for achieving the above object, Al 2 O 3 in an ALD deposition apparatus after removing a natural oxide film by sheet-off the surface of the active region on the silicon substrate separated by the field oxide film a first step of depositing a thin film, the Al 2 O 3 thin film in a reaction with N 2 O atmosphere, performing an annealing process to remove defects in the Al 2 O 3 thin film and between the silicon substrate and the Al 2 O 3 thin film And a third step of forming an oxynitride film on the Al 2 O 3 thin film, and then forming a word line by depositing a WSix, TiSi 2 or tungsten film thereon. It is characterized by.
본 발명은 간단한 어닐 공정을 통해 신뢰성이 우수하며 게이트 누설전류가 작은 고유전체 게이트 박막을 형성할 수 있다.The present invention can form a high dielectric gate thin film having excellent reliability and a small gate leakage current through a simple annealing process.
도 1(a) 내지 도 1(c)는 본 발명에 따른 게이트 산화막 형성 방법을 설명하기 위해 도시한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of a device shown for explaining a method of forming a gate oxide film according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>
1: 실리콘 기판 2: 필드산화막1: silicon substrate 2: field oxide film
3: 액티브 영역 4: Al2O3 3: active area 4: Al 2 O 3
5: H2O 6: TMA5: H 2 O 6: TMA
7: N2O 8: 옥시나이트라이드막7: N 2 O 8: oxynitride film
9: 폴리 실리콘 10: WSix 또는 TiSi2, W9: polysilicon 10: WSix or T i Si 2 , W
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1(a) 내지 도 1(c)는 본 발명에 따른 게이트 산화막 형성 방법을 설명하기 위해 도시한 단면도이다.1 (a) to 1 (c) are cross-sectional views illustrating a method of forming a gate oxide film according to the present invention.
도 1(a)에서, 실리콘 기판(1) 상부의 필드 산화막(2)에 의해 분리된 액티브 영역(3)을 HF 에 의해 표면을 시트-오프(Sheet-off)하여 자연 산화막을 제거한 후 ALD 증착 장비에서 H2O(5) 와 TMA(6)(Al(CH3)3) 소스를 사용하여 Al2O3박막(4)을 50 내지 100Å 두께로 얇게 증착한다.In FIG. 1A, the active region 3 separated by the field oxide film 2 on the silicon substrate 1 is sheet-off the surface by HF to remove the native oxide film, and then ALD deposition. In the equipment, a thin film of Al 2 O 3 thin film (4) was deposited to a thickness of 50 to 100 μs using H 2 O (5) and TMA (6) (Al (CH 3 ) 3 ) sources.
도 1(b)에서, 증착된 Al2O3박막(4)을 반응로에서 N2O(7) 분위기로 어닐 공정을 수행한다. 이때, 어닐 공정 온도는 활성화 산소가 충분히 나오고 써멀 버지트(Thermal budget)을 낮게 가져가기 위해 800 내지 900℃에서 수행한다.In FIG. 1 (b), the deposited Al 2 O 3 thin film 4 is annealed in an N 2 O (7) atmosphere in a reactor. At this time, the annealing process temperature is carried out at 800 to 900 ℃ to get enough activated oxygen and lower the thermal budget (Thermal budget).
그리고, 반응로의 용적을 고려해서 N2O(7) 가스의 플로우 비는 5 내지 20ℓ로 하고, 압력은 감압 혹은 상압분위기에서 행한다. 이때 N2O(7)가 분해되어 NO와 활성화 산소가 발생하게 되는데 이때 발생한 활성화 산소가 Al2O3박막(4) 증착시 함유되어 있는 탄소(C)와 결합하여 CO 나 CO2형태로 변하여 제거되기 때문에 Al2O3박막(4)의 누설전류 소스를 제거해 주는 효과를 가져온다.In consideration of the volume of the reactor, the flow ratio of the N 2 O (7) gas is set to 5 to 20 l, and the pressure is performed in a reduced pressure or atmospheric pressure atmosphere. At this time, N 2 O (7) is decomposed to generate NO and activated oxygen. At this time, the activated oxygen is combined with carbon (C) contained in the deposition of Al 2 O 3 thin film (4) to form CO or CO 2 . Since it is removed, the effect of removing the leakage current source of the Al 2 O 3 thin film (4).
또한, 활성화 산소는 원자 크기가 작기때문에 증착이 빨라서 Al2O3박막(4) 밑부분까지 충분히 확산하여 탄소를 제거해줄 뿐만아니라, 실리콘 기판과 반응하여 SiO2막을 형성하여 인터페이스 상태가 상태적으로 적은 Si/SiO2계면을 만들게 되고, 함께 확산하여 들어간 NO 분자에 의해 이렇게 생성된 산화막이 질화되어 전체적으로 신뢰성이 우수한 아주 얇은 옥시나이트라이드막(8)을 형성하게 되어, 핫 캐리어 스트레스에 대한 내성을 증가시키게 된다. 또한, Al2O3박막(4)에도 NO가 반응하여 미결합 Al-O 본드(bond)에 N을 효과적으로 결합하여 Al2O3박막(4)의 신뢰성을 올릴 수 있다. 또한, 상기 Al2O3박막(4) 및 옥시나이트라이드막(8) 증착시 공정 시간을 줄이기 위해 ALD 증착 장비와 RTO를 클러스터(Cluster)화 시킨 시스템을 이용하여 증착한다.In addition, since activated oxygen has a small atomic size, deposition is fast, and it diffuses sufficiently to the bottom of the Al 2 O 3 thin film 4 to remove carbon, and also reacts with a silicon substrate to form an SiO 2 film to maintain an interface state. As a result, a small Si / SiO 2 interface is produced, and the oxide film thus formed is nitrided by the NO molecules diffused together to form a very thin oxynitride film (8) with excellent overall reliability, thereby improving resistance to hot carrier stress. Is increased. In addition, Al 2 O 3 thin film 4 also is NO can react to increase the reliability of the non-joined Al-O bond (bond) to effectively combine the N to Al 2 O 3 thin film (4). In addition, in order to reduce the process time when the Al 2 O 3 thin film 4 and the oxynitride film 8 are deposited, the ALD deposition apparatus and the RTO are deposited using a clustered system.
도 1(c)에서, Al2O3박막(4) 위에 폴리 실리콘막(9)을 증착한 후, 그 위에 WSix, TiSi2또는 W(텅스텐) 막(10)을 증착하여 워드라인을 형성한다.In FIG. 1 (c), a polysilicon film 9 is deposited on an Al 2 O 3 thin film 4, and then a WSix, TiSi 2 or W (tungsten) film 10 is deposited thereon to form a word line. .
상술한 바와 같이 본 발명은 고신뢰도 및 저누설전류의 고유전율의 게이트 유전체를 복잡한 공정을 거치지 않고 간단한 어닐 공정을 추가하여 형성시킬 수 있다. 전저 열산화막에 비해 상대적으로 유전상수가 큰 Al2O3박막을 증착하여 디렉트 터널링 전류에 의한 게이트 누설전류를 억제시킬 수 있다. 또한 Al2O3박막이 후속 N2O 가스에 의한 어닐 공정시 활성화 산소에 의해 Al2O3박막의 카본(Carbon)을 포함한 유기물이 제거되어 이에 의한 누설전류를 줄일 수 있고, 활성화 산소와 NO 분자에 의해 Al2O3박막과 실리콘 사이에 옥시나이트라이드막을 형성할 수 있어 계면 특성이 향상될 뿐만 아니라, 핫 캐리어 인잭션에 대한 내성을 증가시킬 수 있다. 또한, Al2O3박막에도 NO가 반응하여 미결합 Al-O 본드(bond)에 N을 효과적으로 결합하여 Al2O3박막의 신뢰성을 증가시켜 전반적으로 신뢰성이 향상된 고유전율을 가진 박막을 제조할 수 있다.As described above, the present invention can form a high dielectric constant gate dielectric of high reliability and low leakage current by adding a simple annealing process without a complicated process. The gate leakage current caused by the direct tunneling current can be suppressed by depositing an Al 2 O 3 thin film having a relatively high dielectric constant compared to the total low thermal oxide film. In addition, Al 2 O 3 thin film is subsequently N 2 O the organic material including carbon (Carbon) of Al 2 O 3 film by active oxygen during the annealing process by the gas is removed it is possible to reduce the leakage current due to, free radicals and NO By the molecule, an oxynitride film can be formed between the Al 2 O 3 thin film and the silicon, thereby improving the interfacial properties and increasing the resistance to hot carrier interaction. In addition, NO reacts to Al 2 O 3 thin film non-joined Al-O bond (bond) to effectively combine the N to Al 2 O increases the reliability of the third thin film to produce a thin film having an overall reliability enhanced by a high-k Can be.
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| KR100522765B1 (en) * | 2001-07-03 | 2005-10-19 | 주식회사 컴텍스 | Manufacturing method of base for semiconductor device using material of GaN series |
| KR100609047B1 (en) * | 2004-10-30 | 2006-08-09 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
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| KR100431306B1 (en) * | 2002-08-30 | 2004-05-12 | 주식회사 하이닉스반도체 | Method for formig gate of semiconductor device using gate oxide made of double film of aluminium oxide and yttrium oxynitride |
| KR100524197B1 (en) | 2003-04-29 | 2005-10-27 | 삼성전자주식회사 | Single wafer type manufacturing device of semiconductor device and method of forming gate electrode and contact plug using the same |
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| KR100522765B1 (en) * | 2001-07-03 | 2005-10-19 | 주식회사 컴텍스 | Manufacturing method of base for semiconductor device using material of GaN series |
| KR100609047B1 (en) * | 2004-10-30 | 2006-08-09 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
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