US20060139989A1 - Integration of 1T1R CBRAM memory cells - Google Patents

Integration of 1T1R CBRAM memory cells Download PDF

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Publication number
US20060139989A1
US20060139989A1 US11/311,435 US31143505A US2006139989A1 US 20060139989 A1 US20060139989 A1 US 20060139989A1 US 31143505 A US31143505 A US 31143505A US 2006139989 A1 US2006139989 A1 US 2006139989A1
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solid body
memory cell
body electrolyte
memory cells
layer
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Ulrike Gruning Von Schwerin
Thomas Happ
Cay-Uwe Pinnow
Thomas Rohr
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Infineon Technologies AG
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/041—Modification of switching materials after formation, e.g. doping
    • H10N70/046—Modification of switching materials after formation, e.g. doping by diffusion, e.g. photo-dissolution
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8822—Sulfides, e.g. CuS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8825—Selenides, e.g. GeSe
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Definitions

  • the invention relates to a memory cell array or a memory cell field, respectively, for the integration of resistively switching solid body electrolyte memory cells.
  • the invention further relates to a method for manufacturing a memory cell field with an integrated arrangement of solid body electrolyte memory cells, and in particular of 1T1R CBRAM memory cells in minimum structure size.
  • An integrated memory device usually comprises a cell field (array) consisting of a plurality of memory cells and a matrix of electroconductive supply lines which is composed of column and row supply lines or word and bit lines, respectively.
  • a cell field array
  • the memory cells are each positioned at the crosspoints of the electroconductive supply lines that are each connected with the memory cell via an upper electrode or top electrode and a lower electrode or bottom electrode.
  • the corresponding word and bit lines are selected and impacted either with a write current or with a read current.
  • a RAM memory device is a memory with optional access, i.e. data can be stored under a particular address and can be read out again under this address later.
  • a particular kind of RAM semiconductor memories are DRAMs (Dynamic Random Access Memory) which comprise in general only one single, correspondingly controlled capacitive element per memory cell, e.g. a trench capacitor, with the capacitance of which one bit each can be stored as charge. The charge or the information stored, however, remains for a relatively short time only in a DRAM memory cell, so that a so-called “refresh” must be performed regularly, with the corresponding information content being written in the memory cell again, or being refreshed, respectively.
  • DRAMs Dynamic Random Access Memory
  • the presently common semiconductor memory technologies are based primarily on the principle of charge storage in materials produced by standard CMOS (complement metal oxide semiconductor) processes.
  • CMOS complementary metal oxide semiconductor
  • the problem of the leaking currents existing with the DRAM memory concept, which result in a loss of charge or a loss of information, respectively, has so far been solved insufficiently only by the permanent refreshing of the stored charge, which results in a high energy consumption of the DRAM chip.
  • the flash memory concept underlies the problem of write and read cycles limited by barrier layers, wherein no optimum solution has been found yet, either, for the high switching voltages and the slow read and write cycles. Moreover, long write times in the range of several ps to ms are required.
  • CB memory cells or CBRAM memory cells have also become known recently, in which digital information can be stored by a resistive switching process.
  • a CB or CBRAM memory cell is adapted to be switched between different electric resistance values by means of bipolar electric pulsing.
  • such an element can be switched between a very high (e.g. in the GOhm range) and a distinctly lower resistance value (e.g. in the kOhm range) by applying short current or voltage pulses, wherein the switching rates may be below one microsecond.
  • the structure of conductive bridging memory cells (CB memory cells or CBRAM memory cells) or solid body electrolyte memory cells, respectively, consists substantially of an upper electrode or top electrode and a lower electrode or bottom electrode, and of a volume with electrochemically active material positioned therebetween, which may be doped with a metal, in particular with silver or e.g. copper.
  • a metal in particular with silver or e.g. copper.
  • an electrochemically active material for the ion conductor materials such as Ge x Se 1-x , Ge x S 1-x , WO x , Cu—S, Cu—Se, or similar chalcogenide-containing compounds are generally used.
  • reactive materials for the reactive metal electrode copper (CU) or in particular silver (Ag) are typically used.
  • the CBRAM cell typically has an asymmetric structure, i.e. the electrode material 1 is different from the electrode material 2 .
  • the above-mentioned switching process is on principle based on the fact that, by applying appropriate current or voltage pulses of particular intensity and duration at the electrodes in the active chalcogenide material positioned between the electrodes, metal-rich elements of so-called clusters continue to increase in their number and/or size in the chalcogenide material volume until the two electrodes are finally electroconductively bridged, i.e. electroconductively connected with each other, which corresponds to the electroconductive state of the CB memory cell.
  • this process can be reversed again, whereby the corresponding CB memory cell can be returned to a highly resistive state.
  • the electroconductivity of the CB memory cell can be assigned to a logic memory state (logic “1” or logic “0”).
  • the current is evaluated at an applied read voltage U read , wherein U read ⁇ U write (write voltage).
  • CB memory cells have to be manufactured in an array with an integration that is as dense as possible, or with good scalability, respectively, making use of a technology that is as simple as possible and that yields reliable results.
  • metal ions diffuse in a controlled manner from the anode into the ion conductor by applying bipolar voltage pulses at the electrodes.
  • these metal ions are identical to the anode material, i.e. metal anode material is oxidized and is dissolved in the ion conductor on applying of a positive write voltage U write >U read .
  • the ion diffusion may be controlled by the duration, the amplitude, and the polarity of the electric voltage externally impressed to the memory cell.
  • the metal cations diffuse, under the influence of the electric field applied externally via the electrodes of the CB memory cell, through the ion conductor in the direction of the cathode.
  • a lowly resistive metal bridge between the anode and the cathode can be formed, this causing the electric resistance of the memory cell to drop strongly since the highly resistive solid body electrolyte matrix is electrically short-circuited.
  • the above-mentioned crosspoint architecture has, for instance, been suggested, in which the memory cells are controlled via a matrix of word and bit lines as well as a 1TnR arrangement in which a transistor, together with a number of switchable resistors, constitutes a memory cell.
  • the above-mentioned crosspoint architecture has, however, not been known any integration concept so far.
  • Another object consists in providing a method for manufacturing a memory cell array with a 1T1R CBRAM architecture which is as cheap as possible.
  • this object is solved by a memory cell field with the features indicated in claim 1 , and by a method according to claim 8 .
  • a memory cell field with an integrated arrangement of solid body electrolyte memory cells, and in particular of CBRAM solid body electrolyte memory cells with 1T1R architecture, wherein said memory cells each comprise a layer stack comprising at least a bottom and a top electroconductive, in particular metal, layer, and a layer of solid body electrolyte material or ion conductor material, respectively, positioned therebetween, and wherein each solid body electrolyte memory cells is adapted to be controlled via a word line, a bit line and a plate line by means of a selection transistor, wherein at least a number of solid body electrolyte memory cells in the memory cell field comprise a common plate electrode or are connected to a common plate line, respectively.
  • a substantial feature of the present invention consequently consists in that an electrode, in particular the top electrode or the plate line of a memory cell field, respectively, is designed as continuous plate or electrode, respectively, so that the memory cells of an array have a common electrode (plate line) or are connected with each other via a common electrode, respectively.
  • a common electrode has the advantage that no expensive lithography processes with critical structures are necessary for their manufacturing.
  • the structure of the inventive memory cell array is simplified and, on the other hand, the effort of the processes for their manufacturing is reduced and is thus cheaper.
  • the above-mentioned objects are solved by a method for manufacturing at least one memory cell field with an integrated arrangement of solid body electrolyte memory cells, and in particular of CBRAM solid body electrolyte memory cells, for generating a memory array with 1T1R architecture, wherein the method comprises at least the following steps:
  • generating a layer stack on the prestructured bottom electrode material layer by depositing a solid body electrolyte material or an ion conductor material, as well as a reactive metal, and
  • top electrode material layer for generating a second electrode to which a number of solid body electrolyte memory cells are commonly connected.
  • the present invention suggests a possibility of integration, whereby the manufacturing of a CB memory cell array or of a CBRAM memory cell array, respectively, can be integrated into a CMOS manufacturing method.
  • CMOS manufacturing method different possibilities of realizing a CBRAM module with an integrated arrangement of 1T1R CBRAM memory cells in minimum structure size are indicated.
  • the integration approach according to the present invention it is possible to achieve a high memory cell density in the memory cell array, and to program, erase, and read individual CBRAM memory cells in the array independently of each other by a predetermined switching pulse scheme.
  • a particular advantage of the present invention consists in that, by the use of the so-called common plate architecture, the common top electrode or the plate line, respectively, of the CBRAM memory cells need not be structured individually for each CBRAM memory cell.
  • a substantial simplification with respect to process technology is achieved vis-à-vis a standard integration approach which, for instance, provides for the structuring of a top electrode or plate line, respectively, for every single memory cell.
  • the principle of the present invention is based on the providing and the use of a common top electrode or plate line, respectively, for a plurality of CBRAM memory cells that are integrated or arranged in a memory cell array.
  • this common top electrode is structured at the edge of the memory cell array or of the memory cell field, respectively, or at some other suitable position.
  • the manufacturing of the common top electrode or plate line, respectively, is preferably performed by dry chemical or wet chemical methods, and is thus restricted in space.
  • the CBRAM memory cell is placed on the so-called CC contact (“node contact”) or over the so-called CC contact, respectively, which is connected with the respective selection transistor in the silicon substrate via a co-called CA contact.
  • the active material e.g. GeSe/Ag
  • the solid body electrolyte memory cell is structured.
  • the active solid body electrolyte material is filled into the back-etched CC contact and subsequently planarized. This process is preferably performed with the additional establishing of barrier layers so as to limit the diffusion region of the solid body electrolyte material.
  • the finished and planarized contact is, for instance, etched back by wet chemical etching by a particular degree so as to create the space required for the memory resistor.
  • the memory cell array or the cell field, respectively may be covered relative to the periphery by means of an uncritical lithography step.
  • the ion conductor material e.g. GeSe
  • the reactive metal e.g. Ag
  • CMP chemical mechanical polishing
  • the plate electrode is structured after its deposition with a likewise uncritical lithography step at the edges of the memory cell array or the cell field, respectively, or at some other suitable position.
  • a diffusion barrier for instance, of SiN is applied conformely after the back-etching of the plug (and TiN liner), and subsequently the contact to the plug is re-established by means of anisotropic etching. This prevents a possible diffusing out of the active materials such as silver ions.
  • the necessary planarizing of the active material may also be performed without the use of a CMP tool.
  • the plug (with the TiN liner) is etched back, and subsequently the ion conductor material is deposited.
  • the reactive metal (Ag) is deposited and the chalcogenide layer created is doped, wherein, again, a complete via filling is avoided.
  • a nitride sacrifice layer and a thick oxide sacrifice layer are deposited to balance the remaining topography. This is then chemically mechanically polished in a standard process with a CMP tool down to the nitride layer and planarized, and the SiN of the diffusion barrier is etched at the exposed positions. Subsequently, the active material can be structured in the vias with a wet etching step, and finally the now superfluous sacrifice layers can be removed again. Then, the plate electrode can be deposited and structured.
  • a fourth preferred embodiment of the inventive method wherein an additional diffusion barrier, for instance, of SiN, is also introduced, and the contact to the plug is made by an anisotropic back-etching step.
  • an additional diffusion barrier for instance, of SiN
  • a substantial aspect with the above-described embodiments of the inventive method consists in that, as a result, a plurality of memory cells are electrically connected to a common top electrode, the so-called plate line (PL).
  • PL plate line
  • the plate line may, during the operation of the CBRAM memory cells, in the simplest case be kept on a constant potential level, which has been explained in conjunction with FIG. 1 with respect to the pulse triggering of the bit line and the word line of a resistively switching solid body electrolyte memory cell.
  • the result of this is, in addition to a simple connection of the memory cells, also the advantage of a minimal mutual influencing of the respective memory cells.
  • FIG. 1 shows two diagrams for pulse triggering of the bit line and of the word line of a resistively switching solid body electrolyte memory cell, e.g. a CBRAM memory cell;
  • FIG. 2 shows an arrangement or an electric circuit, respectively, of solid body electrolyte memory cells in 1T1R CBRAM architecture based on a memory cell field with 1T1R CBRAM memory cells according to a preferred embodiment of the present invention
  • FIG. 3 shows a schematic sectional view through a memory cell field with 1T1R CBRAM architecture according to a first preferred embodiment of the present invention
  • FIG. 4 shows a schematic sectional view through a memory cell field with 1T1R CBRAM architecture according to a first preferred embodiment of the present invention illustrated in FIG. 3 , wherein the plane of the sectional view of FIG. 4 extends along the line A-A plotted in FIG. 3 ;
  • FIG. 5 shows a schematic sectional view through a memory cell field with 1T1R CBRAM architecture according to a second preferred embodiment of the present invention
  • FIG. 6 shows a schematic sectional view through a memory cell field with 1T1R CBRAM memory cells according to a third preferred embodiment of the present invention
  • FIGS. 7 and 8 show schematic representations of individual process steps of a preferred embodiment of the inventive method for manufacturing a memory cell field with 1T1R CBRAM architecture according to the embodiment of the present invention illustrated in FIG. 6 ;
  • FIG. 9 shows a schematic sectional view through a memory cell field with 1T1R CBRAM architecture according to a third preferred embodiment of the present invention.
  • FIG. 1 shows respective diagrams for pulse triggering in the form of voltage pulses at the bit line V(BL) and at the word line V(WL) of a resistively switching solid body electrolyte memory cell.
  • the diagrams each show a time sequence of a write pulse “write”, a read pulse “read”, an erase pulse “erase”, and a further read pulse “read” at the electrodes of the solid body electrolyte memory cell.
  • metal ions are diffused in a controlled manner from the anode into the ion conductor of the solid body electrolyte memory cell by applying bipolar voltage pulses at the electrodes of the solid body electrolyte memory cell.
  • a positive electric write voltage U write >U read at the electrodes of the solid body electrolyte memory cell the metal cations diffuse from the anode under the influence of the external electric field through the ion conductor in the direction of the cathode, and dissolve in the ion conductor.
  • the extent of the ion diffusion is controlled by the duration, the amplitude, and the polarity of the electric voltage impressed externally in the CB memory cell.
  • FIG. 2 shows an arrangement of solid body electrolyte memory cells in an electric circuit with 1T1R CBRAM architecture, as it may be the basis for a memory cell field with 1T1R CBRAM memory cells according to a preferred embodiment of the present invention.
  • the memory cell field comprises electric supply lines that are oriented orthogonally to each other in a matrix of word lines WL and bit lines BL.
  • a resistor or a resistively switching solid body electrolyte memory cell R respectively, each is connected in series with a selection transistor T, wherein the transistor T is connected with the bit line BL at the side opposite to the resistor and with the adjacent word line WL at its gate.
  • the resistively switching solid body electrolyte memory cell or CBRAM memory cell R is connected to a plate line.
  • the plate lines extend in a different plane than the word lines WL and the bit lines BL and are therefore not illustrated in FIG. 2 .
  • the plate lines PL of the CBRAM memory cells R are connected with one another, i.e. all CBRAM memory cells R of a memory cell field, or the CBRAM memory cells from a particular region of the memory cells field, respectively, are connected to a common plate line.
  • a CA contact Between the bit line BL and the transistor T there is positioned a CA contact, and between the transistor T and the solid body electrolyte memory cell or CBRAM memory cell R there is positioned a CC contact, preferably of tungsten (W), which will be described in more detail in the following.
  • W tungsten
  • FIG. 3 shows a schematic sectional view through a memory cell field with 1T1R architecture according to a first preferred embodiment of the present invention.
  • FIG. 3 includes a line A-A which constitutes the section plane of FIG. 4 .
  • a CB contact At the left of the line A-A there is represented a sectional view through a CB contact while on the right side of the line A-A there is represented a sectional view through a CC contact (“node contact”).
  • the inventive memory cell field is built up on a silicon substrate S in which transistors or selection transistors T, respectively, are structured which are each separated from one another by isolations I.
  • the transistors are each contacted via a so-called CA contact CA on which there is positioned a so-called CB contact connecting the CA contact and thus the selection transistor T with a bit line BL.
  • a selection transistor T is connected with the active material of a resistively switching solid body electrolyte memory cell R via the CA contact and the CC contact, this resulting in the 1T1R architecture of the memory cell field.
  • the solid body electrolyte memory cell is connected with a plate line PL that is formed as a continuous electrode plate.
  • a plate line PL that is formed as a continuous electrode plate.
  • FIG. 4 shows a schematic sectional view through a memory cell field with 1T1R CBRAM architecture according to a first preferred embodiment of the invention illustrated in FIG. 3 , wherein the plane of the sectional view of FIG. 4 extends along the line A-A plotted in FIG. 3 .
  • the inventive memory cell field is structured on a silicon substrate S in which transistors or selection transistors T are structured, the source/drain regions SD of which are isolated from each other, for instance, by a shallow trench isolation STI.
  • the selection transistors T are each contacted via a so-called CA contact CA which is in turn connected with the active material R of the solid body electrolyte memory cell by a CC contact. Since the bit line BL is positioned in a different plane than the paper plane of FIG. 4 , the bit line BL is indicated in dashed lines.
  • the CC contact thus constitutes the lower electrode or bottom electrode of the solid body electrolyte memory cell.
  • the plate line PL thus constitutes the common upper electrode or the common top electrode, respectively, for a number of solid body electrolyte memory cells.
  • FIG. 5 shows a schematic sectional view through a memory cell field with 1T1R CBRAM architecture according to a second preferred embodiment of the present invention.
  • the embodiment of the inventive memory cell field illustrated in FIG. 5 corresponds in many features to the embodiment illustrated in FIG. 4 , so that the following description restricts itself to the differing features.
  • the active material of the solid body electrolyte memory cell may contain silver-bearing material that has a high mobility in SiO 2 , so that is adapted to diffuse out of the region with the active material R and to spread in an uncontrolled manner in the memory cell field.
  • silver impurities the characteristic curves of the selection transistors T and the electric behavior of other components in the silicon substrate S may be modified, and thus the function of the memory cell field may be impaired as a whole.
  • a memory cell field according to the second preferred embodiment of the present invention to laterally restrict the region with the active material R of the solid body electrolyte memory cell by means of barrier layers B.
  • the edges of the region with the active material R of the solid body electrolyte memory cell are provided with a barrier layer B that extends from the bottom electrode or the CC contact CC, respectively, to the upper electrode or the plate line PL, respectively, of the solid body electrolyte memory cell.
  • the barrier layer B may be manufactured of a nitride compound such as silicon nitride, aluminum nitride, or another isolating material.
  • FIG. 6 shows a schematic sectional view through a memory cell field with 1T1R CBRAM memory cells according to a third preferred embodiment of the present invention.
  • the embodiment of the inventive memory cell field illustrated in FIG. 6 corresponds in most features to the embodiments illustrated in FIG. 4 or in FIG. 5 , so that the following description restricts itself to the deviating features.
  • the region with the active material R of the solid body electrolyte memory cell is designed in the form of a well, so that the region with the active material or chalcogenide material R, respectively, comprises a recess at the upper face that is in communication with the plate line PL. This way, the region with the active material R can be formed with an exactly defined strength, this improving the determinability of the characteristic curves and of the threshold voltages of the solid body electrolyte memory cell.
  • FIGS. 7 and 8 show a schematic representation of individual process steps of a preferred embodiment of the inventive method for manufacturing a memory cell field with 1T1R CBRAM architecture according to the embodiment of the present invention illustrated in FIG. 6 .
  • a layer stack is first of all generated which comprises a number of different material layers, as is illustrated in the top portion of FIG. 7 .
  • the bottom layer consists of a silicon substrate S that has been preprocessed in a suitable manner.
  • the structures for the bottom electrodes or CC contacts or also so-called plugs CC for the solid body electrolyte memory cells are incorporated by suitable lithographic processes and etching processes, and are preferably filled with tungsten and planarized such that the desired tungsten plugs are generated.
  • An active material or chalcogenide material R with a defined thickness for the CB memory cell is deposited on the CC contacts CC and doped with silver.
  • a nitride layer N is deposited which serves in subsequent process steps as a protective layer for the layer with the active material R, and as an etch stop layer.
  • a layer of silicon oxide SO is deposited over the nitride layer N.
  • the following method step is illustrated in the bottom portion of FIG. 7 , in which the silicon oxide layer SO is, for instance, by a dry or wet chemical process, etched away down to the nitride layer N and is planarized.
  • the nitride layer N may be used as an etch stop layer.
  • a kind of protective cap or a dummy oxide SO, respectively, of silicon oxide remains left in the region above the active material R over the nitride layer N.
  • the following process step is illustrated in the top portion of FIG. 8 , in which a vertically acting erosion process is, for instance, performed by sputtering and mainly erodes the chalcogenide material R and leaves the silicon oxide SO substantially unchanged, so that the nitride layer N below the dummy oxide SO also remains left.
  • the barrier B acts as an isolator since it preferably only consists of Si 3 N 4 or of AlN. In this preferably wet chemical partial chalcogenide etching process the chalcogenide material R is therefore removed only partially at the lateral edges in the region between the protective cap SO of silicon oxide and the silicon substrate S.
  • the protective cap or the dummy oxide SO, respectively, of silicon oxide is removed completely together with the remaining nitride layer N by a suitable etching method or by a plurality of suitable method steps, respectively, so that a well W with defined strength is formed in the region with the active chalcogenide material R.
  • a continuous layer of metal electrode material is deposited, so that a continuous upper electrode or a common top electrode, respectively, or a common plate line can be formed.
  • the structure of the inventive memory cell field illustrated in FIG. 6 can be generated, in which the region with the active material or the chalcogenide material R, respectively, has a defined strength.
  • FIG. 9 shows a schematic sectional view through a memory cell field with 1T1R CBRAM architecture according to a third preferred embodiment of the present invention.
  • the embodiment of the inventive memory cell field illustrated in FIG. 9 corresponds in most features to the embodiment illustrated in FIG. 6 , so that the following description concentrates on the deviating features.
  • the region with the active material R of the solid body electrolyte memory cell designed in the form of a well W so that the region with the active material or chalcogenide material R, respectively, comprises a recess at the upper area that is in communication with the plate line PL.
  • the region with the active material R is limited laterally by barrier layers B so as to prevent a lateral diffusing out of substances from the region with the active material R.
  • Such a structure may, for instance be generated in that the processes described by means of FIGS. 7 and 8 are performed, with the difference that the process step for removing the active chalcogenide material R at the lateral edges in the region between the protective cap SO of silicon oxide and the silicon substrate S ( FIG. 8 top) is performed correspondingly longer, so that the edges of the active material R are completely eroded.
  • the generated gaps could then, for instance, be filled with SiN, and subsequently the contact to the plug could be re-established by anisotropic etching.

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