US20060084255A1 - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
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- US20060084255A1 US20060084255A1 US11/246,337 US24633705A US2006084255A1 US 20060084255 A1 US20060084255 A1 US 20060084255A1 US 24633705 A US24633705 A US 24633705A US 2006084255 A1 US2006084255 A1 US 2006084255A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 79
- 238000004519 manufacturing process Methods 0.000 title claims description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 68
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 67
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 63
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 62
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 51
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 44
- 239000010937 tungsten Substances 0.000 claims abstract description 44
- 239000003870 refractory metal Substances 0.000 claims abstract description 38
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
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- 238000000151 deposition Methods 0.000 claims description 4
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- 238000000034 method Methods 0.000 description 38
- 230000008569 process Effects 0.000 description 26
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- -1 tungsten nitride Chemical class 0.000 description 11
- 239000003990 capacitor Substances 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 230000007547 defect Effects 0.000 description 8
- 238000002955 isolation Methods 0.000 description 7
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- 238000007254 oxidation reaction Methods 0.000 description 7
- 239000010410 layer Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
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- 238000011109 contamination Methods 0.000 description 3
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- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
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- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
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- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Definitions
- the present invention relates to a semiconductor device and a method of manufacturing the same.
- the invention particularly relates to a metal-oxide semiconductor field-effect transistor (MOSFET) having a gate electrode of a poly-metal structure consisting of high-melting point metal and polycrystalline silicon (poly-silicon), and a method of manufacturing the MOSFET.
- MOSFET metal-oxide semiconductor field-effect transistor
- a so-called poly-metal structure gate electrode (poly-metal gate) having a refractory metal film such as tungsten stacked on a poly-silicon film is used in order to reduce resistance of a gate electrode (see Japanese Patent Application Laid-Open Nos. 2000-156497 and 2002-141500).
- a gate dielectric film positioned at a lower part of the gate electrode is also slightly etched. Therefore, a breakdown voltage of the gate dielectric film decreases and a leak current increases in this state.
- an oxide film is formed on a side surface of the gate electrode. In other words, a so-called light oxidation is carried out.
- a refractory metal scatters to a silicon substrate during the light oxidation, which substantially increases a junction leakage.
- the inventors have carried out detailed researches into the phenomenon in which the junction leakage does not decrease to a predetermined level or lower even when a light oxidation is carried out after covering the side surfaces of a refractory metal film with a silicon nitride film. It is found through the research that the silicon nitride film that covers the side surfaces of the refractory metal film has many defects. These defects are considered to be attributable to damages caused, by etching, to a part where the silicon nitride film remains to cover the side surfaces of the refractory metal film, at the time of etching back the silicon nitride film.
- a semiconductor device including: a semiconductor substrate; a gate dielectric film formed on the semiconductor substrate; a poly-metal gate electrode having at least a poly-silicon film and a refractory metal film formed on the gate dielectric film; a gate cap that covers an upper surface of the poly-metal gate electrode; and a sidewall that covers side surfaces of the poly-metal gate electrode.
- the sidewall has a multilayer structure including at least a first dielectric film and a second dielectric film made of a material different from that of the first dielectric film.
- the first dielectric film has a vertical part that is in contact with the side surfaces of the poly-metal gate electrode, and a horizontal part that extends substantially parallel with a front surface of the semiconductor substrate from the gate dielectric film side end at the vertical part.
- the sidewall that covers the side surfaces of the poly-metal gate electrode has a multilayer structure. Therefore, serious defects do not occur in the sidewall. Consequently, it is possible to effectively prevent a scattering of the refractory metal contained in the poly-metal gate electrode. Accordingly, junction leakage attributable to the refractory metal can be reduced substantially.
- a method of manufacturing a semiconductor device including: a first step of forming a gate dielectric film on a semiconductor substrate; a second step of forming at least a poly-silicon film and a refractory metal film on the gate dielectric film; a third step of patterning at least the refractory metal film; a fourth step of forming a sidewall having a multilayer structure on side surfaces of the patterned refractory metal film; a fifth step of patterning the poly-silicon film; and a sixth step of oxidizing the side surfaces of the patterned poly-silicon film.
- the poly-silicon film is patterned and the light oxidation is carried out after the sidewalls having a multilayer structure are formed on the side surfaces of the refractory metal film. Therefore, a scattering of the refractory metal can be effectively prevented at the time of light oxidizing the poly-silicon film.
- the fourth step can include: a step of depositing a silicon nitride film; a step of depositing a silicon oxide film on the silicon nitride film; a step of etching back the silicon oxide film; and a step of etching the silicon nitride film using the silicon oxide film as a mask. Based on this arrangement, the silicon nitride film is hardly damaged at the time of etching back the silicon oxide film. Further, at the time of etching the silicon nitride film, the part covered with the silicon oxide film is protected. Accordingly, a sidewall (silicon nitride film) with a very small amount of defects can be formed.
- FIG. 1 is a schematic cross section of one process (a formation of an element isolation trench 12 and a silicon oxide film 13 a ) of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention
- FIG. 2 is a schematic cross section of one process (a formation of an STI 14 to a formation of a p-type well layer 16 ) of the method of manufacturing a semiconductor device according to the embodiment;
- FIG. 3 is a schematic cross section of one process (a formation of a gate dielectric film 17 to a formation of a silicon oxide film 19 b ) of the method of manufacturing a semiconductor device according to the embodiment;
- FIG. 4 is a schematic cross section of one process (a formation of a tungsten film 18 c and a patterning of a tungsten nitride film 18 b ) of the method of manufacturing a semiconductor device according to the embodiment;
- FIG. 5 is a schematic cross section of one process (a formation of a silicon nitride film 20 a and a silicon oxide film 20 b ) of the method of manufacturing a semiconductor device according to the embodiment;
- FIG. 6 is a schematic cross section of one process (an etching back of the silicon oxide film 20 b ) of the method of manufacturing a semiconductor device according to the embodiment;
- FIG. 7 is a schematic cross section of one process (an etching of the silicon nitride film 20 a ) of the method of manufacturing a semiconductor device according to the embodiment;
- FIG. 8 is a schematic cross section of one process (an etching of a poly-silicon film 18 a ) of the method of manufacturing a semiconductor device according to the embodiment;
- FIG. 9 is a schematic cross section of one process (a formation of a light oxide film 18 x ) of the method of manufacturing a semiconductor device according to the embodiment.
- FIG. 10 is a schematic cross section of one process (a formation of a diffused area 21 a ) of the method of manufacturing a semiconductor device according to the embodiment;
- FIG. 11 is a schematic cross section of one process (a formation of a silicon nitride film 22 (a side spacer)) of the method of manufacturing a semiconductor device according to the embodiment;
- FIG. 12 is a schematic cross section of one process (a formation of a silicon oxide film 23 ) of the method of manufacturing a semiconductor device according to the embodiment;
- FIG. 13 is a schematic cross section of one process (a formation of contact holes 24 ) of the method of manufacturing a semiconductor device according to the embodiment;
- FIG. 14 is a schematic cross section of one process (a formation of a diffused area 21 b ) of the method of manufacturing a semiconductor device according to the embodiment;
- FIG. 15 is a schematic cross section of one process (a formation of first plugs 25 ) of the method of manufacturing a semiconductor device according to the embodiment;
- FIG. 16 is a schematic cross section of one process (a formation of a silicon oxide film 26 ) of the method of manufacturing a semiconductor device according to the embodiment;
- FIG. 17 is a schematic cross section of one process (a formation of a through-hole 27 ) of the method of manufacturing a semiconductor device according to the embodiment;
- FIG. 18 is a schematic cross section of one process (a formation of a bit line 28 ) of the method of manufacturing a semiconductor device according to the embodiment;
- FIG. 19 is a schematic cross section of one process (a formation of a silicon oxide film 29 to a formation of second plugs 31 ) of the method of manufacturing a semiconductor device according to the embodiment;
- FIG. 20 is a schematic cross section of one process (a formation of a silicon nitride film 32 to a formation of capacitor trenches 34 ) of the method of manufacturing a semiconductor device according to the embodiment.
- FIG. 21 is a schematic cross section of one process (a formation of a capacitor C) of the method of manufacturing a semiconductor device according to the embodiment.
- FIG. 1 to FIG. 21 is schematic cross sections of processes of a method of manufacturing a semiconductor device according to the exemplary embodiment of the present invention.
- the manufacturing method according to the present invention is applied to a DRAM.
- a semiconductor substrate 11 made of p-type mono-crystalline silicon having a specific resistance of about 1 to 10 ⁇ /cm is etched, thereby forming an element isolation trench 12 having a depth of about 350 nm.
- the semiconductor substrate 11 is thermally oxidized at about 1,000° C., thereby forming a silicon oxide film 13 a as thin as about 10 nm on an inner wall of the element isolation trench 12 .
- This silicon oxide film 13 a is formed to repair a damage generated on the inner wall of the element isolation trench 12 due to the etching, and to alleviate a stress generated on the interface between the semiconductor substrate 11 and an oxide silicon film 13 b embedded in the element isolation trench 12 at the next process.
- the silicon oxide film 13 b having a film thickness of about 450 to 500 nm is then deposited on the entire surface of the semiconductor substrate 11 including the element isolation trench 12 , by a chemical vapor deposition (CVD) method. Thereafter, the silicon oxide film 13 b is ground by a chemical mechanical polishing (CMP) method, and the surface of the silicon oxide film 13 b is flattened, thereby forming a shallow trench isolation (STI) 14 and a protection film 15 for forming a well layer having a film thickness of about 15 nm. Then, an impurity such as boron (B) is ion implanted into the semiconductor substrate 11 via the protection film 15 , thereby forming a p-type well layer 16 inside the semiconductor substrate 11 .
- CMP chemical mechanical polishing
- the unnecessary protection film 15 is removed, and the surface of the semiconductor substrate 11 (the p-type well layer 16 ) is then wet-cleaned using a hydrofluoric acid cleaning solution. Then, a gate dielectric film 17 having a film thickness of about 6 to 7 nm is formed on the surface of the semiconductor substrate 11 by thermal oxidation at around 800° C.
- a low-resistance poly-silicon film (hereinafter, simply referred to as a poly-silicon film) 18 a having a film thickness of about 70 to 100 nm doped with phosphor (P) is deposited on the surface of the gate dielectric film 17 , by the CVD method.
- a tungsten nitride (WNx) film 18 b having a film thickness of about 5 to 15 nm and a tungsten (W) film 18 c having a film thickness of about 80 to 100 nm are sequentially deposited on the surface of the poly-silicon film 18 a, by a sputtering method. Further, a silicon nitride film 19 a and a silicon oxide film 19 b having a film thickness of about 100 to 200 nm respectively are sequentially deposited on the surface of the tungsten film 18 c, by the CVD method.
- the tungsten film 18 c is a metal film for reducing a sheet resistance of the gate electrode.
- the tungsten nitride film 18 b functions as a barrier layer between the tungsten film 18 c and the poly-silicon film 18 a.
- the tungsten film 18 c reacts with the poly-silicon film 18 a to form silicide, and increases the resistance. Therefore, in order to prevent this increase in the resistance, the tungsten nitride film 18 b is provided.
- the silicon oxide film 19 b has high etching selectivity to the poly-silicon film 18 a, the tungsten nitride film 18 b, and the tungsten film 18 c. Therefore, the silicon oxide film 19 b is used as a mask to etch these films.
- the silicon nitride film 19 a is used as a barrier layer between the tungsten film 18 c and the silicon oxide film 19 a. In other words, when the silicon oxide film 19 a is directly formed on the tungsten film 18 c, the tungsten film 18 c is abnormally oxidized, and has a high resistance. At the same time, the surface of the tungsten film 18 c becomes very poor. Therefore, in order to prevent these problems, the silicon nitride film 19 a is provided.
- a resist pattern (not shown) is then formed in a predetermined area where the gate electrode is to be formed, and the silicon oxide film 19 b and the silicon nitride film 19 a are etched by a magnetron reactive ion etching (RIE) method using this resist pattern as a mask, thereby forming a gate cap 19 consisting of the silicon oxide film 19 b and the silicon nitride film 19 a.
- the tungsten film 18 c and the tungsten nitride film 18 b are etched by a plasma etching method of an electron cyclotron resonance (ECR) system, using the gate cap 19 as a mask.
- ECR electron cyclotron resonance
- the poly-silicon film 18 a is over-etched.
- the poly-silicon film 18 a needs to be left to some extent on the gate dielectric film 17 .
- the poly-silicon film 18 a is over-etched in order to completely cover the tungsten film 18 c and the tungsten nitride film 18 b with a sidewall to be described later.
- the poly-silicon film 18 a is left on the semiconductor substrate 11 (the gate dielectric film 17 ) for the following reason. If the gate dielectric film 17 is exposed before forming the sidewall, tungsten and its oxide (for example, WO3) are adhered to the gate dielectric film 17 , because the tungsten film 18 c and the tungsten nitride film 18 b are also exposed by the etching. On the other hand, if the poly-silicon film 17 remains, this film becomes a protection film, and can prevent a metal contamination of the gate dielectric film.
- a silicon nitride film (Si3N4) 20 a is then deposited to have a film thickness of about 10 to 20 nm on the entire surface of the gate electrode-processed semiconductor substrate 11 , by a low pressure chemical vapor deposition (LPCVD) method.
- LPCVD low pressure chemical vapor deposition
- SiO2 silicon oxide film
- a silicon oxide film (SiO2) 20 b is deposited to have a film thickness of about 10 to 20 nm on the surface of the silicon nitride film, by the LPCVD method. Accordingly, side surfaces of the tungsten film 18 c are covered with the silicon nitride film 20 a and the silicon oxide film 20 b.
- the silicon nitride film 20 a is used as an internal dielectric film of the gate electrode because the silicon nitride film 20 a does not react with the tungsten film 18 c even when the silicon nitride film 20 a is brought into contact with the tungsten film 18 c.
- the silicon oxide film 20 b is used as an external dielectric film because the silicon oxide film 20 b has high etching selectivity to the silicon nitride film. Therefore, an dielectric film made of other material can be used as long as the material satisfies these conditions.
- a silicon oxynitride film SiNO3 can be used in place of the silicon oxide film 20 b.
- the silicon oxide film 20 b is then etched back. Accordingly, all the silicon oxide films 20 b formed on the surfaces substantially parallel with the surface of the semiconductor substrate 11 are removed, and only the silicon oxide film 20 b formed on the surfaces substantially perpendicular to the surface of the semiconductor substrate 11 remains. In this case, the silicon oxide film 20 b at the sidewall parts may get damaged, thereby causing a defect. However, since the silicon oxide film 20 b can secure high etching selectivity to the silicon nitride film 20 a, the silicon nitride film 20 a is not damaged when the silicon oxide film 20 b is etched.
- the silicon nitride film 20 a is then etched using the remaining silicon oxide film 20 b as a mask. Accordingly, all the silicon nitride film 20 a is removed except the part covered with the silicon oxide film 20 b. Since the remaining silicon nitride film 20 a is covered with the silicon oxide film 20 b, the silicon nitride film 20 a is not directly exposed to the etching atmosphere, and is not damaged accordingly. In other words, the remaining silicon nitride film 20 a becomes a state having substantially no defect. Further, since the poly-silicon film 18 a remains, the gate dielectric film 17 is not damaged at etching the silicon nitride film 20 a. Consequently, a sidewall 20 having a multilayer structure consisting of the silicon nitride film 20 a and the silicon oxide film 20 b is formed on the side surfaces of the gate electrode.
- the poly-silicon film 18 a is then etched using the gate cap 19 and the sidewall 20 as a mask. Accordingly, the poly-silicon film 18 a in the area between the gate electrodes is completely removed, and the gate dielectric film 17 is exposed in this area. The side surfaces of the poly-silicon film 18 a constituting the gate electrode are also exposed.
- the semiconductor substrate 11 is then thermally oxidized at about 800 to 900° C. in the wet hydrogen atmosphere, thereby forming a thin silicon oxide film (a light oxide film) 18 x on the side surfaces of the poly-silicon film 18 a and improving the film quality of the gate dielectric film 17 at the gate edge. Accordingly, the light oxide film 18 x is formed on the side surface of the poly-silicon film 18 a stripped by the etching, and the gate dielectric film 17 damaged by the etching is repaired.
- a thin silicon oxide film a light oxide film
- Tungsten and its oxide are not scattered at the time of forming the light oxide film 18 x, because the sidewall 20 has a double film of the silicon nitride film 20 a and the silicon oxide film 20 b. Therefore, the influence of contamination due to the scattering can be securely prevented.
- the silicon nitride film 20 a on the sidewall is unavoidably damaged at the etching back time. Tungsten leaks out from the defect part, and is scattered to the gate dielectric film 17 .
- the sidewall 20 since the sidewall 20 has a double structure, the silicon nitride film 20 a on the sidewall is not exposed to the etching atmosphere at the time of etching the silicon nitride film 20 a. Consequently, the silicon nitride film 20 a on the sidewall is not damaged. Accordingly, a scattering of tungsten and its oxide can be prevented securely, and metal contamination of the gate dielectric film 16 can be prevented completely. The processing of the gate electrode 18 is thus completed.
- an n-type impurity (phosphor) is then ion implanted into the semiconductor substrate 11 at both sides of the gate electrodes, thereby forming n-type shallow diffused areas 21 a on the gate electrodes in self-alignment near the surface of the semiconductor substrate 11 .
- a silicon nitride film is then deposited to have a film thickness of about 40 nm on the entire surface of the semiconductor substrate 11 by the CVD method.
- the silicon nitride film is etched back to form a silicon nitride film 22 on only the side surfaces of the gate electrodes.
- This silicon nitride film 22 is called a side spacer.
- the side spacer together with the sidewall 20 , functions to secure electric dielectric between the gate electrode and a contact hole, described later. (The side spacer is also used as an ion injection guide at the time of forming a deep diffused area, described later.)
- a thick silicon oxide film 23 is then deposited on the entire surface of the semiconductor substrate 11 formed with the above films, by the CVD method, and the silicon oxide film 23 is ground and its surface is flattened by the CMP method.
- the silicon oxide film 23 is dry etched using a photo-resist (not shown) as a mask, thereby forming contact holes 24 on the upper part of the n-type shallow diffused areas 21 a.
- the remaining silicon oxide film 23 forms a so-called interlayer dielectric film.
- the silicon oxide film 23 is etched in the condition that the silicon oxide film 23 has large etching selectivity to the silicon nitride film.
- an n-type impurity such as phosphor (P) and arsenic (As) is then ion implanted into the n-type shallow diffused area 21 a through the contact holes 24 , thereby forming deep diffused areas 21 b for electrolytic relaxation. Accordingly, an n-type diffused area (a source and drain area) 21 including the shallow diffused area 21 a and the deep diffused area 21 b is formed on the gate electrodes in self-alignment.
- a transistor part of the memory cell of the DRAM is completed in the above process. Thereafter, a bit line and a capacitor of the DRAM are formed using a general method.
- first plugs 25 are embedded into the contact holes 24 as shown in FIG. 15 .
- a silicon oxide film 26 is deposited to have a film thickness of about 100 nm on the surface of the silicon oxide film (the interlayer dielectric film) 23 by the CVD method. Then, as shown in FIG. 17 , this silicon oxide film 26 is dry etched, thereby forming a through-hole 27 on the upper part of the first plug 25 at the center among three first plugs 25 shown in FIG. 17 .
- a bit line 28 is formed on the upper part of the through-hole 27 .
- a silicon oxide film 29 is deposited on the surface of the silicon oxide film 26 on which the bit line 28 is formed.
- through-holes 30 are formed on the upper parts of the two first plugs 25 at both sides among the three first plugs 25 shown in FIG. 19 .
- a silicon nitride film 32 and a silicon oxide film 33 are deposited, and these films are dry etched to form capacitor trenches 34 on the upper part of the second plugs 31 , as shown in FIG. 20 .
- lower electrodes 35 each consisting of a low-resistance poly-silicon film, are formed on the inner walls of the capacitor trenches 34 .
- an dielectric film 36 consisting of tantalum oxide film or the like and an upper electrode 37 consisting of a conductive film such as a TiN film and a W film are sequentially formed, thereby forming a capacitor C.
- a silicon oxide film 38 is deposited on the upper part of the semiconductor substrate 11 formed with the above films, by the CVD method, and a necessary wiring (not shown) is formed. Accordingly, the DRAM according to the present embodiment is substantially completed.
- the side surfaces of the tungsten film 18 c and the tungsten nitride film 18 b are covered with a double sidewall consisting of the silicon nitride film and the silicon oxide film. Therefore, in the process of forming the light oxide film 18 x, a scattering of tungsten and its oxide can be securely prevented. Accordingly, a leak current from the memory cell decreases substantially, and refresh characteristic can be improved.
- the method of manufacturing a semiconductor device according to the present invention is not limited to the DRAM, and can be also applied to all kinds of semiconductor devices having a gate electrode of a poly-metal structure.
- tungsten film 18 c is used as a refractory metal film of a poly-metal gate electrode, other refractory metal film such as a titanium (Ti) film can be also used.
- an alloy film (a tungsten silicide (WSix) film) of tungsten and silicon can be also provided between the poly-silicon film 13 a and the tungsten nitride film in order to improve close adhesiveness.
- the sidewall includes a double film of a silicon nitride film and a silicon oxide film in the above embodiment, the sidewall can also include three films of a silicon nitride film, a silicon oxide film, and a silicon nitride film. In other words, the sidewall according to the present invention can include two or more films.
- junction leakage attributable to the refractory metal can be further reduced. Consequently, when the present invention is applied to a memory cell transistor of a DRAM, a junction leakage current in the diffused area connected to a lower electrode of a memory capacitor can be reduced, and a leakage of electric charge stored in the memory cell capacitor can be reduced. Therefore, the refresh characteristic can be substantially increased.
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Abstract
A gate dielectric film, a poly-silicon film, a film of a refractory metal such as tungsten, and a gate cap dielectric film are sequentially laminated on a semiconductor substrate. The gate cap dielectric film and the refractory metal film are selectively removed by etching. Thereafter, a double protection film including a silicon nitride film and a silicon oxide film is formed on side surfaces of the gate cap dielectric film, the refractory metal film, and the poly-silicon film. The poly-silicon film is etched using the double protection film as a mask. Thereafter, the semiconductor substrate is light oxidized to form a silicon oxide film on side surfaces of the poly-silicon film. Accordingly, a junction leakage of a MOSFET having a gate electrode of a poly-metal structure, particularly, a memory cell transistor of a DRAM, can be further reduced.
Description
- The present invention relates to a semiconductor device and a method of manufacturing the same. The invention particularly relates to a metal-oxide semiconductor field-effect transistor (MOSFET) having a gate electrode of a poly-metal structure consisting of high-melting point metal and polycrystalline silicon (poly-silicon), and a method of manufacturing the MOSFET.
- Recently, in a MOSFET that is used for a memory cell such as a dynamic random access memory (DRAM), a so-called poly-metal structure gate electrode (poly-metal gate) having a refractory metal film such as tungsten stacked on a poly-silicon film is used in order to reduce resistance of a gate electrode (see Japanese Patent Application Laid-Open Nos. 2000-156497 and 2002-141500).
- On the other hand, at the time of patterning the gate electrode, a gate dielectric film positioned at a lower part of the gate electrode is also slightly etched. Therefore, a breakdown voltage of the gate dielectric film decreases and a leak current increases in this state. In order to prevent this problem, conventionally, after the gate electrode is patterned, an oxide film is formed on a side surface of the gate electrode. In other words, a so-called light oxidation is carried out.
- However, when the gate electrode has a poly-metal structure, a refractory metal scatters to a silicon substrate during the light oxidation, which substantially increases a junction leakage.
- As methods for solving this problem, a pamphlet of International Publication No. 98/37583 and Japanese Patent Application Laid-Open Nos. H10-189974 and 2003-68878 disclose techniques of preventing a scattering of a refractory metal film by executing a light oxidation after covering side surfaces of the refractory metal film that constitutes a poly-metal gate with a silicon nitride film.
- However, according to researches carried out by the inventors of the invention, it is made clear that it is difficult to reduce a junction leakage to a predetermined level or lower even when a light oxidation is carried out after covering the side surfaces of a refractory metal film with a silicon nitride film. Since this junction leakage increases power consumption, it is desirable to reduce the junction leakage as much as possible. Particularly, in a semiconductor device that stores an extremely small amount of electric charge such as a DRAM, a slight amount of junction leakage directly leads to a reduction in refresh characteristic. Therefore, it is particularly important to reduce the junction leakage.
- It is therefore an object of the present invention to provide a semiconductor device that can reduce a junction leakage of a MOSFET having a gate electrode of a poly-metal structure, particularly, a memory cell transistor of a DRAM.
- The inventors have carried out detailed researches into the phenomenon in which the junction leakage does not decrease to a predetermined level or lower even when a light oxidation is carried out after covering the side surfaces of a refractory metal film with a silicon nitride film. It is found through the research that the silicon nitride film that covers the side surfaces of the refractory metal film has many defects. These defects are considered to be attributable to damages caused, by etching, to a part where the silicon nitride film remains to cover the side surfaces of the refractory metal film, at the time of etching back the silicon nitride film.
- The present invention has been achieved based on the above technical knowledge. According to the present invention, there is provided a semiconductor device including: a semiconductor substrate; a gate dielectric film formed on the semiconductor substrate; a poly-metal gate electrode having at least a poly-silicon film and a refractory metal film formed on the gate dielectric film; a gate cap that covers an upper surface of the poly-metal gate electrode; and a sidewall that covers side surfaces of the poly-metal gate electrode. The sidewall has a multilayer structure including at least a first dielectric film and a second dielectric film made of a material different from that of the first dielectric film. The first dielectric film has a vertical part that is in contact with the side surfaces of the poly-metal gate electrode, and a horizontal part that extends substantially parallel with a front surface of the semiconductor substrate from the gate dielectric film side end at the vertical part.
- According to the present invention, the sidewall that covers the side surfaces of the poly-metal gate electrode has a multilayer structure. Therefore, serious defects do not occur in the sidewall. Consequently, it is possible to effectively prevent a scattering of the refractory metal contained in the poly-metal gate electrode. Accordingly, junction leakage attributable to the refractory metal can be reduced substantially.
- In order to reinforce the sidewall, there is also considered a method of increasing a film thickness of the sidewall in a single-layer structure, instead of in a multilayer structure as in the present invention. However, according to this method, the amount of etch back increases corresponding to the increased film thickness, and the damage on the sidewall increases. On the other hand, based on the structure of the sidewall according to the present invention, at the time of etching back the external dielectric film (the second dielectric film, for example), little damage is caused on the internal dielectric film (the first dielectric film, for example). At the time of etching the internal dielectric film (the first dielectric film), a part covered with the external dielectric film (the second dielectric film) is protected. Consequently, a sidewall (the first dielectric film) with a very small amount of defects can be finally obtained.
- According to the present invention, there is provided a method of manufacturing a semiconductor device, the method including: a first step of forming a gate dielectric film on a semiconductor substrate; a second step of forming at least a poly-silicon film and a refractory metal film on the gate dielectric film; a third step of patterning at least the refractory metal film; a fourth step of forming a sidewall having a multilayer structure on side surfaces of the patterned refractory metal film; a fifth step of patterning the poly-silicon film; and a sixth step of oxidizing the side surfaces of the patterned poly-silicon film.
- According to the present invention, the poly-silicon film is patterned and the light oxidation is carried out after the sidewalls having a multilayer structure are formed on the side surfaces of the refractory metal film. Therefore, a scattering of the refractory metal can be effectively prevented at the time of light oxidizing the poly-silicon film.
- The fourth step can include: a step of depositing a silicon nitride film; a step of depositing a silicon oxide film on the silicon nitride film; a step of etching back the silicon oxide film; and a step of etching the silicon nitride film using the silicon oxide film as a mask. Based on this arrangement, the silicon nitride film is hardly damaged at the time of etching back the silicon oxide film. Further, at the time of etching the silicon nitride film, the part covered with the silicon oxide film is protected. Accordingly, a sidewall (silicon nitride film) with a very small amount of defects can be formed.
- It is therefore an object of the present invention to provide a multilayer substrate and a method of manufacturing the same, which can offer a high degree of design freedom and arbitrary selection of optimal pattern shapes and variations required in various electronic elements.
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FIG. 1 is a schematic cross section of one process (a formation of anelement isolation trench 12 and asilicon oxide film 13 a) of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention; -
FIG. 2 is a schematic cross section of one process (a formation of anSTI 14 to a formation of a p-type well layer 16) of the method of manufacturing a semiconductor device according to the embodiment; -
FIG. 3 is a schematic cross section of one process (a formation of a gatedielectric film 17 to a formation of asilicon oxide film 19 b) of the method of manufacturing a semiconductor device according to the embodiment; -
FIG. 4 is a schematic cross section of one process (a formation of atungsten film 18 c and a patterning of atungsten nitride film 18 b) of the method of manufacturing a semiconductor device according to the embodiment; -
FIG. 5 is a schematic cross section of one process (a formation of asilicon nitride film 20 a and asilicon oxide film 20 b) of the method of manufacturing a semiconductor device according to the embodiment; -
FIG. 6 is a schematic cross section of one process (an etching back of thesilicon oxide film 20 b) of the method of manufacturing a semiconductor device according to the embodiment; -
FIG. 7 is a schematic cross section of one process (an etching of thesilicon nitride film 20 a) of the method of manufacturing a semiconductor device according to the embodiment; -
FIG. 8 is a schematic cross section of one process (an etching of a poly-silicon film 18 a) of the method of manufacturing a semiconductor device according to the embodiment; -
FIG. 9 is a schematic cross section of one process (a formation of alight oxide film 18 x) of the method of manufacturing a semiconductor device according to the embodiment; -
FIG. 10 is a schematic cross section of one process (a formation of adiffused area 21 a) of the method of manufacturing a semiconductor device according to the embodiment; -
FIG. 11 is a schematic cross section of one process (a formation of a silicon nitride film 22 (a side spacer)) of the method of manufacturing a semiconductor device according to the embodiment; -
FIG. 12 is a schematic cross section of one process (a formation of a silicon oxide film 23) of the method of manufacturing a semiconductor device according to the embodiment; -
FIG. 13 is a schematic cross section of one process (a formation of contact holes 24) of the method of manufacturing a semiconductor device according to the embodiment; -
FIG. 14 is a schematic cross section of one process (a formation of adiffused area 21 b) of the method of manufacturing a semiconductor device according to the embodiment; -
FIG. 15 is a schematic cross section of one process (a formation of first plugs 25) of the method of manufacturing a semiconductor device according to the embodiment; -
FIG. 16 is a schematic cross section of one process (a formation of a silicon oxide film 26) of the method of manufacturing a semiconductor device according to the embodiment; -
FIG. 17 is a schematic cross section of one process (a formation of a through-hole 27) of the method of manufacturing a semiconductor device according to the embodiment; -
FIG. 18 is a schematic cross section of one process (a formation of a bit line 28) of the method of manufacturing a semiconductor device according to the embodiment; -
FIG. 19 is a schematic cross section of one process (a formation of asilicon oxide film 29 to a formation of second plugs 31) of the method of manufacturing a semiconductor device according to the embodiment; -
FIG. 20 is a schematic cross section of one process (a formation of asilicon nitride film 32 to a formation of capacitor trenches 34) of the method of manufacturing a semiconductor device according to the embodiment; and -
FIG. 21 is a schematic cross section of one process (a formation of a capacitor C) of the method of manufacturing a semiconductor device according to the embodiment. - Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
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FIG. 1 toFIG. 21 is schematic cross sections of processes of a method of manufacturing a semiconductor device according to the exemplary embodiment of the present invention. In the present embodiment, the manufacturing method according to the present invention is applied to a DRAM. - First, as shown in
FIG. 1 , asemiconductor substrate 11 made of p-type mono-crystalline silicon having a specific resistance of about 1 to 10 Ω/cm is etched, thereby forming anelement isolation trench 12 having a depth of about 350 nm. Thesemiconductor substrate 11 is thermally oxidized at about 1,000° C., thereby forming asilicon oxide film 13 a as thin as about 10 nm on an inner wall of theelement isolation trench 12. Thissilicon oxide film 13 a is formed to repair a damage generated on the inner wall of theelement isolation trench 12 due to the etching, and to alleviate a stress generated on the interface between thesemiconductor substrate 11 and anoxide silicon film 13 b embedded in theelement isolation trench 12 at the next process. - As shown in
FIG. 2 , thesilicon oxide film 13 b having a film thickness of about 450 to 500 nm is then deposited on the entire surface of thesemiconductor substrate 11 including theelement isolation trench 12, by a chemical vapor deposition (CVD) method. Thereafter, thesilicon oxide film 13 b is ground by a chemical mechanical polishing (CMP) method, and the surface of thesilicon oxide film 13 b is flattened, thereby forming a shallow trench isolation (STI) 14 and aprotection film 15 for forming a well layer having a film thickness of about 15 nm. Then, an impurity such as boron (B) is ion implanted into thesemiconductor substrate 11 via theprotection film 15, thereby forming a p-type well layer 16 inside thesemiconductor substrate 11. - As shown in
FIG. 3 , theunnecessary protection film 15 is removed, and the surface of the semiconductor substrate 11 (the p-type well layer 16) is then wet-cleaned using a hydrofluoric acid cleaning solution. Then, agate dielectric film 17 having a film thickness of about 6 to 7 nm is formed on the surface of thesemiconductor substrate 11 by thermal oxidation at around 800° C. A low-resistance poly-silicon film (hereinafter, simply referred to as a poly-silicon film) 18 a having a film thickness of about 70 to 100 nm doped with phosphor (P) is deposited on the surface of thegate dielectric film 17, by the CVD method. A tungsten nitride (WNx)film 18 b having a film thickness of about 5 to 15 nm and a tungsten (W)film 18 c having a film thickness of about 80 to 100 nm are sequentially deposited on the surface of the poly-silicon film 18 a, by a sputtering method. Further, asilicon nitride film 19 a and asilicon oxide film 19 b having a film thickness of about 100 to 200 nm respectively are sequentially deposited on the surface of thetungsten film 18 c, by the CVD method. - The
tungsten film 18 c is a metal film for reducing a sheet resistance of the gate electrode. Thetungsten nitride film 18 b functions as a barrier layer between thetungsten film 18 c and the poly-silicon film 18 a. In other words, when thetungsten film 18 c is directly formed on the poly-silicon film 18 a, thetungsten film 18 c reacts with the poly-silicon film 18 a to form silicide, and increases the resistance. Therefore, in order to prevent this increase in the resistance, thetungsten nitride film 18 b is provided. - The
silicon oxide film 19 b has high etching selectivity to the poly-silicon film 18 a, thetungsten nitride film 18 b, and thetungsten film 18 c. Therefore, thesilicon oxide film 19 b is used as a mask to etch these films. Thesilicon nitride film 19 a is used as a barrier layer between thetungsten film 18 c and thesilicon oxide film 19 a. In other words, when thesilicon oxide film 19 a is directly formed on thetungsten film 18 c, thetungsten film 18 c is abnormally oxidized, and has a high resistance. At the same time, the surface of thetungsten film 18 c becomes very poor. Therefore, in order to prevent these problems, thesilicon nitride film 19 a is provided. - As shown in
FIG. 4 , a resist pattern (not shown) is then formed in a predetermined area where the gate electrode is to be formed, and thesilicon oxide film 19 b and thesilicon nitride film 19 a are etched by a magnetron reactive ion etching (RIE) method using this resist pattern as a mask, thereby forming a gate cap 19 consisting of thesilicon oxide film 19 b and thesilicon nitride film 19 a. After the resist pattern is removed, thetungsten film 18 c and thetungsten nitride film 18 b are etched by a plasma etching method of an electron cyclotron resonance (ECR) system, using the gate cap 19 as a mask. In this case, preferably, the poly-silicon film 18 a is over-etched. For this purpose, the poly-silicon film 18 a needs to be left to some extent on thegate dielectric film 17. - The poly-
silicon film 18 a is over-etched in order to completely cover thetungsten film 18 c and thetungsten nitride film 18 b with a sidewall to be described later. The poly-silicon film 18 a is left on the semiconductor substrate 11 (the gate dielectric film 17) for the following reason. If thegate dielectric film 17 is exposed before forming the sidewall, tungsten and its oxide (for example, WO3) are adhered to thegate dielectric film 17, because thetungsten film 18 c and thetungsten nitride film 18 b are also exposed by the etching. On the other hand, if the poly-silicon film 17 remains, this film becomes a protection film, and can prevent a metal contamination of the gate dielectric film. - As shown in
FIG. 5 , a silicon nitride film (Si3N4) 20 a is then deposited to have a film thickness of about 10 to 20 nm on the entire surface of the gate electrode-processedsemiconductor substrate 11, by a low pressure chemical vapor deposition (LPCVD) method. Then, a silicon oxide film (SiO2) 20 b is deposited to have a film thickness of about 10 to 20 nm on the surface of the silicon nitride film, by the LPCVD method. Accordingly, side surfaces of thetungsten film 18 c are covered with thesilicon nitride film 20 a and thesilicon oxide film 20 b. - The
silicon nitride film 20 a is used as an internal dielectric film of the gate electrode because thesilicon nitride film 20 a does not react with thetungsten film 18 c even when thesilicon nitride film 20 a is brought into contact with thetungsten film 18 c. Thesilicon oxide film 20 b is used as an external dielectric film because thesilicon oxide film 20 b has high etching selectivity to the silicon nitride film. Therefore, an dielectric film made of other material can be used as long as the material satisfies these conditions. For example, for the external dielectric film, a silicon oxynitride film (SiNO3) can be used in place of thesilicon oxide film 20 b. - As shown in
FIG. 6 , thesilicon oxide film 20 b is then etched back. Accordingly, all thesilicon oxide films 20 b formed on the surfaces substantially parallel with the surface of thesemiconductor substrate 11 are removed, and only thesilicon oxide film 20 b formed on the surfaces substantially perpendicular to the surface of thesemiconductor substrate 11 remains. In this case, thesilicon oxide film 20 b at the sidewall parts may get damaged, thereby causing a defect. However, since thesilicon oxide film 20 b can secure high etching selectivity to thesilicon nitride film 20 a, thesilicon nitride film 20 a is not damaged when thesilicon oxide film 20 b is etched. - As shown in
FIG. 7 , thesilicon nitride film 20 a is then etched using the remainingsilicon oxide film 20 b as a mask. Accordingly, all thesilicon nitride film 20 a is removed except the part covered with thesilicon oxide film 20 b. Since the remainingsilicon nitride film 20 a is covered with thesilicon oxide film 20 b, thesilicon nitride film 20 a is not directly exposed to the etching atmosphere, and is not damaged accordingly. In other words, the remainingsilicon nitride film 20 a becomes a state having substantially no defect. Further, since the poly-silicon film 18 a remains, thegate dielectric film 17 is not damaged at etching thesilicon nitride film 20 a. Consequently, a sidewall 20 having a multilayer structure consisting of thesilicon nitride film 20 a and thesilicon oxide film 20 b is formed on the side surfaces of the gate electrode. - As shown in
FIG. 8 , the poly-silicon film 18 a is then etched using the gate cap 19 and the sidewall 20 as a mask. Accordingly, the poly-silicon film 18 a in the area between the gate electrodes is completely removed, and thegate dielectric film 17 is exposed in this area. The side surfaces of the poly-silicon film 18 a constituting the gate electrode are also exposed. - As shown in
FIG. 9 , thesemiconductor substrate 11 is then thermally oxidized at about 800 to 900° C. in the wet hydrogen atmosphere, thereby forming a thin silicon oxide film (a light oxide film) 18 x on the side surfaces of the poly-silicon film 18 a and improving the film quality of thegate dielectric film 17 at the gate edge. Accordingly, thelight oxide film 18 x is formed on the side surface of the poly-silicon film 18 a stripped by the etching, and thegate dielectric film 17 damaged by the etching is repaired. - Tungsten and its oxide are not scattered at the time of forming the
light oxide film 18 x, because the sidewall 20 has a double film of thesilicon nitride film 20 a and thesilicon oxide film 20 b. Therefore, the influence of contamination due to the scattering can be securely prevented. In other words, when the gate electrode is covered with only thesilicon nitride film 20 a, thesilicon nitride film 20 a on the sidewall is unavoidably damaged at the etching back time. Tungsten leaks out from the defect part, and is scattered to thegate dielectric film 17. On the other hand, according to the present embodiment, since the sidewall 20 has a double structure, thesilicon nitride film 20 a on the sidewall is not exposed to the etching atmosphere at the time of etching thesilicon nitride film 20 a. Consequently, thesilicon nitride film 20 a on the sidewall is not damaged. Accordingly, a scattering of tungsten and its oxide can be prevented securely, and metal contamination of thegate dielectric film 16 can be prevented completely. The processing of the gate electrode 18 is thus completed. - As shown in
FIG. 10 , an n-type impurity (phosphor) is then ion implanted into thesemiconductor substrate 11 at both sides of the gate electrodes, thereby forming n-type shallow diffusedareas 21 a on the gate electrodes in self-alignment near the surface of thesemiconductor substrate 11. - As shown in
FIG. 11 , a silicon nitride film is then deposited to have a film thickness of about 40 nm on the entire surface of thesemiconductor substrate 11 by the CVD method. The silicon nitride film is etched back to form asilicon nitride film 22 on only the side surfaces of the gate electrodes. Thissilicon nitride film 22 is called a side spacer. The side spacer, together with the sidewall 20, functions to secure electric dielectric between the gate electrode and a contact hole, described later. (The side spacer is also used as an ion injection guide at the time of forming a deep diffused area, described later.) - As shown in
FIG. 12 , a thicksilicon oxide film 23 is then deposited on the entire surface of thesemiconductor substrate 11 formed with the above films, by the CVD method, and thesilicon oxide film 23 is ground and its surface is flattened by the CMP method. As shown inFIG. 13 , thesilicon oxide film 23 is dry etched using a photo-resist (not shown) as a mask, thereby forming contact holes 24 on the upper part of the n-type shallow diffusedareas 21 a. The remainingsilicon oxide film 23 forms a so-called interlayer dielectric film. Thesilicon oxide film 23 is etched in the condition that thesilicon oxide film 23 has large etching selectivity to the silicon nitride film. - As shown in
FIG. 14 , an n-type impurity such as phosphor (P) and arsenic (As) is then ion implanted into the n-type shallow diffusedarea 21 a through the contact holes 24, thereby forming deep diffusedareas 21 b for electrolytic relaxation. Accordingly, an n-type diffused area (a source and drain area) 21 including the shallow diffusedarea 21 a and the deep diffusedarea 21 b is formed on the gate electrodes in self-alignment. - A transistor part of the memory cell of the DRAM is completed in the above process. Thereafter, a bit line and a capacitor of the DRAM are formed using a general method. In other words, after the exposed parts of the
gate dielectric film 17 are removed, first plugs 25 are embedded into the contact holes 24 as shown inFIG. 15 . As shown inFIG. 16 , asilicon oxide film 26 is deposited to have a film thickness of about 100 nm on the surface of the silicon oxide film (the interlayer dielectric film) 23 by the CVD method. Then, as shown inFIG. 17 , thissilicon oxide film 26 is dry etched, thereby forming a through-hole 27 on the upper part of thefirst plug 25 at the center among threefirst plugs 25 shown inFIG. 17 . - As shown in
FIG. 18 , abit line 28 is formed on the upper part of the through-hole 27. Next, as shown inFIG. 19 , asilicon oxide film 29 is deposited on the surface of thesilicon oxide film 26 on which thebit line 28 is formed. Thereafter, through-holes 30 are formed on the upper parts of the twofirst plugs 25 at both sides among the threefirst plugs 25 shown inFIG. 19 . - After second plugs 31 are formed inside the second through-
holes 30, asilicon nitride film 32 and asilicon oxide film 33 are deposited, and these films are dry etched to formcapacitor trenches 34 on the upper part of the second plugs 31, as shown inFIG. 20 . Next, as shown inFIG. 21 ,lower electrodes 35, each consisting of a low-resistance poly-silicon film, are formed on the inner walls of thecapacitor trenches 34. Thereafter, andielectric film 36 consisting of tantalum oxide film or the like and anupper electrode 37 consisting of a conductive film such as a TiN film and a W film are sequentially formed, thereby forming a capacitor C. Through the above process, a memory cell of the DRAM having the MOSFET and the capacitor connected in series is completed. - Thereafter, a
silicon oxide film 38 is deposited on the upper part of thesemiconductor substrate 11 formed with the above films, by the CVD method, and a necessary wiring (not shown) is formed. Accordingly, the DRAM according to the present embodiment is substantially completed. - As explained above, according to the present embodiment, the side surfaces of the
tungsten film 18 c and thetungsten nitride film 18 b are covered with a double sidewall consisting of the silicon nitride film and the silicon oxide film. Therefore, in the process of forming thelight oxide film 18 x, a scattering of tungsten and its oxide can be securely prevented. Accordingly, a leak current from the memory cell decreases substantially, and refresh characteristic can be improved. - The present invention is not limited by the above embodiments, and various modifications may be made within the scope of the appended claims, which will be also covered by the scope of the invention.
- While a DRAM is taken as an example in the above embodiment, the method of manufacturing a semiconductor device according to the present invention is not limited to the DRAM, and can be also applied to all kinds of semiconductor devices having a gate electrode of a poly-metal structure.
- While the
tungsten film 18 c is used as a refractory metal film of a poly-metal gate electrode, other refractory metal film such as a titanium (Ti) film can be also used. - While a tungsten nitride film is directly formed on the surface of a poly-silicon film in the above embodiment, an alloy film (a tungsten silicide (WSix) film) of tungsten and silicon can be also provided between the poly-
silicon film 13 a and the tungsten nitride film in order to improve close adhesiveness. - While the sidewall includes a double film of a silicon nitride film and a silicon oxide film in the above embodiment, the sidewall can also include three films of a silicon nitride film, a silicon oxide film, and a silicon nitride film. In other words, the sidewall according to the present invention can include two or more films.
- As explained above, according to the present invention, since a scattering of a refractory metal contained in the poly-metal gate electrode can be prevented more effectively, junction leakage attributable to the refractory metal can be further reduced. Consequently, when the present invention is applied to a memory cell transistor of a DRAM, a junction leakage current in the diffused area connected to a lower electrode of a memory capacitor can be reduced, and a leakage of electric charge stored in the memory cell capacitor can be reduced. Therefore, the refresh characteristic can be substantially increased.
Claims (20)
1. A semiconductor device, comprising:
a semiconductor substrate;
a gate dielectric film formed on the semiconductor substrate;
a poly-metal gate electrode having at least a poly-silicon film and a refractory metal film formed on the gate dielectric film;
a gate cap that covers an upper surface of the poly-metal gate electrode; and
a sidewall that covers side surfaces of the poly-metal gate electrode,
wherein the sidewall has a multilayer structure including at least a first dielectric film and a second dielectric film made of a material different from that of the first dielectric film, and the first dielectric film has a vertical part that is in contact with the side surfaces of the poly-metal gate electrode and a horizontal part that extends substantially parallel with a front surface of the semiconductor substrate from the gate dielectric film side end at the vertical part.
2. The semiconductor device as claimed in claim 1 , wherein the second dielectric film is in contact with both the vertical and the horizontal part of the first dielectric film.
3. The semiconductor device as claimed in claim 1 , wherein the poly-silicon film locates at the side of the gate dielectric film and the refractory metal film locates at the side of the gate cap.
4. The semiconductor device as claimed in claim 2 , wherein the poly-silicon film locates at the side of the gate dielectric film and the refractory metal film locates at the side of the gate cap.
5. The semiconductor device as claimed in claim 3 further comprise a light oxide film formed between the horizontal part of the first dielectric film and the gate dielectric film.
6. The semiconductor device as claimed in claim 4 further comprise a light oxide film formed between the horizontal part of the first dielectric film and the gate dielectric film.
7. The semiconductor device as claimed in claim 3 , wherein the cross sectional form of the poly-silicon film has a projection by removing the corner of the poly-silicon film located at the side of the refractory metal film.
8. The semiconductor device as claimed in claim 4 , wherein the cross sectional form of the poly-silicon film has a projection by removing the corner of the poly-silicon film located at the side of the refractory metal film.
9. The semiconductor device as claimed in claim 5 , wherein the cross sectional form of the poly-silicon film has a projection by removing the corner of the poly-silicon film located at the side of the refractory metal film.
10. The semiconductor device as claimed in claim 6 , wherein the cross sectional form of the poly-silicon film has a projection by removing the corner of the poly-silicon film located at the side of the refractory metal film.
11. The semiconductor device as claimed in claim 1 , wherein the first dielectric film consists of a silicon nitride film, the second dielectric film consists of a silicon oxide film, and the refractory metal film consists of a tungsten film.
12. The semiconductor device as claimed in claim 2 , wherein the first dielectric film consists of a silicon nitride film, the second dielectric film consists of a silicon oxide film, and the refractory metal film consists of a tungsten film.
13. The semiconductor device as claimed in claim 4 , wherein the first dielectric film consists of a silicon nitride film, the second dielectric film consists of a silicon oxide film, and the refractory metal film consists of a tungsten film.
14. The semiconductor device as claimed in claim 6 , wherein the first dielectric film consists of a silicon nitride film, the second dielectric film consists of a silicon oxide film, and the refractory metal film consists of a tungsten film.
15. The semiconductor device as claimed in claim 10 , wherein the first dielectric film consists of a silicon nitride film, the second dielectric film consists of a silicon oxide film, and the refractory metal film consists of a tungsten film.
16. The semiconductor device as claimed in claim 15 , the poly-metal gate electrode is the gate electrode of a memory cell transistor of a DRAM.
17. A method of manufacturing a semiconductor device, comprising:
a first step of forming a gate dielectric film on a semiconductor substrate;
a second step of forming at least a poly-silicon film and a refractory metal film on the gate dielectric film;
a third step of patterning at least the refractory metal film;
a fourth step of forming a sidewall having a multilayer structure on side surfaces of the patterned refractory metal film;
a fifth step of patterning the poly-silicon film; and
a sixth step of oxidizing the side surfaces of the patterned poly-silicon film.
18. The method of manufacturing the semiconductor device as claimed in claim 17 , wherein the fourth step include:
a step of depositing a silicon nitride film;
a step of depositing a silicon oxide film on the silicon nitride film;
a step of etching back the silicon oxide film; and
a step of etching the silicon nitride film using the silicon oxide film as a mask.
19. The method of manufacturing the semiconductor device as claimed in claim 17 , wherein the fifth step consists of the step of patterning the poly-silicon film using the sidewall as a musk.
20. The method of manufacturing the semiconductor device as claimed in claim 18 , wherein the fifth step consists of the step of patterning the poly-silicon film using the sidewall as a musk.
Priority Applications (1)
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US12/246,908 US7846826B2 (en) | 2004-10-15 | 2008-10-07 | Method of manufacturing a semiconductor device with multilayer sidewall |
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JP2004301612A JP4143589B2 (en) | 2004-10-15 | 2004-10-15 | Manufacturing method of semiconductor device |
JP2004-301612 | 2004-10-15 |
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US20060084255A1 true US20060084255A1 (en) | 2006-04-20 |
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US11/246,337 Abandoned US20060084255A1 (en) | 2004-10-15 | 2005-10-11 | Semiconductor device and method of manufacturing the same |
US12/246,908 Active 2026-02-16 US7846826B2 (en) | 2004-10-15 | 2008-10-07 | Method of manufacturing a semiconductor device with multilayer sidewall |
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US20090004802A1 (en) * | 2007-06-29 | 2009-01-01 | Moon Sig Joo | Method of fabricating non-volatile memory device having charge trapping layer |
US20090233406A1 (en) * | 2008-03-11 | 2009-09-17 | Hynix Semiconductor Inc. | Method for fabricating semiconductor memory device |
US8766255B2 (en) | 2011-03-16 | 2014-07-01 | Semiconductor Energy Laboratory Co., Ltd. | Oxide semiconductor device including gate trench and isolation trench |
US8772849B2 (en) | 2011-03-10 | 2014-07-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor memory device |
US8779432B2 (en) | 2011-01-26 | 2014-07-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
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US20140264536A1 (en) * | 2013-03-12 | 2014-09-18 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor storage device and method of manufacturing the same |
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US9691772B2 (en) | 2011-03-03 | 2017-06-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor memory device including memory cell which includes transistor and capacitor |
US10103265B1 (en) * | 2017-08-08 | 2018-10-16 | United Microeletronics Corp. | Complementary metal oxide semiconductor device and method of forming the same |
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JP2011216526A (en) * | 2010-03-31 | 2011-10-27 | Renesas Electronics Corp | Method of manufacturing semiconductor device, and the semiconductor device |
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Also Published As
Publication number | Publication date |
---|---|
US20090042380A1 (en) | 2009-02-12 |
US7846826B2 (en) | 2010-12-07 |
JP4143589B2 (en) | 2008-09-03 |
JP2006114755A (en) | 2006-04-27 |
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