US20040071199A1 - Virtual finger method and apparatus for processing digital communication signals - Google Patents

Virtual finger method and apparatus for processing digital communication signals Download PDF

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US20040071199A1
US20040071199A1 US10/613,825 US61382503A US2004071199A1 US 20040071199 A1 US20040071199 A1 US 20040071199A1 US 61382503 A US61382503 A US 61382503A US 2004071199 A1 US2004071199 A1 US 2004071199A1
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digital samples
buffer
demodulator
path
frequency
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Robert Boesel
Theodore Myers
Tien Nguyen
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Apple Inc
NXP USA Inc
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Commasic LLC
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Publication of US20040071199A1 publication Critical patent/US20040071199A1/en
Assigned to FREESCALE SEMICONDUCTOR, INC. reassignment FREESCALE SEMICONDUCTOR, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: COMMASIC LLC
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7097—Interference-related aspects
    • H04B1/711—Interference-related aspects the interference being multi-path interference
    • H04B1/7115—Constructive combining of multi-path signals, i.e. RAKE receivers
    • H04B1/712—Weighting of fingers for combining, e.g. amplitude control or phase rotation using an inner loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7097—Interference-related aspects
    • H04B1/711—Interference-related aspects the interference being multi-path interference
    • H04B1/7115—Constructive combining of multi-path signals, i.e. RAKE receivers
    • H04B1/7117—Selection, re-selection, allocation or re-allocation of paths to fingers, e.g. timing offset control of allocated fingers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
    • H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
    • H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
    • H04B2201/70701—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation featuring pilot assisted reception
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
    • H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
    • H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
    • H04B2201/70707—Efficiency-related aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
    • H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
    • H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
    • H04B2201/70707—Efficiency-related aspects
    • H04B2201/7071—Efficiency-related aspects with dynamic control of receiver resources

Definitions

  • the present invention is related to communication systems capable of communicating signals. More particularly, the present invention relates to a method and apparatus for demodulating spread spectrum signals in a multi-path environment.
  • conventional digital communication systems include a baseband subsystem in which received signals are demodulated and transmitted signals are modulated.
  • Demodulators in baseband subsystems have been implemented using an application specific integrated circuit (ASIC) or a digital signal processor (DSP) or combination thereof.
  • ASIC application specific integrated circuit
  • DSP digital signal processor
  • known demodulator implementations suffer from significant drawbacks.
  • FIG. 1 illustrates a conventional implementation of a spread-spectrum demodulator 10 .
  • the demodulator 10 includes a combiner 12 that combines symbols received from Fingers 1 , 2 , through Finger N (hereinafter referred collectively as fingers 14 ). Fingers 14 are instantiations of hardware logic for each multi-path processing entity, or “path.”
  • the combiner 12 de-skews or aligns in time the symbols from the fingers 14 and adds the symbols together to form an estimate of the transmitted symbol value. Once steady-state is reached, an output of the combiner 12 occurs synchronously with the symbol reception at the antenna.
  • Demodulator 10 has several disadvantages. For example, several disadvantages in using the demodulator 10 result from the synchronous processing based on clock signal from a master timer 16 . Another disadvantage is that the demodulator 10 uses multiple, static instantiations of the fingers 14 . The number of fingers 14 is selected based on the worst-case channel condition possible, representing the largest possible number of gates needed. To support more and more multi-path signals and to be compatible with advanced wireless techniques such as MIMO (multiple input multiple output antennas), current conventional architectures have been instantiating more and more fingers. More fingers require more power.
  • MIMO multiple input multiple output antennas
  • Another disadvantage of the demodulator 10 is a slow assignment or de-assignment of fingers 14 , thereby wasting power. Turning on and off fingers 14 via assignment and de-assignment is a relatively slow process. As a result, there is a significant lag between a path dying and a finger shutting off. This results in higher power consumption with no corresponding gain in performance.
  • An exemplary embodiment relates to a method for demodulation of a composite signal containing a plurality of multi-path components.
  • the method includes buffering digital samples of a signal into a first memory element, randomly accessing the digital samples from the first memory element to correlate a particular multi-path component from the signal, and iteratively accumulating the correlated particular multi-path component into a second memory element.
  • the apparatus includes buffers, a despreading element, a weighting element, and an accumulator.
  • the buffers are configured to be switchable between a write state with digital samples and a read state by a correlating element.
  • the despreading element operates via random access of buffers that are currently in read state to accumulate energy for a particular multi-path component.
  • the weighting element weights the despread energy for a particular multi-path component using a channel estimate of the particular multi-path component.
  • the accumulator iteratively accumulates the despread energy for each particular multi-path component into a buffer.
  • the demodulator includes a despreader, a channel estimator, and an accumulator.
  • the despreader obtains digital samples from a first memory buffer by randomly accessing the first memory buffer such that the despreader is adaptable to arbitrary sample rates and symbol times.
  • the channel estimator obtains digital sample information from the despreader and provides a channel estimate of a particular multi-path component.
  • the accumulator accumulates the digital samples from the despreader into a second memory buffer based on the channel estimate from the channel estimator.
  • FIG. 1 is a diagrammatic representation of a conventional spread spectrum demodulator
  • FIG. 2 is a diagrammatic representation of a multi-path processing system in accordance with an exemplary embodiment
  • FIG. 3 is a diagrammatic representation comparing the operation of a conventional demodulator with the demodulator of the system of FIG. 2;
  • FIG. 4 is a diagrammatic representation of a minimal buffer operation in accordance with an exemplary embodiment
  • FIG. 5 is a diagrammatic representation of another exemplary buffer operation
  • FIG. 6 is a diagrammatic representation of an Accumulated Maximal Ratio Combining (A-MRC) processing operation in accordance with an exemplary embodiment
  • FIG. 7 is a diagrammatic representation of an Accumulated Maximal Ratio Combining (A-MRC) algorithm processing units in accordance with an exemplary embodiment
  • FIG. 8 is a diagrammatic representation of the Accumulated Maximal Ratio Combining (A-MRC) despreader of FIG. 7;
  • FIG. 9 is a diagrammatic representation of the Accumulated Maximal Ratio Combining (A-MRC) algorithm of FIG. 6 in greater detail;
  • FIG. 10 is a diagrammatic representation of the Accumulated Maximal Ratio Combining (A-MRC) algorithm processing units of FIG. 7 in greater detail;
  • FIG. 11 is a diagrammatic representation of a conventional finger for Multiple Inputs (MI);
  • FIG. 12 is a diagrammatic representation of a conventional Multiple Outputs (MO) Receiver
  • FIG. 13 is a diagrammatic representation of a processor for Accumulated Maximal Ratio Combining (A-MRC) with MIMO in accordance with an exemplary embodiment
  • FIG. 14 is a diagrammatic representation of a first phase of an exemplary windowed search process
  • FIG. 15 is a diagrammatic representation of a second phase of an exemplary windowed search process
  • FIG. 16 is a diagrammatic representation of a windowed searcher implementation in accordance with an exemplary embodiment
  • FIG. 17 is a diagrammatic representation comparing a frequency search feature of an exemplary embodiment to conventional processing
  • FIG. 18 is a diagrammatic representation of a convergent searcher operation in accordance with an exemplary embodiment
  • FIG. 19 is a diagrammatic representation of a soft combiner operation included in the convergent searcher operation of FIG. 18;
  • FIG. 20 is a diagrammatic representation of a convergent searcher implementation in accordance with an exemplary embodiment.
  • FIG. 21 is a state diagram depicting operations in the convergent searcher implementation of FIG. 18.
  • FIG. 2 illustrates a multi-path communication processing system including a processor 20 that receives signals in the form of sub-chip samples from sample buffers 22 .
  • Sample buffers 22 receive timing input from a master timer 24 and chip samples (modulated signals in a spread spectrum system) from a receiver 26 .
  • the receiver 26 can be a radio frequency (RF) or an intermediate frequency (IF) type receiver.
  • the chip samples provided to sample buffers 22 can be decimated or interpolated.
  • a control 28 provides feedback to the receiver 26 .
  • Sample buffers 22 can store an amount of data referred to as a “Symbol Group.”
  • sample buffers 22 make it possible for the processor 20 to not be synchronously clocked by the sample rate because the processor 20 can obtain data from sample buffers 22 as needed. In this way, the processor 20 operates as more like a processor than an application specific integrated circuit (ASIC), working at the fastest clock rate that the silicon technology will support.
  • ASIC application specific integrated circuit
  • FIG. 3 illustrates operation of the processor 20 compared to operation of a conventional synchronous implementation.
  • the processor 20 does the required amount of processing at the fastest clock rate available in a serial fashion. This speed enables the processor 20 to finish its processing before the time needed for the next buffer to fill and require servicing (i.e., a Symbol Group Duration).
  • the processor 20 can be shut down (i.e., the clock is gated off) until the completion of the Symbol Group Duration.
  • the given amount of processing may vary from Symbol Group to Symbol Group.
  • the processor 20 is configured to provide dynamic path processing.
  • This dynamic path processing can be referred to as a “virtual finger” feature because the multi-path communication paths, or fingers, are not actual hardwired circuits but rather paths defined using various algorithms.
  • the clock is disabled. This can be seen in FIG. 3 in the shaded “Shut Down” region.
  • there is no idle power loss from the processor 20 due to capacitive loading on the clock tree resulting from clock ticks on the circuitry without activity.
  • conventional systems using an ASIC for demodulation operations only a small fraction of the clock ticks produce useful output from the ASIC.
  • Another example of the dynamic processing ability of the processor 20 is the dynamic setting of bit-widths. Dynamically processing the bits is particularly beneficial since less bits are usually needed to produce a decodable output than the instantaneous worst case. By processing less bits on average, less power is consumed.
  • Bits can be treated like paths, in that they can be separately processed, because of the linearity in most demodulation processing (e.g., de-spreading, accumulation, MRC) such that many bits can be divided into sub-units of bits. If the processor 20 were designed in this fashion, it would be composed of small bit-width circuitry. In the presence of a fade, where more bits are necessary on a given path, the same path would be processed several times, each on a different sub-unit of bits (i.e. first the LSB sub-unit and last the MSB sub-unit). Each time a sub-unit is processed, the de-spreaded output is appropriately shifted and accumulated into a symbol buffer. Such processing is simply another kind of Accumulated Maximal Ratio Combining (A-MRC) algorithm with the paths being replaced by sub-units of bits in the algorithm.
  • A-MRC Accumulated Maximal Ratio Combining
  • processor 20 can dynamically set bit-widths is by using a programmable ASIC. If only a few bits are needed, the data is shifted to the right such that the number of toggling bits in the demodulator are reduced.
  • the processor 20 can offload some of the low processing intensive operations that are typically forced into ASIC.
  • the buffering nature of the processor 20 operation can be exploited to eliminate the stringent real-time DSP deadlines that typically force these operations into ASIC. Because samples are buffered, stringent real-time processor deadlines are no longer in force.
  • the processor can offload many relatively non-computationally intensive tasks including Multipath Finger Assignment, Equalization/Interpolation/MRC Tap Weight Calculation, NCO Stride Selection, and Time Tracking. Offloading this functionality into the processor 20 represents a saving in silicon area, yielding lower cost in addition to reduced development risks. Incorporating a processor into the demodulation algorithm reduces power consumption, too.
  • FIG. 4 illustrates the operation of an exemplary buffering scheme.
  • a “buffer” is a memory element including two sets of data/address ports—one for read and one for write. The buffer does not have to support simultaneous read/write access. Any given cycle is either read or write or both.
  • the selection criteria of this exemplary buffer scheme is to use a small amount of RAM for the chip memory, yet have very simple operation of the processor. At any given time, the processor is processing on two of the buffers that are logically functioning as one.
  • a state 40 in FIG. 4 shows that during iteration N, Buffer 1 and Buffer 2 are serving as a single logical data source. With this scheme, all symbols whose earliest path begins in Buffer 1 are processed to completion (all multi-paths are combined), which entails using the chips in Buffer 2 for the later paths of these symbols. Those symbols whose earliest paths occur in Buffer 2 are not processed until iteration N+1 in a state 42 as shown in FIG. 4.
  • Buffer 3 is receiving the samples occurring during the processing of the logical combination of Buffer 1 and Buffer 2 .
  • the processor processes those symbols whose earliest path are in Buffer 2 while using the contents of Buffer 3 as the necessary later arriving paths which also must be present to complete the symbol processing.
  • these operations allow for complete symbol processing during any iteration which eliminates the requirement of many state variables to keep track of the partial processing between iterations, and more complicated control logic to allow “fast-forwarding” through states to reach partial symbols.
  • the larger sample buffer size is used when other requirements drive the necessity of a larger buffer size.
  • the driving requirement of sample buffer size is the multi-path delay spread such that all data for symbol processing is accessible to the processor simultaneously.
  • burst-pilot wireless technologies such as 1 xEV-DO
  • the burst spacing is the more stringent requirement for determining buffer size.
  • the processor must have simultaneous access to all the data stored between pilot bursts, in addition to the later pilot burst for linear interpolation of the channel estimate to be performed which is vital for demodulation performance for the automatic frequency control (AFC) drift that is ever-present.
  • AFC automatic frequency control
  • FIG. 5 illustrates an exemplary buffering scheme for wireless technologies that use burst-pilot.
  • Buffers 1 , 2 , and 3 serve as a single logical data source to the processor 20 (FIG. 2).
  • Buffers 4 and 5 serve as a single logical memory element that captures the synchronously arriving samples from the ADC. All symbols whose earliest arriving multi-path components are contained in Buffers 1 and 2 are completely processed during iteration N. This operation uses the samples in Buffer 3 in order to process the later arriving multi-path components. The processing of the symbols whose earliest arriving multi-path components are contained in Buffer 3 is deferred until iteration N+1. Therefore, during iteration N+1, Buffers 3 , 4 , and 5 serve as the single logical entity for processing.
  • FIG. 6 illustrates operations in an Accumulated Maximal Ratio Combining (A-MRC) procedure of the processor 20 described with reference to FIG. 2. As can be seen here, operations are performed serially. In an operation 60 , the number of paths, N, is set to zero. In an operation 62 , a pilot channel for path N is processed, yielding a channel estimate. Operation 62 continues until all known multi-paths are estimated. Advantageously, the number of paths, N, can vary over time.
  • A-MRC Accumulated Maximal Ratio Combining
  • channel estimates for a set of M relevant multi-paths are used in data de-spreading of an operation 64 .
  • multi-paths can refer to communication signals from the one base station, other base stations, one antenna, or other antennas.
  • data for path M is processed while multiplying by the channel estimate.
  • Operation 64 continues until all relevant multi-paths for all channels are demodulated.
  • the processor sleeps until the next symbol group is available.
  • FIG. 7 shows exemplary processing blocks of the processor 20 that are specific to the A-MRC algorithm.
  • the Master Timer 24 is used to determine the beginning of the Processing Interval.
  • the processor 20 begins processing of sub-chip samples.
  • An address generator 52 decimates the samples to the correct rate and phase by initializing to the buffer address corresponding to the desired sub-ship phase. To keep proper sub-chip phase alignment, the address generator 52 is advanced the number of sub-chips per chip.
  • a despreader 56 and a channel estimator 58 serially despread and accumulate the paths into a Symbol Buffer 54 .
  • FIG. 8 illustrates the despreader 56 for the A-MRC algorithm.
  • the despreader 56 operates by multiplying by the known pilot sequence, and inserting the correlation value into a channel estimator 58 .
  • the despreader 56 multiplies the on-phase sub-chip samples by the correct PN and channelization code (e.g., Walsh, OVSF, etc.) and outputs the value at symbol rate.
  • the complex symbols are then multiplied by the channel estimate from the path and accumulated into the symbol buffer 54 . In other words, the complex symbols are read, added to the current value, and written back into the symbol buffer 54 .
  • the MRC estimates are valid at the end of processing the relevant multi-paths and are ready for symbol processing (e.g., deinterleaving, depuncturing, and decoding).
  • FIG. 9 illustrates in more detail operations performed in the Accumulated Maximal Ratio Combining (A-MRC) procedure described with reference to FIG. 6.
  • A-MRC Accumulated Maximal Ratio Combining
  • a state 65 the channel estimate for path N is multiplied by the despread data of path N, the accumulator is bypassed, and the output is sent to intermediate buffers.
  • symbols from the path N are accumulated over multi-paths and base stations.
  • the current MRC accumulation of the group of symbols (which are initialized to zero for processing of the first path) from the intermediate buffer are added to the despread and channel estimated symbols from the intermediate buffer, the accumulator is bypassed, and output is sent to intermediate buffers.
  • States 63 - 66 are repeated until all N relevant multi-paths and base stations are processed at which point, the current MRC accumulation is the final accumulation and this value is output to the symbol processor.
  • this process may be repeated in the case where a receiver is demodulating several channels After that, in a state 67 , the processor 20 sleeps until the next processing interval.
  • FIG. 10 illustrates in more detail the processing blocks specific to the A-MRC algorithm described with reference to FIG. 7.
  • the processor 20 includes a state machine control 80 configured to change states as described with reference to FIG. 8.
  • the processor 20 also includes multiplexers (MUX) 82 , 83 , and 85 directing input from the sample buffers 22 , intermediate buffers 86 , and despreader sequence generator 88 .
  • a bypassable accumulator 84 directs symbols to a decoder and intermediate buffers 86 .
  • the bypassable accumulator 84 can output channel estimates, current and incomplete accumulated symbols, despread data symbols, despread pilot symbols, or channel estimated data symbols for a particular path.
  • the sample buffer 22 inputs pilot symbols to MUX 82 and the despread sequence generator 88 inputs despread data to MUX 83 . These inputs are multiplied and sent to bypassable accumulator 84 via MUX 85 .
  • the bypassable accumulator 84 outputs accumulated symbols to intermediate buffers 86 . The control of where results are output is dependent upon the state diagram described with reference to FIG. 9.
  • the A-MRC algorithm serially accumulates to the correct MRC value.
  • f i,n is the extracted symbol estimate of the ith symbol for the nth multi-path
  • c(.) is the contents of the chip sample buffer
  • J is the spreading factor
  • s(i) is the beginning of the correlation for the i th symbol
  • T n is the multi-path delay
  • d is the decimation rate
  • p j is the pseudo-nose sequence multiplied by the orthogonal channelization code.
  • ⁇ i,n is the channel estimate of multipath n during the i th symbol.
  • criteria can include not to process paths that have an instantaneous power in excess of T 1 dB below the strongest instantaneous multi-path component. Paths that are substantially below a strongest path contribute little to the SNR of the resultant (especially in an interference dominated scenario).
  • Another criteria can be to rank paths in order of strongest to weakest instantaneous powers and not process paths once a threshold of T 2 has been reached. This represents a condition where de-codability has been reached and there is no need for processing any more multi-path components.
  • MIMO Multiple Inputs
  • RX Multiple receive
  • SIMO Single Input Multiple Outputs
  • the processor 20 can process all links.
  • the dynamic processing capabilities of the processor 20 allows a substantial power savings in that only the links (or multi-path within each link) that are sufficiently strong are processed.
  • FIG. 11 illustrates a conventional finger supporting multiple input antenna (MI).
  • MI multiple input antenna
  • FIG. 12 illustrates a conventional receiver supporting multiple output antenna (MO).
  • MO multiple output antenna
  • FIG. 13 illustrates a receiver 75 supporting full-fledged MIMO.
  • the receiver 75 treats paths emanating from different BS antennas as well as paths coming from different RX antennas almost the same as another multi-path.
  • MI the only addition to the receiver 75 compared to the processing system of FIG. 7 is the necessity of a transformer 77 to handle such operations as STTD in WCDMA.
  • MO the only addition to the receiver 75 compared to the processing system of FIG. 7 is that the sample buffer 22 is doubled to support data coming in from both RF chains. As a result, there is substantial cost savings.
  • processor 20 is configured for operation with a “burst-pilot” signal where the information sent from the communication base-station used to estimate the cellular channel is time-division multiplexed so that it is present and not present in the forward-link signal at different times.
  • processor 20 is configured for operation with a “continuous-pilot” where the information sent from the communication base-station used to estimate the cellular channel is always present in the forward link signal transmitted by the base-station.
  • Finding the multi-path components in a timely manner so that they may contribute to the demodulation of the signal is one of the design challenges in a CDMA receiver implementation.
  • Searching refers to the process of finding multi-path components in a rapidly changing environment.
  • the processor 20 allows for enhanced searcher operation.
  • the convergent searcher function described below with reference to FIGS. 18 - 19 is a distinct algorithm that allows for fast acquisition of multi-path components and enhances the performance of the CDMA receiver in a rapidly changing multi-path environment.
  • the processor 20 includes a scheme that does not require separate buffering for the windowed searching operation.
  • conventional implementations generally consist of instantiations of “fingers” operating synchronously upon the samples in parallel.
  • the processor 20 serially processes each multi-path one at a time where each iteration through the data is termed a “virtual finger.”
  • channel estimates performed by conventional ASIC hardware are performed by dedicated hardware in addition to the demodulation specific circuitry.
  • the processor 20 does not have this limitation. The same circuitry can be used both for demodulation and channel estimation.
  • the way that the samples are buffered helps in the operation of the processor 20 .
  • a three buffer scheme is used which gives access to the entire delay spread of the sub-chip samples to be demodulated by the processor 20 .
  • This minimal buffering scheme avoids the time delay of a two buffer scheme where the two physical buffers switch roles once the buffer receiving chips is full. Further, the buffering scheme has an entire multi-path spread worth of digital samples available during each processing iteration.
  • a single dual-port memory is used to implement the buffering scheme.
  • FIG. 14 illustrates a first phase of an exemplary windowed search process.
  • the process takes a set of digital complex samples 92 , 94 , 96 , 98 , and 100 and determines the correlation of these samples with various hypothesis.
  • all combinations of 4 adjacent chips are computed for a number of adjacent sets of 4 chips.
  • FIG. 15 illustrates a second phase of the exemplary windowed search process.
  • the computed combinations from phase one are used to find correlations over multiples of 4 chips.
  • the correlations can be coherent and non-coherent. In the example shown, 128 correlations are found.
  • a PN sequence 104 is received by shift registers 106 .
  • Shift registers 106 direct processed chips from the PN sequence 104 to a number of RAM devices (e.g., RAM 1 - 32 ).
  • RAM device 108 includes, for example, partial sums of chips 1 - 4 .
  • RAM device 110 includes partial sums of chips 5 - 8 .
  • RAM device 112 includes partial sums of chips 125 - 128 . Correlations from the RAM devices are combined using a combining apparatus 124 .
  • phase one can be amortized across a large number of hypothesis such that it becomes negligible in the analysis.
  • the number of computations becomes close to a factor of 4 reduction relative to conventional algorithms, given a sufficiently large set of PN hypothesis to be correlated against.
  • the processor 20 described with reference to FIG. 2 can perform a windowed search.
  • An additional search functionality referred to as a convergent searcher is described below with reference to FIGS. 20 - 21 .
  • the processor 20 receives samples from sample buffers 82 and 84 .
  • the sample buffer 82 provides even phase samples and the sample buffer 84 provides odd phase samples.
  • a 2 ⁇ 2 permute block 86 supplies a demodulator 88 with on-time samples such that the signal energy is maximized.
  • the other set of sample buffers is for use with a searcher 89 .
  • the searcher 89 gets either the odd phase or the even phase samples, whichever is not used by the demodulator 88 , whenever the searcher 89 and the demodulator 88 contend for the same memory block.
  • the searcher 89 After acquisition, the searcher 89 operates on samples that are either 1 ⁇ 8 th chip early or 1 ⁇ 8 th chip late, but this slight degradation in energy impacts operation of the searcher 89 only minimally.
  • the windowed searcher function performs a sufficient number of correlations, then shuts down until a new block of data is available. As such, hardware idle cycles are avoided.
  • a buffer 87 is used to store digital samples obtained at a different frequency than an original frequency. Using an additional buffer has the advantage of storing samples for possible use later. Alternatively, the digital samples obtained at a different frequency can be placed in sample buffers 82 and 84 for a receive iteration and a processing iteration.
  • FIG. 17 illustrates a frequency search feature of an exemplary embodiment compared with frequency search accomplished by conventional processing.
  • the processor 20 allows for baseband processing of signals while the RF is either shut-off or tuned to a different frequency.
  • One benefit of this technique is a more effective inter-frequency search.
  • FIG. 17 shows that a search for base stations at other frequencies can be performed “off-line” after an initial buffer fill.
  • One benefit is that the time-consuming process of testing various PN offsets via coherent and non-coherent combinations of correlations can be performed while tuned to the demodulation frequency. This potentially enhances system performance by either: reducing the amount of time necessary for making other frequency measurements, or allowing for less data loss from the current frequency assignment during other frequency measurements.
  • the frequency search feature utilizes the same sample buffers used with the original frequency.
  • the sample buffers receive the digital samples from the new frequency in one iteration and process them in a next iteration. After the original frequency is returned to, the sample buffers continue in use.
  • a separate buffer is used for new frequency, such as buffer 87 described with reference to FIG. 17. Use of a separate buffer has the advantage of maintaining the digital samples received at the new frequency even after returning to the original frequency.
  • FIG. 18 illustrates a convergent searcher operation.
  • a received chip, r n is multiplied by channel reliability, R, to obtain a channel measurement, S channel .
  • the convergent searcher operation converges to the correct PN state using noisy chip measurements of the pilot.
  • Channel measurements are used as a soft input and added to a soft output feedback from a soft combiner 91 .
  • This soft input is used to compute log-likelihoods.
  • the soft combiner 91 performs a mod 2 addition to a group of channel measurements, S n ⁇ 1 though S n ⁇ 15 .
  • the soft combiner 91 can be implemented by a series of soft XOR operations as described with reference to FIG. 19.
  • the soft XOR operation is implemented via a look-up-table.
  • the convergent searcher operation of FIG. 18 acquires PN synchronization without a priori knowledge of a last known PN like conventional searchers.
  • the convergent searcher operation is capable of finding dominant multi-paths in fewer operations than a windowed searcher operation.
  • Other advantages possible by the convergent searcher operation include the following. First, the operation provides for rapid acquisition of strong pilots that may be missed by a conventional windowed searcher when the path comes in rapidly. Second, the operation enables neighbor set maintenance during idle mode to be performed much more rapidly, which results in a 2 ⁇ increase in stand-by time for a mobile device. Third, the operation provides for rapid acquisition.
  • FIG. 19 illustrates a detailed implementation of the soft combiner 91 of FIG. 18.
  • the convergent searcher operation of FIG. 18 is specific to the PN I (In-Phase) sequence for and defined by the recursion:
  • I n I n ⁇ 15 +I n ⁇ 10 +I n ⁇ 8 +I n ⁇ 7 +I n ⁇ 6 +I n ⁇ 2
  • the Ec/No for quick convergence (around 0 dB) of this technique is higher than the power at which the pilot currently operates.
  • the base station dedicates slots of time at which the pilot signal is transmitted at 100% of the operating power.
  • FIG. 20 illustrates an exemplary implementation of the convergent searcher operation by the processor 20 .
  • the convergent searcher 90 receives samples including a phase rotation from a subtraction of samples from the sample buffers 22 and known paths from a FIR block 98 .
  • FIR (finite impulse response) block 98 is a pulse shaping filter.
  • Known paths 94 are re-modulated by a re-modulator 96 and provided to the FIR block 98 along with channel estimates.
  • FIG. 21 illustrates a state diagram depicting convergent searcher operations performed by the processor 20 .
  • operations 100 and 102 the current set of known paths (which is empty during acquisition) is re-modulated and subtracted out. This separation aids in finding the weaker multi-paths once the stronger ones have been detected. In addition, the instantaneous fading of strong multi-paths aids in this process.
  • phase rotation is introduced before the convergent searcher block because phase rotation of the multi-path is not known.
  • phase rotation hypothesis is iterated upon. Once the phase rotation aligns with the phase of the strongest unknown pilot, convergence is indicated. Hard decisions are made on the soft-decision states, and this state is mapped to a PN phase in an operation 106 which is sent to the windowed searcher for verification and accurate measurement.
  • CDMA code division multiple access
  • other communication protocols and techniques can be utilized.
  • system parameters and design criteria can effect the particulars of the design without departing from the scope of the invention.
  • the invention is not limited to a particular embodiment, but extends to various modifications, combinations, and permutations that nevertheless fall within the scope and spirit of the appended claims.

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