US20040015676A1 - Sharing of a logic operator having a work register - Google Patents

Sharing of a logic operator having a work register Download PDF

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Publication number
US20040015676A1
US20040015676A1 US10/619,105 US61910503A US2004015676A1 US 20040015676 A1 US20040015676 A1 US 20040015676A1 US 61910503 A US61910503 A US 61910503A US 2004015676 A1 US2004015676 A1 US 2004015676A1
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United States
Prior art keywords
operator
function
present
register
circuit
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Abandoned
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US10/619,105
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English (en)
Inventor
Pierre-Yvan Liardet
William Orlando
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STMicroelectronics SA
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STMicroelectronics SA
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Publication date
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Assigned to STMICROELECTRONICS, S.A. reassignment STMICROELECTRONICS, S.A. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LIARDET, PIERRE-YVAN, ORLANDO, WILLIAM
Publication of US20040015676A1 publication Critical patent/US20040015676A1/en
Priority to US11/585,658 priority Critical patent/US7783691B2/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers

Definitions

  • the present invention generally relates to the processing of binary words by calculation functions.
  • the present invention more specifically relates to the execution, by a state machine in wired logic of an integrated circuit, of a calculation representing a function likely to be used by several applications within this same circuit.
  • An example of application of the present invention relates to the implementation, within a same circuit, of several processings all using a same operating function.
  • it may be a public key signature processing, a data integrity control or a random generator for cryptography.
  • a so-called “Hash” discriminating function is generally used, for example, functions known as SHA, MD5, etc.
  • a first problem is linked to the existence of a work register storing the results of the different iterations. Indeed, this means in practice that the result of the functions is only obtained at the end of the multiple iterations.
  • a solution would consist of having interrupts generated by other applications wait until the iteration calculation is over. This is however incompatible with a desire of real time execution required by some applications needing the operator. For example, in the context of an integrity control requiring the discrimination operator for an authentication message calculation, it cannot be awaited until the operator is freed by another application.
  • the present invention aims at providing a solution to the problem of the sharing of a logic operator by several applications exploiting a same iterative discrimination function.
  • the present invention also aims at providing a solution which is compatible with the desired miniaturization of integrated circuits.
  • the present invention also aims at enabling sharing of the operator in wired logic without adversely affecting the need for real time processing of a priority-holding application.
  • the present invention provides a circuit for calculating a discriminating function with successive iterations and with a work register on data divided into blocks, comprising:
  • each register stores a current state of the operator and the rank of the corresponding iteration.
  • said function is a Hash function.
  • a multiplexer forming the selection element is controlled by a priority decoder associated with an integrated processor containing said calculation circuit.
  • FIG. 1 very schematically shows in the form of blocks an embodiment of the circuit for calculating a discrimination function according to the present invention.
  • FIG. 2 is a flowchart of a function exploited by the calculation circuit of FIG. 1 according to an embodiment of the present invention.
  • a feature of the present invention is to dissociate, in a calculation circuit implementing an iterative discriminating function with a work register, the actual operator from the work register. According to the present invention, it is provided to share the operator between several work registers individually dedicated to different applications.
  • FIG. 1 very schematically shows in the form of blocks an embodiment of a shared calculation circuit according to the present invention.
  • Circuit 1 essentially comprises a logic operator 2 (f(PSi-1, Bi)) executing an operation using as operands a binary block B and a state PS representing the result of the operation at a previous iteration.
  • the processed data (in the example of FIG. 1, block B) forms a portion of a data word for which an application requires use of the discriminating function.
  • the input (PS) and the output (CS) states of operator 2 correspond to the successive contents of a single work register per application.
  • work registers 3 REG 1 , . . . , REGj, . . . REGn)
  • there are applications to share circuit 1 are provided.
  • Each register 3 is equivalent to a conventional work register associated with a wired operator 2 .
  • inputs/outputs of registers 3 are connected to the multiple inputs of a multiplexer 4 having a single input/output connected to the input (signal PS)) of operator 2 and to the output (signal CS) of operator 2 .
  • Multiplexer 4 receives a selection signal (SEL) coming, for example, from a priority control (not shown) associated with the central processing unit of the processor integrating circuit 1 .
  • Initial states IS 1 , . . . ISj, . . . ISn are loaded under control of the CPU into each register 3 .
  • the final states FS 1 , FSj, . . . FSn of function f after the required iterations are read individually from each register, by the processor circuits having required the application of the Hash function to a given binary word.
  • number m of iterations depends on the number of data blocks to be processed.
  • number n of registers depends on the number of applications which require operator 2 .
  • FIG. 2 is a simplified flowchart of the function performed by operator 2 .
  • the function starts (block 10 , IS) from an initial state.
  • This state is, in the example of FIG. 1, previously loaded into one of the work registers associated with the application having requested the function.
  • this initial state is predetermined.
  • the data words to be processed by the discriminating function are also stored in adapted memorization elements (for example, registers).
  • Rank i stored in register 3 assigned to the application is used to select the appropriate data block upon resumption of the iterations for the concerned application.
  • An advantage of the present invention is that it enables sharing a same operator in wired logic for several discriminating functions executed by different applications of an integrated processor.
  • Another advantage of the present invention is that by avoiding storage of the intermediary calculation states in an external memory of the integrated circuit, the present invention preserves the security character generally required for applications of discriminating functions.
  • Another advantage of the present invention is that its implementation is particularly simple in an integrated processor.
  • the implementation of the present invention is compatible with the hardware circuits and control processes generally used in integrated processors.
  • the application processed by operator 2 is transparent for said operator, in that all operates as if it was only connected to one register.
  • operator 2 is shared by several applications among which at least one real time data integrity control. In this case, this application is considered as holding the highest priority.
  • a second possible application may be a signature or authentication code calculation having a lower priority rank.
  • the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art.
  • the practical forming of the calculation circuit according to the present invention is within the abilities of those skilled in the art based on the functional indications given hereabove.
  • the commands necessary to the multiplexer and to the different register by using conventional control means are within the abilities of those skilled in the art.
  • the selection of the block Bi assigned to the data word of the application may be performed in several manners. For example, the integrated circuit CPU manages the reading of the desired blocks according to the decided priorities.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Advance Control (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Storage Device Security (AREA)
US10/619,105 2002-07-17 2003-07-14 Sharing of a logic operator having a work register Abandoned US20040015676A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/585,658 US7783691B2 (en) 2002-07-17 2006-10-24 Sharing of a logic operator having a work register

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR02/09072 2002-07-17
FR0209072 2002-07-17

Related Child Applications (1)

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US11/585,658 Continuation US7783691B2 (en) 2002-07-17 2006-10-24 Sharing of a logic operator having a work register

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US20040015676A1 true US20040015676A1 (en) 2004-01-22

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US10/619,105 Abandoned US20040015676A1 (en) 2002-07-17 2003-07-14 Sharing of a logic operator having a work register
US11/585,658 Active 2025-11-27 US7783691B2 (en) 2002-07-17 2006-10-24 Sharing of a logic operator having a work register

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US (2) US20040015676A1 (fr)
EP (1) EP1383041A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060195828A1 (en) * 2005-02-28 2006-08-31 Kabushiki Kaisha Toshiba Instruction generator, method for generating instructions and computer program product that executes an application for an instruction generator

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10409827B2 (en) 2014-10-31 2019-09-10 21, Inc. Digital currency mining circuitry having shared processing logic
US9942046B2 (en) * 2015-05-06 2018-04-10 21, Inc. Digital currency mining circuitry with adaptable difficulty compare capabilities

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5608801A (en) * 1995-11-16 1997-03-04 Bell Communications Research, Inc. Efficient cryptographic hash functions and methods for amplifying the security of hash functions and pseudo-random functions
US20040032347A1 (en) * 2002-04-26 2004-02-19 Masato Yamazaki Soft-output decoder with computation decision unit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5475822A (en) 1993-11-15 1995-12-12 Motorola, Inc. Data processing system for resuming instruction execution after an interrupt and method therefor
US5666300A (en) * 1994-12-22 1997-09-09 Motorola, Inc. Power reduction in a data processing system using pipeline registers and method therefor
US6434584B1 (en) 1998-06-04 2002-08-13 Texas Instruments Incorporated Flexible accumulator register file for use in high performance microprocessors
DE69930893T2 (de) * 1998-06-25 2006-11-16 Texas Instruments Inc., Dallas Digitaler Signalprozessor für Daten mit grosser Bitlänge
JP2001306298A (ja) * 2000-04-27 2001-11-02 Mitsubishi Electric Corp 情報処理装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5608801A (en) * 1995-11-16 1997-03-04 Bell Communications Research, Inc. Efficient cryptographic hash functions and methods for amplifying the security of hash functions and pseudo-random functions
US20040032347A1 (en) * 2002-04-26 2004-02-19 Masato Yamazaki Soft-output decoder with computation decision unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060195828A1 (en) * 2005-02-28 2006-08-31 Kabushiki Kaisha Toshiba Instruction generator, method for generating instructions and computer program product that executes an application for an instruction generator

Also Published As

Publication number Publication date
US20070220074A1 (en) 2007-09-20
EP1383041A1 (fr) 2004-01-21
US7783691B2 (en) 2010-08-24

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Owner name: STMICROELECTRONICS, S.A., FRANCE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIARDET, PIERRE-YVAN;ORLANDO, WILLIAM;REEL/FRAME:014284/0525

Effective date: 20030619

STCB Information on status: application discontinuation

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