US20030148617A1 - Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask - Google Patents
Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask Download PDFInfo
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- US20030148617A1 US20030148617A1 US10/068,053 US6805302A US2003148617A1 US 20030148617 A1 US20030148617 A1 US 20030148617A1 US 6805302 A US6805302 A US 6805302A US 2003148617 A1 US2003148617 A1 US 2003148617A1
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 125000006850 spacer group Chemical group 0.000 title claims abstract description 31
- 239000000463 material Substances 0.000 claims abstract description 89
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 26
- 230000000873 masking effect Effects 0.000 claims abstract description 25
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 13
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 13
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 13
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 13
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000001459 lithography Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
Definitions
- the present invention relates generally to fabrication of semiconductor devices, and more specifically to methods of fabricating transistor gates used in semiconductor devices.
- U.S. Pat. No. 4,784,718 to Mitani et al. describes a method for fabricating a semiconductor device with its gate electrode and source/drain extraction electrodes being made of the same material on a GaAs substrate and with its source/drain heavily doped regions self-aligned with both gate electrode and source/drain extraction electrodes.
- U.S. Pat. No. 5,202,272 to Hsieh et al. describes a method of forming a field effect-transistor formed with a deep-submicron gate.
- U.S. Pat. No. 4,931,137 to Sibuet describes a process for fabricating conductor elements on a substrate mutually spaced by a submicron dimension.
- U.S. Pat. No. 4,648,937 to Ogura et al. describes a method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer.
- U.S. Pat. No. 6,171,937 to Lustig describes a process for fabricating an MOS transistor having a channel length of less than 100 nm.
- U.S. Pat. No. 5,336,630 to Yun et al. describes a method of making a semiconductor memory device having a storage node with a plurality of pillars capable of increasing the storage node surface and thus the cell capacitance.
- Another object of the present invention to provide an improved method of fabricating small transistor gates that relies less on lithography than conventional methods.
- a substrate having an overlying Si 3 N 4 or an SiO 2 /Si 3 N 4 stack gate dielectric layer.
- a gate material layer is formed over the gate dielectric layer.
- a hard mask layer is formed over the gate material layer.
- the hard mask layer and the gate material layer are patterned to form a hard mask/gate material layer stack.
- a planarized dielectric layer is formed surrounding the hard mask/gate material layer stack.
- the patterned hard mask layer is removed from over the patterned gate material layer to form a cavity having exposed dielectric layer side walls.
- Masking spacers are formed on the exposed dielectric layer side walls over a portion of the patterned gate material layer.
- the patterned gate material layer is etched using the masking spacers as masks to expose a portion of the gate dielectric layer.
- the planarized dielectric layer is removed.
- the masking spacers are removed to form narrow gates comprising gate material.
- FIGS. 1 to 6 schematically illustrate in cross-sectional representation a preferred embodiment of the present invention.
- FIG. 1 illustrates a cross-sectional view of a wafer 10 , preferably a semiconductor wafer, having an Si 3 N 4 or SiO 2 /Si 3 N 4 stack gate dielectric layer 12 formed thereover to a thickness of preferably from about 15 to 100 ⁇ and more preferably from about 15 to 28 ⁇ .
- Si 3 N 4 or SiO 2 /Si 3 N 4 stack gate dielectric layer 12 is preferably deposited over wafer 10 and is more preferably is comprised of an SiO 2 /Si 3 N 4 stack as will be used for illustrative purposes hereafter.
- Gate material 14 is deposited over SiO 2 /Si 3 N 4 stack gate dielectric layer 12 to a thickness of preferably from about 900 to 2000 ⁇ and more preferably from about 1200 to 1600 ⁇ .
- Gate material 14 is preferably comprised of polysilicon (poly), W on TiN stack or TaN and is more preferably comprised of poly.
- Hard mask layer 16 may then be formed over gate material 14 to a thickness of from about 900 to 2000 ⁇ and more preferably from about 1200 to 1600 ⁇ .
- Hard mask layer 16 is preferably formed of nitride, silicon nitride (Si 3 N 4 ) or silicon oxynitride (SiON) and is more preferably formed of silicon nitride.
- gate material 14 is then patterned to form patterned gate material 14 ′ having a width of preferably from about 1800 to 3200 ⁇ and more preferably from about 1800 to 2400 ⁇ .
- Gate material 14 may be patterned as shown in FIGS. 1 and 2 to form patterned gate material 14 ′, that is patterned photoresist layer 18 may be formed over hard mask layer 16 as shown in FIG. 1. As shown in FIG. 2, hard mask layer 16 may then be patterned using patterned photoresist layer 18 during an etch process to form patterned hard mask layer 16 ′. Photoresist layer 18 would then be stripped and gate material 14 patterned to form patterned gate material 14 ′ using patterned hard mask layer 16 ′ as a mask. If it is desired to minimize loss of the hard mask layer 16 ′ during etching of the gate material 14 , photoresist layer 18 is not stripped until after the patterned gate material 14 ′ is formed. The thickness of the patterned hard mask layer 16 ′ determines the thickness of the resist spacers 24 to be formed later (see below).
- dielectric layer 20 is then deposited over the structure and planarized to fill in the gaps between adjacent patterned hard mask 16 ′/patterned gate material 14 ′ stacks.
- Dielectric layer 20 is planarized using patterned hard mask layer 16 ′ as a polish stop.
- Dielectric layer 20 is preferably planarized using chemical mechanical polishing (CMP).
- Dielectric layer 20 is preferably high-density plasma (HDP) oxide, PECVD oxide, LPCVD oxide or SABPSG and is more preferably HDP oxide as that provides for better gap fill between the gates.
- HDP high-density plasma
- patterned hard mask layer 16 ′ is removed, preferably by wet stripping or dry selective etching and more preferably wet stripping to form cavity 22 .
- Cavity 22 has exposed side walls 26 .
- a thin layer of spacer material is deposited over the structure, filling cavity 22 , and is then etched, preferably by a blanket etch, to form self-aligned spacers 24 over exposed side walls 26 of cavity 22 .
- Spacers 24 are preferably comprised of photoresist.
- patterned gate material 14 ′ is etched using spacers 24 as masks to form small transistor gate electrodes 30 .
- Small gate electrodes 30 have a width of preferably from about 250 to 800 ⁇ and more preferably from about 250 to 500 ⁇ . It is noted that SiO 2 /Si 3 N 4 stack gate dielectric layer 12 between gate electrodes 30 are also partially etched.
- small, narrow transistor gate electrodes 30 are formed in accordance with the method of the present invention with less reliance upon lithography to form the small, narrow gate electrodes 30 . Instead the width of masking spacers 24 determines the width of small, narrow transistor gate electrodes 30 which are in turn formed by a blanket etch, without direct reliance upon lithography.
- planarized dielectric layer 20 is removed, preferably by an oxide dip.
- masking spacers 24 are preferably removed by a resist ashing process, leaving small, narrow gate electrodes 30 .
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Abstract
A method of forming narrow gates comprising the following steps. A substrate is provided having an overlying Si3N4 or an SiO2/Si3N4 stack gate dielectric layer. A gate material layer is formed over the gate dielectric layer. A hard mask layer is formed over the gate material layer. The hard mask layer and the gate material layer are patterned to form a hard mask/gate material layer stack. A planarized dielectric layer is formed surrounding the hard mask/gate material layer stack. The patterned hard mask layer is removed from over the patterned gate material layer to form a cavity having exposed dielectric layer side walls. Masking spacers are formed on the exposed dielectric layer side walls over a portion of the patterned gate material layer. The patterned gate material layer is etched using the masking spacers as masks to expose a portion of the gate dielectric layer. The planarized dielectric layer is removed. The masking spacers are removed to form narrow gates comprising gate material.
Description
- The present invention relates generally to fabrication of semiconductor devices, and more specifically to methods of fabricating transistor gates used in semiconductor devices.
- The current practice to form small transistor gates uses increasingly smaller wavelengths of light in the lithography step(s). The current practice places increasingly stringent requirements on lithography.
- U.S. Pat. No. 4,784,718 to Mitani et al. describes a method for fabricating a semiconductor device with its gate electrode and source/drain extraction electrodes being made of the same material on a GaAs substrate and with its source/drain heavily doped regions self-aligned with both gate electrode and source/drain extraction electrodes.
- U.S. Pat. No. 5,202,272 to Hsieh et al. describes a method of forming a field effect-transistor formed with a deep-submicron gate.
- U.S. Pat. No. 4,931,137 to Sibuet describes a process for fabricating conductor elements on a substrate mutually spaced by a submicron dimension.
- U.S. Pat. No. 4,729,966 to Koshino et al. describes a process for fabricating a Schottky FET device using metal sidewalls as gates.
- U.S. Pat. No. 4,648,937 to Ogura et al. describes a method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer.
- U.S. Pat. No. 6,171,937 to Lustig describes a process for fabricating an MOS transistor having a channel length of less than 100 nm.
- U.S. Pat. No. 5,336,630 to Yun et al. describes a method of making a semiconductor memory device having a storage node with a plurality of pillars capable of increasing the storage node surface and thus the cell capacitance.
- Accordingly, it is an object of the present invention to provide an improved method of fabricating small transistor gates.
- Another object of the present invention to provide an improved method of fabricating small transistor gates that relies less on lithography than conventional methods.
- Other objects will appear hereinafter.
- It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate is provided having an overlying Si3N4 or an SiO2/Si3N4 stack gate dielectric layer. A gate material layer is formed over the gate dielectric layer. A hard mask layer is formed over the gate material layer. The hard mask layer and the gate material layer are patterned to form a hard mask/gate material layer stack. A planarized dielectric layer is formed surrounding the hard mask/gate material layer stack. The patterned hard mask layer is removed from over the patterned gate material layer to form a cavity having exposed dielectric layer side walls. Masking spacers are formed on the exposed dielectric layer side walls over a portion of the patterned gate material layer. The patterned gate material layer is etched using the masking spacers as masks to expose a portion of the gate dielectric layer. The planarized dielectric layer is removed. The masking spacers are removed to form narrow gates comprising gate material.
- The features and advantages of the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:
- FIGS.1 to 6 schematically illustrate in cross-sectional representation a preferred embodiment of the present invention.
- Unless otherwise specified, all structures, layers, etc. may be formed or accomplished by conventional methods known in the prior art.
- Initial Structure
- FIG. 1 illustrates a cross-sectional view of a
wafer 10, preferably a semiconductor wafer, having an Si3N4 or SiO2/Si3N4 stack gatedielectric layer 12 formed thereover to a thickness of preferably from about 15 to 100 Å and more preferably from about 15 to 28 Å. Si3N4 or SiO2/Si3N4 stack gatedielectric layer 12 is preferably deposited overwafer 10 and is more preferably is comprised of an SiO2/Si3N4 stack as will be used for illustrative purposes hereafter. -
Gate material 14 is deposited over SiO2/Si3N4 stack gatedielectric layer 12 to a thickness of preferably from about 900 to 2000 Å and more preferably from about 1200 to 1600 Å.Gate material 14 is preferably comprised of polysilicon (poly), W on TiN stack or TaN and is more preferably comprised of poly. -
Hard mask layer 16 may then be formed overgate material 14 to a thickness of from about 900 to 2000 Å and more preferably from about 1200 to 1600 Å.Hard mask layer 16 is preferably formed of nitride, silicon nitride (Si3N4) or silicon oxynitride (SiON) and is more preferably formed of silicon nitride. - Patterning of
Gate Material 14 - As shown in FIG. 2,
gate material 14 is then patterned to form patternedgate material 14′ having a width of preferably from about 1800 to 3200 Å and more preferably from about 1800 to 2400 Å. -
Gate material 14 may be patterned as shown in FIGS. 1 and 2 to form patternedgate material 14′, that is patternedphotoresist layer 18 may be formed overhard mask layer 16 as shown in FIG. 1. As shown in FIG. 2,hard mask layer 16 may then be patterned using patternedphotoresist layer 18 during an etch process to form patternedhard mask layer 16′.Photoresist layer 18 would then be stripped andgate material 14 patterned to form patternedgate material 14′ using patternedhard mask layer 16′ as a mask. If it is desired to minimize loss of thehard mask layer 16′ during etching of thegate material 14,photoresist layer 18 is not stripped until after the patternedgate material 14′ is formed. The thickness of the patternedhard mask layer 16′ determines the thickness of theresist spacers 24 to be formed later (see below). - Deposition of
Dielectric Layer 20 - As shown in FIG. 2,
dielectric layer 20 is then deposited over the structure and planarized to fill in the gaps between adjacent patternedhard mask 16′/patternedgate material 14′ stacks.Dielectric layer 20 is planarized using patternedhard mask layer 16′ as a polish stop.Dielectric layer 20 is preferably planarized using chemical mechanical polishing (CMP). -
Dielectric layer 20 is preferably high-density plasma (HDP) oxide, PECVD oxide, LPCVD oxide or SABPSG and is more preferably HDP oxide as that provides for better gap fill between the gates.. - Formation of
Spacers 24 - As shown in FIG. 3, patterned
hard mask layer 16′ is removed, preferably by wet stripping or dry selective etching and more preferably wet stripping to formcavity 22.Cavity 22 has exposedside walls 26. - A thin layer of spacer material is deposited over the structure,
filling cavity 22, and is then etched, preferably by a blanket etch, to form self-alignedspacers 24 over exposedside walls 26 ofcavity 22.Spacers 24 are preferably comprised of photoresist. - Etching of
Patterned Gate Material 14′ - As shown in FIG. 4, patterned
gate material 14′ is etched usingspacers 24 as masks to form smalltransistor gate electrodes 30.Small gate electrodes 30 have a width of preferably from about 250 to 800 Å and more preferably from about 250 to 500 Å. It is noted that SiO2/Si3N4 stackgate dielectric layer 12 betweengate electrodes 30 are also partially etched. - It is noted that small, narrow
transistor gate electrodes 30 are formed in accordance with the method of the present invention with less reliance upon lithography to form the small,narrow gate electrodes 30. Instead the width of maskingspacers 24 determines the width of small, narrowtransistor gate electrodes 30 which are in turn formed by a blanket etch, without direct reliance upon lithography. - Removal of
Dielectric Layer 20 - As shown in FIG. 5, planarized
dielectric layer 20 is removed, preferably by an oxide dip. - Removal of
Masking Spacers 24 - As shown in FIG. 6, masking
spacers 24 are preferably removed by a resist ashing process, leaving small,narrow gate electrodes 30. - Any unwanted connections between adjacent small,
narrow gate electrodes 30 are etched off after appropriate masking. - Advantages of the Invention
- The advantages of the present invention include:
- 1); non-reliance on very advanced lithography performance; and
- 2) deposition and etch-dependent poly critical dimensions are more controllable than lithography.
- While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.
Claims (30)
1. A method of forming narrow gates, comprising the steps of:
providing a substrate having an overlying gate dielectric layer;
forming a gate material layer over the gate dielectric layer;
forming a hard mask layer over the gate material layer;
patterning the hard mask layer and the gate material layer to form a hard mask/gate material layer stack;
forming a planarized dielectric layer surrounding the hard mask/gate material layer stack;
removing the patterned hard mask layer from over the patterned gate material layer to form a cavity having exposed dielectric layer side walls;
forming masking spacers on the exposed dielectric layer side walls over a portion of the patterned gate material layer;
etching the patterned gate material layer using the masking spacers as masks to expose a portion of the gate dielectric layer;
removing the planarized dielectric layer; and
removing masking spacers to form narrow gates comprising gate material.
2. The method of claim 1 , wherein the gate dielectric layer is from about 15 to 100 Å thick; the gate material layer is from about 900 to 2000 Å thick; and the hard mask layer is from about 900 to 2000 Å thick.
3. The method of claim 1 , wherein the gate dielectric layer is from about 15 to 28 Å thick; the gate material layer is from about 1200 to 1600 Å thick; and the hard mask layer is from about 1200 to 1600 Å thick.
4. The method of claim 1 , wherein the gate dielectric layer is comprised of a material selected from the group consisting of Si3N4 and SiO2/Si3N4 stack; the gate material layer is comprised of a material selected from the group consisting of poly, W on TiN stack and TaN; and the hard mask layer is comprised of a material selected from the group consisting of nitride, silicon nitride and silicon oxynitride.
5. The method of claim 1 , wherein the gate dielectric layer is comprised of an SiO2/Si3N4 stack; the gate material layer is comprised of poly; and the hard mask layer is comprised of silicon nitride.
6. The method of claim 1 , wherein the hard mask/gate material layer stack is from about 1800 to 3200 Å wide.
7. The method of claim 1 , wherein the hard mask/gate material layer stack is from about 1800 to 2400 Å wide.
8. The method of claim 1 , wherein the masking spacers have a base width of from about 250 to 800 Å and the narrow gates are from about 250 to 800 Å wide.
9. The method of claim 1 , wherein the masking spacers have a base width of from about 250 to 500 Å and the narrow gates are from about 250 to 500 Å wide.
10. The method of claim 1 wherein the planarized dielectric layer is removed by an oxide dip.
11. The method of claim 1 , including the step of etching away any connections between narrow gates.
12. A method of forming narrow gates, comprising the steps of:
providing a substrate having an overlying gate dielectric layer; the gate dielectric layer is comprised of a material selected from the group consisting of Si3N4 and SiO2/Si3N4 stack;
forming a gate material layer over the gate dielectric layer; the gate material layer is comprised of a material selected from the group consisting of poly, W on TiN stack and TaN;
forming a hard mask layer over the gate material layer; the hard mask layer is comprised of a material selected from the group consisting of nitride, silicon nitride and silicon oxynitride;
patterning the hard mask layer and the gate material layer to form a hard mask/gate material layer stack;
forming a planarized dielectric layer surrounding the hard mask/gate material layer stack;
removing the patterned hard mask layer from over the patterned gate material layer to form a cavity having exposed dielectric layer side walls;
forming masking spacers on the exposed dielectric layer side walls over a portion of the patterned gate material layer;
etching the patterned gate material layer using the masking spacers as masks to expose a portion of the gate dielectric layer;
removing the planarized dielectric layer; and
removing masking spacers to form narrow gates comprising gate material.
13. The method of claim 12 , wherein the gate dielectric layer is from about 15 to 100 Å thick; the gate material layer is from about 900 to 2000 Å thick; and the hard mask layer is from about 900 to 2000 Å thick.
14. The method of claim 12 , wherein the gate dielectric layer is from about 15 to 28 Å thick; the gate material layer is from about 1200 to 1600 Å thick; and the hard mask layer is from about 1200 to 1600 Å thick.
15. The method of claim 12 , wherein the gate dielectric layer is comprised of an SiO2/Si3N4 stack; the gate material layer is comprised of poly; and the hard mask layer 16 is comprised of silicon nitride.
16. The method of claim 12 , wherein the hard mask/gate material layer stack is from about 1800 to 3200 Å wide.
17. The method of claim 12 , wherein the hard mask/gate material layer stack is from about 1800 to 2400 Å wide.
18. The method of claim 12 , wherein the masking spacers have a base width of from about 250 to 800 Å and the narrow gates are from about 250 to 800 Å wide.
19. The method of claim 12 , wherein the masking spacers have a base width of from about 250 to 500 Å and the narrow gates are from about 250 to 500 Å wide.
20. The method of claim 12 , wherein the planarized dielectric layer is removed by an oxide dip.
21. The method of claim 12 , including the step of etching away any connections between narrow gates.
22. A method of forming narrow gates, comprising the steps of:
providing a substrate having an overlying gate dielectric layer; the gate dielectric layer is comprised of a material selected from the group consisting of Si3N4 and SiO2/Si3N4 stack; the gate dielectric layer being from about 15 to 100 Å thick;
forming a gate material layer over the gate dielectric layer; the gate material layer is comprised of a material selected from the group consisting of poly, W on TiN stack and TaN; the gate material layer being from about 900 to 2000 Å thick;
forming a hard mask layer over the gate material layer; the hard mask layer is comprised of a material selected from the group consisting of nitride, silicon nitride and silicon oxynitride; the hard mask layer is from about 900 to 2000 Å thick;
patterning the hard mask layer and the gate material layer to form a hard mask/gate material layer stack;
forming a planarized dielectric layer surrounding the hard mask/gate material layer stack;
removing the patterned hard mask layer from over the patterned gate material layer to form a cavity having exposed dielectric layer side walls;
forming masking spacers on the exposed dielectric layer side walls over a portion of the patterned gate material layer;
etching the patterned gate material layer using the masking spacers as masks to expose a portion of the gate dielectric layer;
removing the planarized dielectric layer; and
removing masking spacers to form narrow gates comprising gate material.
23. The method of claim 22 , wherein the gate dielectric layer is from about 15 to 28 Å thick; the gate material layer is from about 1200 to 1600 Å thick; and the hard mask layer is from about 1200 to 1600 Å thick.
24. The method of claim 22 , wherein the gate dielectric layer is comprised of an SiO2/Si3N4 stack; the gate material layer is comprised of poly; and the hard mask layer 16 is comprised of silicon nitride.
25. The method of claim 22 , wherein the hard mask/gate material layer stack is from about 1800 to 3200 Å wide.
26. The method of claim 22 , wherein the hard mask/gate material layer stack is from about 1800 to 2400 Å wide.
27. The method of claim 22 , wherein the masking spacers have a base width of from about 250 to 800 Å and the narrow gates are from about 250 to 800 Å wide.
28. The method of claim 22 , wherein the masking spacers have a base width of from about 250 to 500 Å and the narrow gates are from about 250 to 500 Å wide.
29. The method of claim 22 , wherein the planarized dielectric layer is removed by an oxide dip.
30. The method of claim 22 , including the step of etching away any connections between narrow gates.
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US10/068,053 US6610604B1 (en) | 2002-02-05 | 2002-02-05 | Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask |
SG200207453A SG104349A1 (en) | 2002-02-05 | 2002-12-05 | Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask |
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Cited By (2)
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US20050208742A1 (en) * | 2004-03-17 | 2005-09-22 | International Business Machines Corporation | Oxidized tantalum nitride as an improved hardmask in dual-damascene processing |
CN104347360A (en) * | 2013-07-24 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Dual-pattern structure and forming method thereof |
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US7521371B2 (en) * | 2006-08-21 | 2009-04-21 | Micron Technology, Inc. | Methods of forming semiconductor constructions having lines |
US7838371B2 (en) * | 2006-11-06 | 2010-11-23 | Nxp B.V. | Method of manufacturing a FET gate |
JP5933953B2 (en) * | 2011-10-06 | 2016-06-15 | キヤノン株式会社 | Manufacturing method of semiconductor device |
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JPS6046074A (en) | 1983-08-24 | 1985-03-12 | Toshiba Corp | Semiconductor device and manufacture thereof |
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US5202272A (en) | 1991-03-25 | 1993-04-13 | International Business Machines Corporation | Field effect transistor formed with deep-submicron gate |
TW221720B (en) | 1991-11-15 | 1994-03-11 | Gold Star Co | |
DE19548058C2 (en) | 1995-12-21 | 1997-11-20 | Siemens Ag | Method of manufacturing a MOS transistor |
US6204517B1 (en) * | 1998-04-09 | 2001-03-20 | Texas Instruments-Acer Incorporated | Single electron transistor memory array |
US6355528B1 (en) * | 1999-08-11 | 2002-03-12 | Advanced Micro Devices, Inc. | Method to form narrow structure using double-damascene process |
US6184116B1 (en) * | 2000-01-11 | 2001-02-06 | Taiwan Semiconductor Manufacturing Company | Method to fabricate the MOS gate |
US6500743B1 (en) * | 2000-08-30 | 2002-12-31 | Advanced Micro Devices, Inc. | Method of copper-polysilicon T-gate formation |
US6455433B1 (en) * | 2001-03-30 | 2002-09-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming square-shouldered sidewall spacers and devices fabricated |
-
2002
- 2002-02-05 US US10/068,053 patent/US6610604B1/en not_active Expired - Lifetime
- 2002-12-05 SG SG200207453A patent/SG104349A1/en unknown
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050208742A1 (en) * | 2004-03-17 | 2005-09-22 | International Business Machines Corporation | Oxidized tantalum nitride as an improved hardmask in dual-damascene processing |
CN104347360A (en) * | 2013-07-24 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Dual-pattern structure and forming method thereof |
Also Published As
Publication number | Publication date |
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SG104349A1 (en) | 2004-06-21 |
US6610604B1 (en) | 2003-08-26 |
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