CN104347360A - Dual-pattern structure and forming method thereof - Google Patents
Dual-pattern structure and forming method thereof Download PDFInfo
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- CN104347360A CN104347360A CN201310315127.8A CN201310315127A CN104347360A CN 104347360 A CN104347360 A CN 104347360A CN 201310315127 A CN201310315127 A CN 201310315127A CN 104347360 A CN104347360 A CN 104347360A
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- 239000000463 material Substances 0.000 claims abstract description 108
- 239000010410 layer Substances 0.000 claims description 368
- 125000006850 spacer group Chemical group 0.000 claims description 39
- 230000015572 biosynthetic process Effects 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
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- 239000002356 single layer Substances 0.000 claims description 12
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 238000005137 deposition process Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000004576 sand Substances 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- -1 SiCN Inorganic materials 0.000 claims description 3
- 229910004541 SiN Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 3
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- 229910052718 tin Inorganic materials 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000019552 anatomical structure morphogenesis Effects 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
Abstract
The invention relates to a dual-pattern structure and a forming method thereof. The forming method of the dual-pattern structure includes the following steps that: a layer to be etched is provided; a stress layer is formed on the layer to be etched; a sacrificial layer with a plurality of openings is formed on the stress layer, wherein the openings expose a part of the surface of the stress layer; a side wall material layer is formed on the surfaces of the stress layer and the sacrificial layer; a dielectric layer which fully fills the openings is formed on the surface of the side wall material layer; with the sacrificial layer adopted as a stopping layer, flattening is performed on the dielectric layer, and the surface of the top of the sacrificial layer is exposed; the sacrificial layer and the dielectric layer are removed; and the stress layer is etched, so that grooves which pass through the stress layer can be formed in the stress layer. With the forming method of the dual-pattern structure adopted, the dual-pattern structure will not be deformed.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of double-pattern structure and forming method thereof.
Background technology
Along with the minimum feature of integrated circuit (IC) design and constantly reducing of spacing, when exposing theory resolution power close to exposure system of the characteristic size of lines, will there is serious distortion in the imaging of silicon chip surface, thus cause the degradation of litho pattern quality.In order to reduce the impact of optical proximity effect, industrial quarters proposes photoetching resolution enhancing technology (RET), and the double-pattern technology (DPT) wherein received much concern is considered to fill up the powerful guarantee of wide gap between immersion lithography and EUV.
Double-pattern technology forms etching sacrificial layer usually on material layer to be etched, formation side wall around etching sacrificial layer, after removing described etching sacrificial layer, with described side wall for mask, etches described material layer to be etched, can the little figure of morphogenesis characters size.
Fig. 1 to Fig. 5 is the structural representation adopting dual graphic method to form double-pattern in prior art.
Please refer to Fig. 1, form etachable material layer 20 over the semiconductor substrate 10.
Please refer to Fig. 2, form sacrificial material layer (not shown) to be etched on the surface of etachable material layer 20, etch described sacrificial material layer to be etched, form patterned sacrifice layer 30, expose the surface of partial etching material layer 20.
Please refer to Fig. 3, form spacer material layer on described patterned sacrifice layer 30 surface and etachable material layer 20 surface, and etch described spacer material layer, form side wall 40 in the sidewall surfaces of described patterned sacrifice layer 30.
Please refer to Fig. 4, remove patterned sacrifice layer 30.
Please refer to Fig. 5, with described side wall 40 for mask, etachable material layer 20 is etched, form figure 21 to be etched.
The double-pattern that prior art is formed easily deforms, and affects the accuracy of the etched features that etachable material layer described in subsequent etching is formed.
Summary of the invention
The problem that the present invention solves is to provide a kind of double-pattern structure and forming method thereof, can improve the accuracy of the etched features of formation.
For solving the problem, the invention provides a kind of formation method of double-pattern structure, comprising: providing layer to be etched; Described layer to be etched on form stressor layers; Described stressor layers is formed the sacrifice layer with some openings, and described opening exposes the surface of part stressor layers; Spacer material layer is formed in described stressor layers and sacrificial layer surface; The dielectric layer of filling full described opening is formed on described spacer material layer surface; With described sacrifice layer for stop-layer, planarization is carried out to described dielectric layer, expose the top surface of sacrifice layer; Remove described sacrifice layer and dielectric layer; With described spacer material layer for mask, etch described stressor layers, form the groove running through described stressor layers.
Optionally, described stressor layers is single layer structure or double-decker.
Optionally, the material of described stressor layers is silicon nitride, carborundum or tetraethoxysilane.
Optionally, the thickness of described stressor layers is
.
Optionally, the stressor layers of described single layer structure has compression or tensile stress.
Optionally, the stress intensity of described stressor layers is 50MPa ~ 1000MPa.
Optionally, described double-deck stressor layers comprise be positioned at described layer to be etched on tensile stress layer and be positioned at the compressive stress layer on described tensile stress layer surface.
Optionally, the material of described sacrifice layer is photoresist, antireflecting coating or silicon nitride.
Optionally, atom layer deposition process is adopted to form described spacer material layer.
Optionally, the material of described dielectric layer is photoresist, antireflection material, SiCO or SiCOH.
Optionally, described material layer to be etched is advanced low-k materials, amorphous silicon, amorphous carbon, silica, SiN, SiON, SiCN, SiC, BN, SiCO, SiCOH, BN or TiN.
Optionally, treat that sacrificial layer surface is formed after hard mask layer described, form stressor layers on described hard mask layer surface.
For solving the problem, technical scheme of the present invention additionally provides a kind of double-pattern structure adopting said method to be formed, and comprising: layer to be etched; Be positioned at layer to be etched on some discrete stressor layers; Be positioned at the discrete side wall on the surface, two ends of stressor layers.
Optionally, described stressor layers is single layer structure or double-decker.
Optionally, the material of described stressor layers is silicon nitride, carborundum or tetraethoxysilane.
Optionally, the thickness of described stressor layers is
.
Optionally, the stressor layers of described single layer structure has compression or tensile stress.
Optionally, the stress intensity of described stressor layers is 50MPa ~ 1000MPa.
Optionally, described double-deck stressor layers comprise be positioned at described layer to be etched on tensile stress layer and be positioned at the compressive stress layer on described tensile stress layer surface.
Optionally, the material of described side wall is one or more in silica, silicon nitride, silicon oxynitride, carborundum, fire sand.
Compared with prior art, technical scheme of the present invention has the following advantages:
Stressor layers is formed on layer to be etched, described stressor layers has stress, is formed in the process of spacer material layer on described stressor layers surface, and described stressor layers is for eliminating or reducing the stress that produces between spacer material layer and sacrifice layer, after sacrifice layer is removed, side wall generation deformation can be avoided.After the described spacer material layer of formation, dielectric layer is formed and planarization on described spacer material layer surface, expose sacrifice layer, remove the surface that described sacrifice layer and dielectric layer expose part stressor layers simultaneously, then stressor layers is etched, form the groove running through stressor layers, described groove makes stressor layers be divided into some undersized stressor layers, reduce the stress in stressor layers, separatedly between the side wall on adjacent undersized stressor layers surface to open, the stress influence of all the other stressor layers can not be subject to, thus the stress eliminated or reduce between stressor layers and side wall, and eliminate or reduce stressor layers and layer to be etched between stress.And, while etching forms described groove, side wall is etched, make mutually to disconnect between the side wall on some undersized stressor layers surfaces, and depression can be formed on described some undersized stressor layers surfaces, make to be separated from each other between the side wall on described undersized stressor layers surface, there is no effect of stress each other.Therefore, said method can make the stress elimination of side wall generation deformation or be reduced to minimum, thus avoids side wall generation deformation.
Further, the side wall of the double-pattern structure adopting the formation method of dual structure of the present invention to be formed can keep vertical, deformation can not occur, thus can improve the accuracy of the etched features of subsequent etching formation layer to be etched.
Accompanying drawing explanation
Fig. 1 to Fig. 6 is the structural representation of the forming process adopting double-pattern structure in prior art;
Fig. 7 to Figure 14 is the structural representation of the forming process of the double-pattern structure of embodiments of the invention.
Embodiment
As described in the background art, the double-pattern structure that prior art is formed easily deforms, and affects the accuracy of the etched features of follow-up formation.
Research finds, in prior art, after removing sacrifice layer, the actual side wall pattern formed as shown in Figure 6, by the sacrifice layer 30(between adjacent side wall 40 with reference to figure 3) remove after, adjacent side wall 40 can to the position run-off the straight at original sacrifice layer place, the double-pattern structure of formation is made to produce distortion, follow-up adopt again described side wall be mask etching hard mask layer and layer to be etched time, the figure of hard mask layer and middle formation layer to be etched can be made to produce distortion, affect the stability of the device of follow-up formation.
Prior art is when sacrifice layer 30 surface forms spacer material layer, usual employing atom layer deposition process or chemical vapor deposition method form described spacer material layer, described spacer material layer, sacrifice layer, material in the middle of material layer to be etched is not identical, formed in the process of described spacer material layer at employing atom layer deposition process or chemical vapor deposition method, described spacer material layer inside can form stress, and described spacer material layer and layer to be etched between can form stress, finally can produce certain effect of stress to sacrifice layer, extruding is produced to sacrifice layer top, make the sidewall generation inclination to a certain degree of sacrifice layer, but because sacrifice layer inside can produce a contrary stress to offset this effect, so, the side wall formed in sacrifice layer both sides substantially still keeps vertical form.But after the described sacrifice layer of removal, rightabout stress relieved, makes side wall to the position run-off the straight at original sacrifice layer place, thus the figure generation deformation made, affect the formation of subsequent etching figure.
Technical scheme of the present invention, proposes a kind of double-pattern structure and forming method thereof, effectively can be made the stress of side wall generation deformation by release double-pattern structure in forming process, make the final etched features formed more accurate.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Please refer to Fig. 7, provide layer to be etched 100, form hard mask layer 101 on described surface layer to be etched, form stressor layers 200 on described hard mask layer surface.
Described layer to be etched 100 is the follow-up material layer needing etching.Described layer to be etched 100 can be single or multiple lift stacked structure.The described material of layer to be etched 100 is dielectric layer material or metal material or nonmetallic materials.Concrete, the described material of layer to be etched 100 is advanced low-k materials, polysilicon, amorphous silicon, amorphous carbon, silica, SiN, SiON, SiCN, SiC, BN, SiCO, SiCOH, BN, TiN, W, Al or Cu etc.It should be noted that, described layer to be etched can also be other materials, the material of etch layer should not limit the scope of the invention.
Described hard mask layer 101 is follow-up as the described mask of layer to be etched 100 of etching, after described hard mask layer 101 surface forms double-pattern, described double-pattern is transferred on described hard mask layer 101, then using described hard mask layer 101 as material layer to be etched described in mask etching, because the material hardness of described hard mask layer 101 is larger, in etching process, mask pattern not easily changes, thus can improve the accuracy of etched features.In other embodiments of the invention, also directly stressor layers can be formed on described surface layer to be etched.
The material of described stressor layers 200 is silicon nitride, carborundum or tetraethoxysilane (TEOS), and the thickness of described stressor layers is
described stressor layers 200 is eliminated for follow-up formation in deposition in the process of spacer material layer or reduces the effect of stress between spacer material layer and sacrifice layer, thus after sacrifice layer is removed, makes side wall deformation not occur.
Described stressor layers 200 can be single layer structure or double-decker.In the present embodiment, adopt double-deck stressor layers 200, described stressor layers 200 comprises the first stressor layers 201 being positioned at hard mask layer 101 surface and the second stressor layers 202 being positioned at described first stressor layers 201 surface.Described first stressor layers 201 has tensile stress, and described second stressor layers 202 has compression.The stress intensity of described first stressor layers 201 and the second stressor layers 202 is 50Mpa ~ 1000Mpa.In other embodiments of the invention, described stressor layers 200 is single layer structure, and the stressor layers 200 of described individual layer can have tensile stress or compression, and the size of described tensile stress or compression is 50Mpa ~ 1000Mpa.
In the present embodiment, so the material of the first stressor layers 201 and the second stressor layers 202 is silicon nitride.Concrete, the formation method with the first stressor layers 201 of tensile stress comprises: using plasma strengthens chemical vapor deposition method, wherein, adopts NH
3and SiH
4as reacting gas, inert gas is as carrier gas, and reaction temperature is 200 DEG C ~ 500 DEG C, and reaction pressure is 100mTorr ~ 200mTorr, and provides a power to be 10W ~ 100W, and frequency is the radio frequency power source of 10MHz ~ 15MHz; Have compression second described in the formation method of stressor layers 202 comprise: using plasma strengthens chemical vapor deposition method, wherein, NH
3and SiH
4as reacting gas, inert gas is as carrier gas, and reaction temperature is 200 DEG C ~ 500 DEG C, and reaction pressure is 100mTorr ~ 200mTorr, and provides a power to be 10W ~ 100W, and frequency is the low frequency power source of 50KHz ~ 500kHz.Said method is adopted to form described first stressor layers 201 and the second stressor layers 202 respectively.
Please refer to Fig. 8, described stressor layers 200 is formed the sacrifice layer 203 with some openings 204, and described opening 204 exposes the surface of part stressor layers 200.
The formation method of described sacrifice layer 203 comprises: in described stressor layers 202, form sacrificial material layer; Form Patterned masking layer on described sacrificial material layer surface, described Patterned masking layer defines position and the size of opening; With described Patterned masking layer for sacrificial material layer described in mask etching, form opening 204 in described sacrificial material layer, residue sacrificial material layer is as sacrifice layer 203.
The material of the spacer material layer of the material of described sacrifice layer 203 and the material of stressor layers 202 and follow-up formation is not identical, to make having different etching selection ratio between each material.
Described sacrifice layer 203 adopts and is easy to remove, and can not cause the material of residual defects.The material of described sacrifice layer 203 is photoresist, bottom antireflective coating or silicon nitride.In the present embodiment, the material of described sacrifice layer 203 is photoresist.
Please refer to Fig. 9, form spacer material layer 205 in described stressor layers 200 and sacrifice layer 203 surface.
The material of described spacer material layer 205 is not identical with the material of sacrifice layer 203, and the material of described spacer material layer 205 is one or more in silica, silicon nitride, silicon oxynitride, carborundum, fire sand.Described spacer material layer 205 is single layer structure or multilayer lamination structure, can be the double stacked structure of silicon oxide-silicon nitride or the three level stack structure of oxide-nitride-oxide.In the present embodiment, described spacer material layer 205 is the silicon oxide layer of individual layer.
In the present embodiment, adopt atom layer deposition process to form described spacer material layer 205, adopt atom layer deposition process that described spacer material layer 205 surface can be made to have good surface smoothness, and be easy to the thickness controlling described spacer material layer 205.In other embodiments of the invention, chemical vapor deposition method can also be adopted to form described spacer material layer 205.
Described spacer material layer 205 is formed in stressor layers 200 surface, described stressor layers 200 has certain effect of stress to described spacer material layer 205, the effect of stress between spacer material layer 205 pairs of sacrifice layer 203 can be eliminated, sacrifice layer 203 is avoided to be subject to the effect of stress of spacer material layer 205, there is deformation, after follow-up removal sacrifice layer 203, the side wall on the sidewall of sacrifice layer 203 both sides can be avoided to deform to sacrifice layer direction.
The one-tenth-value thickness 1/10 of described spacer material layer 205 is less than the half of the spacing dimension between adjacent sacrifice layer 203.
Please refer to Figure 10, formed on described spacer material layer 205 surface and fill full described opening 204(and please refer to Fig. 9) dielectric layer 206.
The material of described dielectric layer 206 is photoresist, antireflection material, SiCO or SiCOH, and other suitable organic material.The material of described dielectric layer 206 can be identical or different with the material of sacrifice layer.In the present embodiment, the material of described dielectric layer 206 is identical with the material of sacrifice layer 203, in subsequent technique, can remove described dielectric layer 206 and sacrifice layer 203 simultaneously, thus Simplified flowsheet step.In the present embodiment, the material of described dielectric layer 206 is photoresist, and adopt spin coating proceeding to form described dielectric layer, described dielectric layer 206 fills full gate mouth 204.
Please refer to Figure 11, with described sacrifice layer 203 for stop-layer, Figure 10 be please refer to described dielectric layer 206() carry out planarization, expose the top surface of sacrifice layer 203.
With described sacrifice layer 203 for stop-layer, cmp process is carried out to described dielectric layer 206, make described smooth after the surface of dielectric layer 206a flush with the surface of sacrifice layer 203, in smooth process, also been removed the spacer material layer at sacrifice layer 203 top simultaneously, form the side wall 205a flushed with sacrifice layer 203 surface, expose the top surface of sacrifice layer 203, be convenient to the described sacrifice layer 203 of follow-up removal.
Please refer to Figure 12, remove described sacrifice layer 203(and please refer to Figure 11) and planarization after dielectric layer 206a.
In the present embodiment, described sacrifice layer 203 is identical with the material of dielectric layer 206a, is photoresist, so cineration technics can be adopted to remove described sacrifice layer 203(please refer to Figure 11 simultaneously) and planarization after dielectric layer 206a.In other embodiments of the invention, wet-etching technology also can be adopted to remove described dielectric layer 206a and sacrifice layer 203 respectively.
After removing described dielectric layer 206a and sacrifice layer 203, expose the surface of the stressor layers 200 of sacrifice layer position.
Please refer to Figure 13, etch described stressor layers 200, in described stressor layers 200, form the groove 207 running through described stressor layers 200.
Figure 12 is please refer to described side wall 205a() for mask, etch described stressor layers 200.Anisotropic dry etch process is adopted to etch described stressor layers 200.In the present embodiment, the material of described stressor layers 200 is silicon nitride, and the etching gas etching the employing of described stressor layers 200 is for containing fluorine-based gas, such as: SF
6, CH
2f
2in one or more.In dry etching process, can carry out etching to side wall 205a simultaneously and form side wall 205b, described side wall 205b is discrete sidewall structure.
In the present embodiment, etching stressor layers forms the groove 207 running through stressor layers 200, described groove 207 makes stressor layers 200 be divided into some undersized stressor layers, reduce the stress in stressor layers, separate between the side wall 205b on adjacent undersized stressor layers surface, the stress influence of all the other stressor layers can not be subject to, thus the stress eliminated or reduce between stressor layers 200 and side wall 205b, and the stress eliminated or reduce between stressor layers 200 and hard mask layer 101, layer to be etched 100.And, while etching forms described groove 207, side wall 205a is etched, make mutually to disconnect between the side wall on some undersized stressor layers surfaces, and depression can be formed on described some undersized stressor layers surfaces, make to be separated from each other between the side wall on described undersized stressor layers surface, there is no effect of stress each other.Therefore, said method can make side wall 205b the stress elimination of deformation occur or be reduced to minimum, thus avoids side wall 205b that deformation occurs.In other embodiments of the invention, after the described groove 207 of formation, can also continue to etch the stressor layers 200 between adjacent grooves 207, using hard mask layer 101 as etching stop layer, the stress in described stressor layers 200 can be reduced further.
Follow-up, with described double-pattern for mask, etch described hard mask layer 101, by Graphic transitions on hard mask layer 101.Due in described double-pattern, the stress that side wall 205b is subject to is less or do not have effect of stress, and side wall can keep vertical, so be conducive to being transferred to by figure in hard mask layer 101 accurately, follow-uply etch described layer to be etched again, figure accurately can be formed.
Please refer to Figure 14, with described side wall 205b, stressor layers 200 for mask, etch described hard mask layer 101, and material layer to be etched, at described interior formation to be etched figure to be etched.
The present invention also provides a kind of double-pattern structure adopting said method to be formed.
Please refer to Figure 13, described double-pattern structure comprises: layer to be etched 100; Be positioned at the some discrete stressor layers 200 on layer to be etched 100; Be positioned at the discrete side wall 205b on the surface, two ends of stressor layers 200.
In the present embodiment, between described layer to be etched 100 and stressor layers 200, also there is hard mask layer 101.
The material of described stressor layers 200 is silicon nitride, carborundum or tetraethoxysilane.The thickness of described stressor layers is
the stress intensity of described stressor layers is 50MPa ~ 1000MPa, and described stressor layers 200 can be individual layer or double-decker.
The stressor layers of described single layer structure has compression or tensile stress.In the present embodiment, described stressor layers 200 is double-decker, described double-deck stressor layers 200 comprise be positioned at described layer to be etched on tensile stress layer 201 and be positioned at the compressive stress layer 202 on described tensile stress layer surface.
The material of described side wall 205b is one or more in silica, silicon nitride, silicon oxynitride, carborundum, fire sand.
It is less or do not have that the side wall 205b of above-mentioned double-pattern structure is subject to the stress influence of bottom stress layer, side wall can keep vertical profile, the accuracy of the follow-up etched features formed in layer to be etched 100 for mask with described double-pattern structure is higher, is conducive to the quality of the device of follow-up formation.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a formation method for double-pattern structure, is characterized in that, comprising:
There is provided layer to be etched;
Described layer to be etched on form stressor layers;
Described stressor layers is formed the sacrifice layer with some openings, and described opening exposes the surface of part stressor layers;
Spacer material layer is formed in described stressor layers and sacrificial layer surface;
The dielectric layer of filling full described opening is formed on described spacer material layer surface;
With described sacrifice layer for stop-layer, planarization is carried out to described dielectric layer, expose the top surface of sacrifice layer;
Remove described sacrifice layer and dielectric layer;
With described spacer material layer for mask, etch described stressor layers, form the groove running through described stressor layers.
2. the formation method of double-pattern structure according to claim 1, is characterized in that, described stressor layers is single layer structure or double-decker.
3. the formation method of double-pattern structure according to claim 2, is characterized in that, the material of described stressor layers is silicon nitride, carborundum or tetraethoxysilane.
4. the formation method of double-pattern structure according to claim 2, is characterized in that, the thickness of described stressor layers is
5. the formation method of double-pattern structure according to claim 2, is characterized in that, the stressor layers of described single layer structure has compression or tensile stress.
6. the formation method of double-pattern structure according to claim 2, is characterized in that, the stress intensity of described stressor layers is 50MPa ~ 1000MPa.
7. the formation method of double-pattern structure according to claim 2, is characterized in that, described double-deck stressor layers comprise be positioned at described layer to be etched on tensile stress layer and be positioned at the compressive stress layer on described tensile stress layer surface.
8. the formation method of double-pattern structure according to claim 1, is characterized in that, the material of described sacrifice layer is photoresist, antireflecting coating or silicon nitride.
9. the formation method of double-pattern structure according to claim 1, is characterized in that, adopts atom layer deposition process to form described spacer material layer.
10. the formation method of double-pattern structure according to claim 1, is characterized in that, the material of described dielectric layer is photoresist, antireflection material, SiCO or SiCOH.
The formation method of 11. double-pattern structures according to claim 1, it is characterized in that, described material layer to be etched is advanced low-k materials, amorphous silicon, amorphous carbon, silica, SiN, SiON, SiCN, SiC, BN, SiCO, SiCOH, BN or TiN.
The formation method of 12. double-pattern structures according to claim 1, is characterized in that, treats that sacrificial layer surface is formed after hard mask layer described, forms stressor layers on described hard mask layer surface.
13. 1 kinds of double-pattern structures, is characterized in that, comprising:
Layer to be etched;
Be positioned at layer to be etched on some discrete stressor layers;
Be positioned at the discrete side wall on the surface, two ends of stressor layers.
14. double-patterns according to claim 13, is characterized in that, described stressor layers is single layer structure or double-decker.
15. double-pattern structures according to claim 13, is characterized in that, the material of described stressor layers is silicon nitride, carborundum or tetraethoxysilane.
16. double-pattern structures according to claim 13, is characterized in that, the thickness of described stressor layers is
17. double-pattern structures according to claim 14, is characterized in that, the stressor layers of described single layer structure has compression or tensile stress.
18. double-pattern structures according to claim 14, is characterized in that, the stress intensity of described stressor layers is 50MPa ~ 1000MPa.
19. double-pattern structures according to claim 14, is characterized in that, described double-deck stressor layers comprise be positioned at described layer to be etched on tensile stress layer and be positioned at the compressive stress layer on described tensile stress layer surface.
20. double-pattern structures according to claim 13, is characterized in that, the material of described side wall is one or more in silica, silicon nitride, silicon oxynitride, carborundum, fire sand.
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