US20030137479A1 - Planar display device for generating gradation voltage by use of resistance elements - Google Patents

Planar display device for generating gradation voltage by use of resistance elements Download PDF

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Publication number
US20030137479A1
US20030137479A1 US10/341,518 US34151803A US2003137479A1 US 20030137479 A1 US20030137479 A1 US 20030137479A1 US 34151803 A US34151803 A US 34151803A US 2003137479 A1 US2003137479 A1 US 2003137479A1
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US
United States
Prior art keywords
gradation voltage
display device
elements
resistance elements
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/341,518
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English (en)
Inventor
Nobuo Yamasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of US20030137479A1 publication Critical patent/US20030137479A1/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only

Definitions

  • the present invention relates to a planar display device for generating a gradation voltage corresponding to video data by dividing a power source voltage with a plurality of resistance elements.
  • planar display device typified by a liquid crystal display device has spread as display devices for various kinds of appliances because of its lower power consumption in addition to its thin structure and lightweight.
  • planar display device using a polysilicon thin film transistors (p-Si TFTs) as switching elements can form a display section, data driver, and scan driver integrally in an array substrate, this planar display device achieves a high precision, a compact sized shape and light weight.
  • the data driver for supplying video data to signal lines adopt a digital input type, because it shows little fluctuation of the video data.
  • a voltage selection type has been known.
  • This type of data driver selects a gradation voltage corresponding to video data of a digital signal to write it to a signal line.
  • the gradation voltages of plural levels are generated by dividing power source voltage with a plurality of resistance elements.
  • a switching element is provided for each resistance, and the gradation voltage corresponding to the video data is selected by the switching element.
  • switching noises caused when the gradation voltage is selected propagate to signal lines, and reduce the image quality.
  • a planar display device of the present invention comprises a display section including scanning lines and signal lines wired in the form of matrix and a pixel arranged for each element of the matrix, a scan driver configured to output a scanning signal to the each scanning line, and a data driver including a gradation voltage generator configured to generate gradation voltages of plural levels by dividing a power source voltage with a plurality of resistance elements and a gradation voltage selector configured to select a gradation voltage corresponding to video data with switching elements, the data driver outputting the selected gradation voltage as an analog signal to the signal line.
  • a capacitance element is electrically connected to at least one of the resistance elements.
  • the display section, the scan driver, and the data driver in which polysilicon thin film transistors are used as switching elements are formed in an array substrate, and the capacitance element is formed in an external substrate.
  • the capacitance element is electrically connected to the resistance elements that generate gradation voltages of intermediate tones.
  • FIG. 1 is a block diagram showing the entire structure of a planar display device of one embodiment.
  • FIG. 2 is a circuit diagram showing a constitution of a data driver shown in FIG. 1.
  • connection means a state in which two elements are electrically connected to each other without regard to whether or not there is a physical connection between the elements.
  • a display section 110 As shown in a block diagram of FIG. 1, a display section 110 , a data driver 120 and a scan driver 130 , which drive the display section 110 , are formed in an array substrate 101 .
  • the display section 110 comprises a plurality of signal lines D 1 , D 2 , . . . (hereinafter referred generically to as D) and a plurality of scanning lines G 1 , G 2 , . . . (hereinafter referred generically to as G).
  • the signal lines D and the scanning lines G are wired in the form of matrix. Pixels 10 are arranged for each element of the matrix. In order to simplify, the only one of pixels 10 is shown in FIG. 1. One end of each of the signal lines D is connected to the data driver 120 , and one end of each of the scanning lines G is connected to the scan driver 130 .
  • a pixel switching element 11 , a pixel electrode 12 , an opposite electrode 13 , a liquid crystal layer 14 and an auxiliary capacitance 15 constitute the pixel 10 .
  • the source of the pixel switching element 11 is connected to the signal line D, and the gate of the pixel switching element 11 is connected to the scanning line G.
  • the drain of the pixel switching element 11 is connected to the pixel electrode 12 and the auxiliary capacitance 15 .
  • the pixel switching element 11 is controlled so as to be turned on or off by a scanning signal that is supplied to the scanning line G. When the pixel switching element 11 is turned on, the signal line D and the pixel electrode 12 electrically conduct, and the video data supplied to the signal line D is written to the pixel electrode 12 .
  • a liquid crystal layer 14 as a display layer is filled between the array substrate 101 and an opposite substrate (not shown).
  • a sealing member (not shown) seals the surrounding of the array substrate 101 and the opposite substrate.
  • the opposite electrode 13 is formed on the surface of the opposite substrate.
  • a voltage for the opposite electrode 13 (hereinafter referred to as an opposite electrode voltage) is supplied from an external substrate 102 so that the opposite electrode 13 and the pixel electrode 12 in the same pixel are electrically opposed.
  • the video data written to the pixel electrode 12 is charged between the pixel electrode 12 and the opposite electrode 13 as a signal voltage.
  • the liquid crystal layer 14 responses to the signal voltage, whereby a pictorial image is displayed on the pixel 10 .
  • the data driver 120 comprises a gradation voltage generator, a gradation voltage selector, a signal line selector and a digital controller, which are to be described later.
  • Video data of a digital signal and driver control signals are supplied from a control IC 140 of the external substrate 102 to the data driver 120 .
  • the gradation voltage selector and the signal line selector are operated based on the driver control signal, the video data is outputted as an analog signal to each signal line D for each predetermined period.
  • the scan driver 130 comprises a shift register, a level shifter and a buffer circuit, which are not shown.
  • the scan driver 130 outputs a scanning signal to each scanning line G based on the driver control signal supplied from the control IC 140 .
  • the external substrate 102 comprises a power source voltage generator (not shown) besides the control IC 140 .
  • the control IC 140 supplies the driver control signal, which includes clock signal and start signal, for controlling the operations of both of the drivers, the video data of the digital signal, the opposite electrode voltage, an auxiliary capacitance voltage and the like to a liquid crystal panel 100 .
  • the power source voltage generator supplies a power source voltage to each driver.
  • the external substrate 102 may be any one of a rigid substrate or a flexible substrate.
  • the data driver 120 comprises the digital controller 111 , the gradation voltage generator 112 , the gradation voltage selector 113 and the signal line selector 114 .
  • the digital controller 111 is a control circuit constituted by a shift register, a data latch and the like.
  • the digital controller 111 controls operation timings of the gradation voltage selector 113 and the signal line selector 114 based on the driver control signal.
  • the digital controller 111 converts the series video data to parallel data, and outputs it to the gradation voltage selector 113 .
  • the gradation voltage generator 112 is constituted by a plurality of resistance elements R 1 , R 2 , R 3 , . . . and Rn connected in series. Gradation voltages of plural levels are generated by dividing a power source voltage with the resistance elements R.
  • the power source voltage VDD is supplied from the power source generator.
  • the gradation voltage generator 112 generates the gradation voltages Vt 1 , Vt 2 , Vt 3 , . . . and Vtm of m levels (m: the number of gradations) between the VDD and the ground voltage GND, outputs the gradation voltages to the gradation voltage selector 113 .
  • Capacitance elements C 1 , C 2 , C 3 , . . . and Cm are connected to the resistance elements R 1 , R 2 , R 3 , . . . and R, respectively.
  • the respective resistance elements R have a resistance value equal to each other
  • the respective capacitance elements C have a capacitance value equal to each other.
  • the capacitance elements C are formed in the external substrate 102 as shown in FIG. 1. This is because polysilicon thin film transistors (p-Si TFTs) are used as switching elements in the array substrate 101 , it is very difficult to manufacture the planar display device so that the capacitor elements C having a large capacity are in the array substrate 101 .
  • the gradation voltage selector 113 is constituted by switching elements (not shown) of plural stages.
  • the gradation voltage selector 113 selects a gradation voltage among Vt 1 , Vt 2 , Vt 3 , . . . and Vtm corresponding to the video data that is supplied from the control IC 140 through the digital controller 111 .
  • the gradation voltage selector 113 outputs this selected gradation voltage to the signal line selector 114 as an analog signal.
  • the signal line selector 114 selects a signal line D to which the analog signal is to be supplied, and amplifies this analog signal to a level necessary for outputting this analog signal to the signal line D.
  • the gradation voltage selector 113 selects the gradation voltage corresponding to the video data, the switching noises due to the switching elements within it occur. However, the switching noises are absorbed by the capacitance elements C 1 , C 2 , C 3 , . . . and Cm corresponding to the respective switching elements. Thus, little switching noise propagates to the signal line, and it is possible to prevent the level fluctuation of the gradation voltages.
  • the video data of analog signal having the gradation level nearly equal to a design value will be written to the pixel electrode 14 , and the image quality can be improved.
  • the capacitance elements C can be constituted by use of such capacitance, whereby it is possible to secure capacitance components of sufficient capacity required to reduce the switching noises.
  • the capacitance elements C 1 , C 2 , C 3 , . . . and Cm are respectively connected to the plurality of resistance elements R 1 , R 2 , R 3 , . . . and Rn was described.
  • the capacitance elements C may be connected to at least one of the resistance elements R.
  • one capacitance element C may be connected to a resistance element R at intervals of one-to-three resistance elements respectively.
  • the capacitance elements C may be connected to the only resistance elements R generating gradation voltages of intermediate tones that are used frequently.
  • the present invention was applied to the liquid crystal display device.
  • the present invention can be also applied to planar display devices having another display layer.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
US10/341,518 2002-01-18 2003-01-14 Planar display device for generating gradation voltage by use of resistance elements Abandoned US20030137479A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002010245A JP4071502B2 (ja) 2002-01-18 2002-01-18 平面表示装置
JP2002-010245 2002-01-18

Publications (1)

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US20030137479A1 true US20030137479A1 (en) 2003-07-24

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US (1) US20030137479A1 (ja)
JP (1) JP4071502B2 (ja)
KR (1) KR20030063156A (ja)
TW (1) TW584825B (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040191650A1 (en) * 2000-07-05 2004-09-30 Numerical Technologies Phase shift masking for complex patterns with proximity adjustments
US20060044301A1 (en) * 2004-09-02 2006-03-02 Samsung Electronics Co., Ltd. Display device and driving method thereof
US20070070026A1 (en) * 2005-09-29 2007-03-29 Samsung Electronics Co., Ltd. Liquid crystal display
WO2015007084A1 (zh) * 2013-07-19 2015-01-22 深圳市华星光电技术有限公司 一种调灰电压产生方法及其装置和面板驱动电路
US20190206358A1 (en) * 2016-09-27 2019-07-04 Sharp Kabushiki Kaisha Display device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
JP2006018148A (ja) * 2004-07-05 2006-01-19 Funai Electric Co Ltd 液晶駆動装置
JP2006189806A (ja) * 2004-12-06 2006-07-20 Semiconductor Energy Lab Co Ltd 表示装置及びその駆動方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5095304A (en) * 1988-10-07 1992-03-10 U.S. Philips Corporation Matrix display device
US6225992B1 (en) * 1997-12-05 2001-05-01 United Microelectronics Corp. Method and apparatus for generating bias voltages for liquid crystal display drivers
US6466191B1 (en) * 1998-12-24 2002-10-15 Samsung Electronics Co., Ltd. Liquid crystal display thin film transistor driving circuit
US6894674B2 (en) * 2000-12-06 2005-05-17 Sony Corporation Timing generation circuit for display apparatus and display apparatus incorporating the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5095304A (en) * 1988-10-07 1992-03-10 U.S. Philips Corporation Matrix display device
US6225992B1 (en) * 1997-12-05 2001-05-01 United Microelectronics Corp. Method and apparatus for generating bias voltages for liquid crystal display drivers
US6466191B1 (en) * 1998-12-24 2002-10-15 Samsung Electronics Co., Ltd. Liquid crystal display thin film transistor driving circuit
US6894674B2 (en) * 2000-12-06 2005-05-17 Sony Corporation Timing generation circuit for display apparatus and display apparatus incorporating the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040191650A1 (en) * 2000-07-05 2004-09-30 Numerical Technologies Phase shift masking for complex patterns with proximity adjustments
US20060044301A1 (en) * 2004-09-02 2006-03-02 Samsung Electronics Co., Ltd. Display device and driving method thereof
US20070070026A1 (en) * 2005-09-29 2007-03-29 Samsung Electronics Co., Ltd. Liquid crystal display
US7812808B2 (en) * 2005-09-29 2010-10-12 Samsung Electronics Co., Ltd. Liquid crystal display
WO2015007084A1 (zh) * 2013-07-19 2015-01-22 深圳市华星光电技术有限公司 一种调灰电压产生方法及其装置和面板驱动电路
US9875680B2 (en) 2013-07-19 2018-01-23 Shenzhen China Star Optoelectronics Technology Co., Ltd. Method and apparatus for generation of gray scale adjustment voltage and panel driver circuit
US20190206358A1 (en) * 2016-09-27 2019-07-04 Sharp Kabushiki Kaisha Display device
US10706808B2 (en) 2016-09-27 2020-07-07 Sharp Kabushiki Kaisha Display device

Also Published As

Publication number Publication date
KR20030063156A (ko) 2003-07-28
JP4071502B2 (ja) 2008-04-02
TW200306513A (en) 2003-11-16
TW584825B (en) 2004-04-21
JP2003216114A (ja) 2003-07-30

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