US20030054619A1 - Method and apparatus for automatic wiring design between block circuits of integrated circuit - Google Patents
Method and apparatus for automatic wiring design between block circuits of integrated circuit Download PDFInfo
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- US20030054619A1 US20030054619A1 US10/209,927 US20992702A US2003054619A1 US 20030054619 A1 US20030054619 A1 US 20030054619A1 US 20992702 A US20992702 A US 20992702A US 2003054619 A1 US2003054619 A1 US 2003054619A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
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- the present invention relates to a method and an apparatus for automatic wiring design between block circuits of an integrated circuit and a program for performing the same method.
- FIG. 12 is a view for illustrating a conventional method for automatic wiring design between block circuits of an integrated circuit.
- inter-block wires 12 and 13 are disposed between circuit blocks 10 and 11
- terminals 101 and 102 are formed along a side 10 S of the circuit block 10 which faces the circuit block 11
- terminals 111 and 112 are formed along a side 11 S of the circuit block 11 which faces the circuit block 10
- a contact hole 101 C is formed at a cross portion between the inter-block wire 12 and a wire 101 L extended from the terminal 101 , and is connected to the wire 101 L.
- a contact hole 112 C is formed at a cross portion between the inter-block wire 12 and a wire 112 L extended from the terminal 112 , and is connected to the wire 112 L.
- the block wire 12 is connected to the wires 101 L and 112 L belonging to upper or lower wire layers, respectively.
- the terminal 101 , the wire 101 L, the contact hole 101 C, the inter-block wire 12 , the contact hole 112 C, the wire 112 L and the terminal 112 belong to a same net.
- the terminal 111 and the inter-block wire 13 can be connected to each other as shown in this figure, but the terminal 102 and the inter-block wire 13 cannot be connected to each other.
- Wiring layout processes has already been performed for the inside of the circuit blocks 10 and 11 , and the block information in the inter-block wiring is given only about the frame and the terminal of the block, and therefore wire extension from the terminal to the internal of the block is forbidden in the inter-block wiring.
- the prior art employs a method as shown in FIG. 13 where interval between the circuit blocks 10 and 11 is made widened; a wire 102 L is extended and bent from the terminal 102 ; a contact hole 102 C is formed at a cross portion between the wire 102 L and the inter-block wire 13 ; and the wire 102 L and the inter-block wire 13 are connected to each other through the contact hole 102 C.
- This falls into increasing the wiring area between the circuit blocks 10 and 11 and also changing the wiring area between the circuit block 10 or 11 and other circuit blocks not shown, causing the rewiring.
- a manual connection must be carried out between the blocks in the layout state shown in FIG. 12, but it requires much longer time in design.
- FIG. 15 a method can be considered as shown in FIG. 15 where the area between the circuit blocks 10 and 11 is secured in advance two times as that in the case shown in FIG. 12; additional inter-block wires 12 A and 13 A are disposed parallel to the inter-block wires 12 and 13 ; the inter-block wires 12 A and 13 A are connected to the inter-block wires 12 and 13 , respectively; the inter-block wires 12 and 13 are used for connection with the terminals of the circuit block 10 ; and the inter-block wires 12 A and 13 A are used for connection with the terminals of the circuit block 11 .
- this method leads to increase in the inter-block area.
- a method for automatic wiring design between block circuits of an integrated circuit which performs an automatic connection between an inter-block wire disposed between a first circuit block and a second circuit block, and terminals formed along sides of the first and second blocks, the sides facing each other, the method comprising the steps of:
- connection is made for the block terminals in descending order of the width thereof, and therefore the length of extended wire from larger width terminals becomes shorter, which allows reducing the inter-block wiring area.
- forming the contact hole is also performed in descending order of the width thereof, it can be avoided that a larger width wire is connected to a smaller width contact hole.
- the method for automatic wiring design between block circuits of an integrated circuit comprises the steps of:
- connection is made for the terminal having larger current value, earlier than the terminal having smaller current value even though they have the same width.
- FIG. 1 is a schematic block diagram showing the hardware configuration of the apparatus for automatic wiring design between block circuits of an integrated circuit according to a first embodiment of the present invention.
- FIG. 2 is a schematic flow chart of part of the program stored in the storage shown in FIG. 1.
- FIG. 3 is a view showing a layout before performing the inter-block connection, which is used for illustrating the data stored in the storage 22 shown in FIG. 1.
- FIG. 4 is a view for illustrating step S 6 shown in FIG. 2.
- FIG. 5 is a view for illustrating step S 8 shown in FIG. 2.
- FIG. 6 is a view for illustrating step S 10 shown in FIG. 2 .
- FIG. 7 is a view for illustrating step S 11 shown in FIG. 2.
- FIG. 8 is a layout view showing a case where the automatic connection is made by the method shown in FIG. 2.
- FIG. 9 is a layout view showing another case where the automatic connection is made by the method shown in FIG. 2.
- FIG. 10 is a schematic flow chart for partly showing the method for automatic wiring design between the circuit blocks of an integrated circuit according to a second embodiment of the present invention.
- FIG. 11 is a layout view showing a case where the automatic connection is made by the method shown in FIG. 10.
- FIG. 12 is a view for illustrating a problem in a conventional method for automatic wiring design between block circuits of an integrated circuit.
- FIG. 13 is a view for illustrating a problem in a conventional method where automatic connection and correction is made for the layout state shown in FIG. 12.
- FIG. 14 is a view for illustrating another problem in a conventional method for automatic wiring design between block circuits of an integrated circuit.
- FIG. 15 is a view for illustrating still another problem in a conventional method for automatic wiring design between block circuits of an integrated circuit.
- FIG. 1 is a schematic block diagram showing the hardware configuration of the apparatus for automatic wiring design between block circuits of an integrated circuit according to a first embodiment of the present invention.
- the apparatus of this embodiment is a computer system which comprises, as shown in FIG. 1, a computer 20 , and storages 21 ⁇ 23 , an input device 24 and a display device 25 , each coupled to the computer 20 .
- the computer 20 loads a program stored in the storage 21 into a main storage, in response to a starting command from the input device 24 .
- the computer 20 reads wiring data from the storage 22 ; automatically performs inter-block connection; stores result of the automatic connection in the storage 23 ; and displays the contents of log file, including the achievement ratio of automatic wiring, not-connected information and the like, on the display device 25 .
- FIG. 3 is a view for illustrating the data stored in the storage 22 shown in FIG. 1, where inter-block wires 12 and 13 are disposed between circuit blocks 10 and 11 , terminals 101 and 102 are formed along a side 10 S of the circuit block 10 which faces the circuit block 11 , and terminals 111 and 112 are formed along a side 11 S of the circuit block 11 which faces the circuit block 10 .
- the storage 22 stores, as wiring data, frame data of the circuit blocks 10 and 11 , data of terminals 101 and 102 in the circuit block 10 and terminals 111 and 112 in the circuit block 11 , data of inter-block wires 12 and 13 , and net-list for inter-block connection.
- the data of the block frame and the block terminal is a cell data registered in a cell library, where the data of the block frame includes the identification code, the position, the size and the direction thereof, the data of the block terminal includes the identification code and the position and the size thereof.
- the direction of the block corresponds to an angle between the direction of its cell in the cell library and the altered direction after it is disposed in the design surface.
- the data of the inter-block wire includes the identification code, the end position, and the width thereof.
- FIG. 2 is a schematic flow chart of part of the program stored in the storage 21 shown in FIG. 1.
- the following parenthesized reference numerals refer to steps shown in FIG. 2.
- Terminals formed along sides of blocks facing each other are sorted in descending order of the width (largest width first). For example, in a case of FIG. 3, terminals 101 , 112 , 102 and 111 are sorted in the mentioned order.
- step S 4 If there is no terminal to be selected in step S 3 , the procedure is finished, and if not, it moves to step S 5 .
- step S 5 If there is no contact hole already formed on an inter-block wire belonging to the same net as the terminal selected in step S 3 , the procedure moves to step S 6 , and if not, it moves to step S 7 .
- a wire having the same width as the terminal selected in step S 3 is extended from the selected terminal, with the shortest extended route satisfying the design rule and is connected to the inter-block wire belonging to the same net.
- a wire 101 L is extended from the terminal 101 in the direction perpendicular to a side 10 S; a contact hole 101 C is formed at the cross portion between the wire 101 L and the inter-block wire 12 ; and the wire 101 L is connected to the contact hole 101 C.
- the inter-block wire 12 belongs to lower or upper wire layers with respect to the wire 101 L and is connected to the wire 101 L through the contact hole 101 C. Thereafter, the procedure returns to step S 3 .
- step S 7 when it is assumed that a wire having the same width as the terminal selected in step S 3 is extended from the selected terminal, with the shortest extended route satisfying the design rule and is connected to the inter-block wire belonging to the same net, if the cross portion between the extended wire and the inter-block wire, that is, the contact hole to be formed is overlapped with the already-formed contact hole, the procedure moves to step S 8 , and if not, it moves to step S 9 . For instance, in a case shown in FIG.
- step S 8 Without forming a contact hole, the terminal selected in step S 3 is connected to the contact hole overlapped therewith. For instance, in a case shown in FIG. 5, the terminal 111 is connected to the already-formed contact hole 101 C through a bent wire 111 L. Thereafter, the procedure returns to step S 3 .
- step S 9 In a case where a space width between the wire extended in step S 7 and the wire which belongs to the same net as the extended wire and has been connected to the already-formed contact hole satisfies the design rule, the procedure moves to step S 10 , and if not, it moves to step S 11 .
- the branch or cross of destination is determined based on whether the design rule is satisfied by the space width SL between the wire 111 L extended from the terminal 111 and the wire 101 L connected to the already-formed contact hole 101 C.
- step S 11 In a case as shown in FIG. 7 where the space width SL between the wire 111 A extended in step S 7 and the already-formed wire 101 L does not satisfy the design rule, the terminal 111 is connected to the contact hole 101 C through a bent wire 111 L, without forming a new contact hole. Thereafter, the procedure returns to step S 3 .
- FIGS. 8 and 9 show examples where the automatic connection is performed by the method shown in FIG. 2.
- FIG. 8 shows a case where terminals 102 and 111 and an inter-block wire 13 belong to one same net, and terminals 101 and 112 and an inter-block wire 12 belong to another same net.
- the terminals 101 and 102 have widths larger than the terminals 111 and 112 , and therefore after connection between the terminals 101 and 102 is performed in step S 6 shown in FIG. 2, connection between the terminals 111 and 112 is performed in step S 10 shown in FIG. 2.
- This method allows reducing the wiring region between the circuit blocks 10 and 11 , compared with the conventional case shown in FIG. 13.
- FIG. 9 shows a case where terminals 101 and 111 and an inter-block wire 13 belong to one same net, and terminals 102 and 112 and an inter-block wire 12 belong to another same net.
- the terminals 101 and 102 have width larger than the terminals 111 and 112 , and therefore after the connection processes for the terminals 101 and 102 are performed in step S 6 shown in FIG. 2, the connection processes for the terminals 111 and 112 are performed in step S 8 shown in FIG. 2.
- This method prevents forming of the contact hole 112 C having a narrow width as shown in FIG. 14.
- a method for automatic wiring design between block circuits of an integrated circuit according to the second embodiment of the present invention employs a procedure shown in FIG. 10 instead of step S 2 shown in FIG. 2.
- step S 21 When there is a block terminal connected to a power supply wire, the procedure moves to step S 21 , and if not, it moves to step S 23 .
- step S 22 The same repeated procedure as the steps S 3 ⁇ S 11 shown in FIG. 2 is performed for the terminals connected to the power supply wire. However, differently from the first embodiment, a terminal having next larger current value is selected in step S 3 shown in FIG. 2.
- step S 23 If there is a block terminal connected to a signal wire, the procedure moves to step S 2 , which is the same as step S 2 shown in FIG. 2, and if not, the procedure is finished.
- FIG. 11 shows an example where the automatic connection is performed by the method shown in FIG. 10.
- FIG. 11 shows a case where inter-block wires 12 and 13 are power supply wires; terminals 101 and 112 and an inter-block wire 12 belong to one same net, and terminals 102 and 111 and an inter-block wire 13 belong to another same net.
- the terminals 111 , 102 , 101 and 112 are in descending order of the current value, and their connection processes are performed in the order.
- connection is made for the terminal 102 having larger current value I 2 , earlier than the terminal 112 having smaller current value I 1 even though they have the same width, which allows the power supply wire to be shortened in length, so that the whole electromigration tolerance of an integrated circuit is improved compared with a case where the connection is made in inverse order.
- the number of inter-block wires is only required to be more than one, and also the number of terminals formed along the block sides facing each other is only required to be more than one.
- the circuit block may be anyone of a cell, a macro cell, or a hard macro, or the like.
- a method may be employed where calculation is made for obtaining the current value (time average or maximum value) of the signal terminal, and the connection is made in descending order of the current value for the signal terminals having the same width. This method also improves the electromigration tolerance.
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Abstract
Description
- 1. Field of the Invention
- The present invention relates to a method and an apparatus for automatic wiring design between block circuits of an integrated circuit and a program for performing the same method.
- 2. Description of the Related Art
- As the latest semiconductor integration circuit becomes to have higher integration density and larger scale, the number of wires increases and also a demand arises for much narrower wire region and much higher integration density thereof.
- FIG. 12 is a view for illustrating a conventional method for automatic wiring design between block circuits of an integrated circuit.
- As shown in this figure,
inter-block wires circuit blocks terminals side 10S of thecircuit block 10 which faces thecircuit block 11, andterminals side 11S of thecircuit block 11 which faces thecircuit block 10. Acontact hole 101C is formed at a cross portion between theinter-block wire 12 and awire 101L extended from theterminal 101, and is connected to thewire 101L. Similarly, acontact hole 112C is formed at a cross portion between theinter-block wire 12 and awire 112L extended from theterminal 112, and is connected to thewire 112L. Through thesecontact holes block wire 12 is connected to thewires terminal 101, thewire 101L, thecontact hole 101C, theinter-block wire 12, thecontact hole 112C, thewire 112L and theterminal 112 belong to a same net. - In a case where the
terminal 102, theinter-block wire 13 and theterminal 111 belong to a same net, theterminal 111 and theinter-block wire 13 can be connected to each other as shown in this figure, but theterminal 102 and theinter-block wire 13 cannot be connected to each other. Wiring layout processes has already been performed for the inside of thecircuit blocks - Thus, the prior art employs a method as shown in FIG. 13 where interval between the
circuit blocks wire 102L is extended and bent from theterminal 102; acontact hole 102C is formed at a cross portion between thewire 102L and theinter-block wire 13; and thewire 102L and theinter-block wire 13 are connected to each other through thecontact hole 102C. This falls into increasing the wiring area between thecircuit blocks circuit block - In addition, in a case where the
terminals inter-block wire 12 belong to a same net as shown in FIG. 14, if theterminal 112 and theinter-block wire 12 are first connected to each other through thewire 112L, acontact hole 112C is formed in the same size as the width of theterminal 112. Therefore, when theterminal 102 and thecontact hole 112C are connected to each other through thewire 102L, the wire resistance is increased due to the insufficient area of thecontact hole 112C, which causes increase in the signal delay and timing error. In a case where the wire is used for supplying the power supply, the increased wire resistance lowers the supplied voltage and the electromigration tolerance, resulting in reducing the reliance of the integration circuit. - In order to avoid these problems, a method can be considered as shown in FIG. 15 where the area between the
circuit blocks inter-block wires inter-block wires inter-block wires inter-block wires inter-block wires circuit block 10; and theinter-block wires circuit block 11. However, this method leads to increase in the inter-block area. - Accordingly, it is an object of the present invention to provide a method and an apparatus for automatic wiring design between block circuits of an integrated circuit and a program for performing the same method, which gives priority order to wring so as to reduce manual processes by decreasing the number of not-connected wires as a result of the automatic wiring process, and also reduce the wiring area required to form the inter-block wiring.
- In one aspect of the present invention, there is provided a method for automatic wiring design between block circuits of an integrated circuit, which performs an automatic connection between an inter-block wire disposed between a first circuit block and a second circuit block, and terminals formed along sides of the first and second blocks, the sides facing each other, the method comprising the steps of:
- (a) sorting the terminals according to the width thereof; and
- (b) selecting a terminal from the terminals in descending order of the width, and connecting between the selected terminal and an inter-block wire belonging to a same net as the terminal.
- According to this method, the connection is made for the block terminals in descending order of the width thereof, and therefore the length of extended wire from larger width terminals becomes shorter, which allows reducing the inter-block wiring area. In addition, because forming the contact hole is also performed in descending order of the width thereof, it can be avoided that a larger width wire is connected to a smaller width contact hole.
- In another aspect of the present invention, the method for automatic wiring design between block circuits of an integrated circuit comprises the steps of:
- (a) sorting the terminals, connected to a power supply wire, according to the value of electric current passing through the terminals; and
- (b) selecting a terminal from the terminals in descending order of the value of electric current and connecting between the selected terminal and an inter-block wire belonging to a same net as the selected terminal.
- According to this method, the connection is made for the terminal having larger current value, earlier than the terminal having smaller current value even though they have the same width. This allows the length of a wire, which connects between the terminal having larger current value and the inter-block wire, to be shorter than a wire which connects between the terminal having smaller current value and the inter-block wire. Therefore the whole electromigration tolerance of an integrated circuit is improved compared with a case where the connection is made in inverse order. Further, this can prevent the voltage reduction due to the wire resistance.
- FIG. 1 is a schematic block diagram showing the hardware configuration of the apparatus for automatic wiring design between block circuits of an integrated circuit according to a first embodiment of the present invention.
- FIG. 2 is a schematic flow chart of part of the program stored in the storage shown in FIG. 1.
- FIG. 3 is a view showing a layout before performing the inter-block connection, which is used for illustrating the data stored in the
storage 22 shown in FIG. 1. - FIG. 4 is a view for illustrating step S6 shown in FIG. 2.
- FIG. 5 is a view for illustrating step S8 shown in FIG. 2.
- FIG. 6 is a view for illustrating step S10 shown in FIG. 2.
- FIG. 7 is a view for illustrating step S11 shown in FIG. 2.
- FIG. 8 is a layout view showing a case where the automatic connection is made by the method shown in FIG. 2.
- FIG. 9 is a layout view showing another case where the automatic connection is made by the method shown in FIG. 2.
- FIG. 10 is a schematic flow chart for partly showing the method for automatic wiring design between the circuit blocks of an integrated circuit according to a second embodiment of the present invention.
- FIG. 11 is a layout view showing a case where the automatic connection is made by the method shown in FIG. 10.
- FIG. 12 is a view for illustrating a problem in a conventional method for automatic wiring design between block circuits of an integrated circuit.
- FIG. 13 is a view for illustrating a problem in a conventional method where automatic connection and correction is made for the layout state shown in FIG. 12.
- FIG. 14 is a view for illustrating another problem in a conventional method for automatic wiring design between block circuits of an integrated circuit.
- FIG. 15 is a view for illustrating still another problem in a conventional method for automatic wiring design between block circuits of an integrated circuit.
- Hereinafter, the present invention will be described in more detail referring to the drawings.
- First Embodiment
- FIG. 1 is a schematic block diagram showing the hardware configuration of the apparatus for automatic wiring design between block circuits of an integrated circuit according to a first embodiment of the present invention.
- The apparatus of this embodiment is a computer system which comprises, as shown in FIG. 1, a
computer 20, andstorages 21˜23, aninput device 24 and adisplay device 25, each coupled to thecomputer 20. Thecomputer 20 loads a program stored in thestorage 21 into a main storage, in response to a starting command from theinput device 24. According to the program, thecomputer 20 reads wiring data from thestorage 22; automatically performs inter-block connection; stores result of the automatic connection in thestorage 23; and displays the contents of log file, including the achievement ratio of automatic wiring, not-connected information and the like, on thedisplay device 25. - FIG. 3 is a view for illustrating the data stored in the
storage 22 shown in FIG. 1, whereinter-block wires circuit blocks terminals side 10S of thecircuit block 10 which faces thecircuit block 11, andterminals side 11S of thecircuit block 11 which faces thecircuit block 10. - The
storage 22 stores, as wiring data, frame data of thecircuit blocks terminals circuit block 10 andterminals circuit block 11, data ofinter-block wires - FIG. 2 is a schematic flow chart of part of the program stored in the
storage 21 shown in FIG. 1. The following parenthesized reference numerals refer to steps shown in FIG. 2. - (S1) The wiring data is read out of the
storage 22. - (S2) Terminals formed along sides of blocks facing each other are sorted in descending order of the width (largest width first). For example, in a case of FIG. 3,
terminals - (S3) A next larger width terminal is selected. In the beginning, a terminal having the largest width is selected.
- (S4) If there is no terminal to be selected in step S3, the procedure is finished, and if not, it moves to step S5.
- (S5) If there is no contact hole already formed on an inter-block wire belonging to the same net as the terminal selected in step S3, the procedure moves to step S6, and if not, it moves to step S7.
- (S6) A wire having the same width as the terminal selected in step S3 is extended from the selected terminal, with the shortest extended route satisfying the design rule and is connected to the inter-block wire belonging to the same net. For example, in a case shown in FIG. 4 where a terminal 101 and an
inter-block wire 12 belong to the same net and there is no contact hole formed on theinter-block wire 12, awire 101L is extended from the terminal 101 in the direction perpendicular to aside 10S; acontact hole 101C is formed at the cross portion between thewire 101L and theinter-block wire 12; and thewire 101L is connected to thecontact hole 101C. Theinter-block wire 12 belongs to lower or upper wire layers with respect to thewire 101L and is connected to thewire 101L through thecontact hole 101C. Thereafter, the procedure returns to step S3. - (S7) when it is assumed that a wire having the same width as the terminal selected in step S3 is extended from the selected terminal, with the shortest extended route satisfying the design rule and is connected to the inter-block wire belonging to the same net, if the cross portion between the extended wire and the inter-block wire, that is, the contact hole to be formed is overlapped with the already-formed contact hole, the procedure moves to step S8, and if not, it moves to step S9. For instance, in a case shown in FIG. 5 where the terminal 101 has already been connected to the
inter-block wire 12, and acontact hole 101C has been formed between thewire 101L and theinter-block wire 12, when awire 111A is virtually extended from the terminal 111 in the direction perpendicular to theside 11S, the cross portion with theinter-block wire 12 is overlapped with an already-formedcontact hole 101C, and therefore the procedure moves to step S8. - (S8) Without forming a contact hole, the terminal selected in step S3 is connected to the contact hole overlapped therewith. For instance, in a case shown in FIG. 5, the terminal 111 is connected to the already-formed
contact hole 101C through abent wire 111L. Thereafter, the procedure returns to step S3. - (S9) In a case where a space width between the wire extended in step S7 and the wire which belongs to the same net as the extended wire and has been connected to the already-formed contact hole satisfies the design rule, the procedure moves to step S10, and if not, it moves to step S11. For instance, as shown in FIG. 6, the branch or cross of destination is determined based on whether the design rule is satisfied by the space width SL between the
wire 111L extended from the terminal 111 and thewire 101L connected to the already-formedcontact hole 101C. - (S10) In the case shown in FIG. 6, a
contact hole 111C is formed at the cross portion between theinter-block wire 12 and thewire 111L extended in step S7, and the terminal 111 is connected to thecontact hole 111C through thewire 111L. Thereafter, the procedure returns to step S3. - (S11) In a case as shown in FIG. 7 where the space width SL between the
wire 111A extended in step S7 and the already-formedwire 101L does not satisfy the design rule, the terminal 111 is connected to thecontact hole 101C through abent wire 111L, without forming a new contact hole. Thereafter, the procedure returns to step S3. - FIGS. 8 and 9 show examples where the automatic connection is performed by the method shown in FIG. 2.
- FIG. 8 shows a case where
terminals inter-block wire 13 belong to one same net, andterminals inter-block wire 12 belong to another same net. As shown in this figure, theterminals terminals terminals terminals - This method allows reducing the wiring region between the circuit blocks10 and 11, compared with the conventional case shown in FIG. 13.
- FIG. 9 shows a case where
terminals inter-block wire 13 belong to one same net, andterminals inter-block wire 12 belong to another same net. As shown in this figure, theterminals terminals terminals terminals - This method prevents forming of the
contact hole 112C having a narrow width as shown in FIG. 14. - Second Embodiment
- A method for automatic wiring design between block circuits of an integrated circuit according to the second embodiment of the present invention employs a procedure shown in FIG. 10 instead of step S2 shown in FIG. 2.
- (S20) When there is a block terminal connected to a power supply wire, the procedure moves to step S21, and if not, it moves to step S23.
- (S21) Calculation has been made in advance for obtaining the value (time average or maximum value) of electric current flowing through each block terminal connected to the power supply wire, and the
storage 22 shown in FIG. 1 has stored the obtained current value. The terminals connected to the power supply wire are sorted in descending order of the current value. - (S22) The same repeated procedure as the steps S3˜S11 shown in FIG. 2 is performed for the terminals connected to the power supply wire. However, differently from the first embodiment, a terminal having next larger current value is selected in step S3 shown in FIG. 2.
- (S23) If there is a block terminal connected to a signal wire, the procedure moves to step S2, which is the same as step S2 shown in FIG. 2, and if not, the procedure is finished.
- FIG. 11 shows an example where the automatic connection is performed by the method shown in FIG. 10.
- FIG. 11 shows a case where
inter-block wires terminals inter-block wire 12 belong to one same net, andterminals inter-block wire 13 belong to another same net. Theterminals - According to this method, the connection is made for the terminal102 having larger current value I2, earlier than the terminal 112 having smaller current value I1 even though they have the same width, which allows the power supply wire to be shortened in length, so that the whole electromigration tolerance of an integrated circuit is improved compared with a case where the connection is made in inverse order.
- In addition, the number of inter-block wires is only required to be more than one, and also the number of terminals formed along the block sides facing each other is only required to be more than one. Further, the circuit block may be anyone of a cell, a macro cell, or a hard macro, or the like. Furthermore, a method may be employed where calculation is made for obtaining the current value (time average or maximum value) of the signal terminal, and the connection is made in descending order of the current value for the signal terminals having the same width. This method also improves the electromigration tolerance.
- The forgoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teachings can be readily applied to other types of apparatuses or methods. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art.
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JP2001-250924 | 2001-08-22 | ||
JP2001250924A JP4596406B2 (en) | 2001-08-22 | 2001-08-22 | Method and apparatus for automatic wiring design between circuit blocks of integrated circuit and program for implementing the method |
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US20030054619A1 true US20030054619A1 (en) | 2003-03-20 |
US6760897B2 US6760897B2 (en) | 2004-07-06 |
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TWI246138B (en) * | 2003-09-08 | 2005-12-21 | Realtek Semiconductor Corp | Method for checking via density in IC layout |
US7725850B2 (en) * | 2007-07-30 | 2010-05-25 | International Business Machines Corporation | Methods for design rule checking with abstracted via obstructions |
JP5327347B2 (en) * | 2012-03-26 | 2013-10-30 | 富士通株式会社 | Macro layout verification apparatus and verification method |
JP7000287B2 (en) * | 2018-09-18 | 2022-01-19 | 株式会社東芝 | Integrated circuit |
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US5648910A (en) * | 1992-03-10 | 1997-07-15 | Nec Corporation | Method of automatically optimizing power supply network for semi-custom made integrated circuit device |
US6281529B1 (en) * | 1995-10-31 | 2001-08-28 | Fujitsu Limited | Semiconductor device having optimized input/output cells |
US20020038448A1 (en) * | 2000-09-13 | 2002-03-28 | Ricoh Company,Ltd. | Semiconductor integrated circuit device, and method of placement and routing for such device |
US20020095643A1 (en) * | 2001-01-17 | 2002-07-18 | Yuko Shiratori | Method and apparatus for revising wiring of a circuit to prevent electro-migration |
US20020127782A1 (en) * | 2001-03-07 | 2002-09-12 | Matsushita Electric Industrial Co., Ltd. | Wiring method in layout design of semiconductor integrated circuit, semiconductor integrated circuit and functional macro |
US20020149116A1 (en) * | 2001-03-05 | 2002-10-17 | Matsushita Electric Industrial Co., Ltd. | Integrated circuit device and method for forming the same |
US6492736B1 (en) * | 2001-03-14 | 2002-12-10 | Lsi Logic Corporation | Power mesh bridge |
US6496968B1 (en) * | 1998-08-18 | 2002-12-17 | Hitachi, Ltd. | Hierarchical wiring method for a semiconductor integrated circuit |
US6504187B1 (en) * | 1999-09-30 | 2003-01-07 | Sanyo Electric Co., Ltd. | Semiconductor integrated circuit and digital camera comprising the same |
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2663680B2 (en) * | 1990-05-24 | 1997-10-15 | 松下電器産業株式会社 | Channel wiring method |
-
2001
- 2001-08-22 JP JP2001250924A patent/JP4596406B2/en not_active Expired - Fee Related
-
2002
- 2002-08-02 US US10/209,927 patent/US6760897B2/en not_active Expired - Fee Related
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
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US5648910A (en) * | 1992-03-10 | 1997-07-15 | Nec Corporation | Method of automatically optimizing power supply network for semi-custom made integrated circuit device |
US6281529B1 (en) * | 1995-10-31 | 2001-08-28 | Fujitsu Limited | Semiconductor device having optimized input/output cells |
US6496968B1 (en) * | 1998-08-18 | 2002-12-17 | Hitachi, Ltd. | Hierarchical wiring method for a semiconductor integrated circuit |
US6504187B1 (en) * | 1999-09-30 | 2003-01-07 | Sanyo Electric Co., Ltd. | Semiconductor integrated circuit and digital camera comprising the same |
US20020038448A1 (en) * | 2000-09-13 | 2002-03-28 | Ricoh Company,Ltd. | Semiconductor integrated circuit device, and method of placement and routing for such device |
US20020095643A1 (en) * | 2001-01-17 | 2002-07-18 | Yuko Shiratori | Method and apparatus for revising wiring of a circuit to prevent electro-migration |
US20020149116A1 (en) * | 2001-03-05 | 2002-10-17 | Matsushita Electric Industrial Co., Ltd. | Integrated circuit device and method for forming the same |
US20020127782A1 (en) * | 2001-03-07 | 2002-09-12 | Matsushita Electric Industrial Co., Ltd. | Wiring method in layout design of semiconductor integrated circuit, semiconductor integrated circuit and functional macro |
US6492736B1 (en) * | 2001-03-14 | 2002-12-10 | Lsi Logic Corporation | Power mesh bridge |
Also Published As
Publication number | Publication date |
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JP2003058591A (en) | 2003-02-28 |
JP4596406B2 (en) | 2010-12-08 |
US6760897B2 (en) | 2004-07-06 |
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