US20020089059A1

US20020089059A1 - Semiconductor device and method for manufacturing the same

Info

Publication number: US20020089059A1
Application number: US10/032,562
Authority: US
Inventors: Shinichi Imai
Original assignee: Individual
Current assignee: Panasonic Holdings Corp
Priority date: 2001-01-10
Filing date: 2002-01-02
Publication date: 2002-07-11
Anticipated expiration: 2022-01-02
Also published as: JP2002208633A; US6821885B2

Abstract

A method for manufacturing a semiconductor device of the present invention includes the steps of: (a) depositing an interlayer insulator film on a substrate including a plurality of conductive layers; (b) forming a plurality of contact holes running through the interlayer insulator film to reach respective ones of the plurality of conductive layers, each of the contact holes having a tapered portion at an upper end thereof; (c) depositing a conductive material film on the interlayer insulator film so as to fill the plurality of contact holes; (d) removing the conductive material film until a surface of the interlayer insulator film is exposed so as to form a plurality of plugs made of the conductive material film filling the plurality of contact holes; and (e) removing a portion of the interlayer insulator film, which has been exposed in the step (d), so as to remove the tapered portions.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to measures that should be taken along with the miniaturization of semiconductor devices.

In recent years, there has been a remarkable improvement in the degree of integration of semiconductor devices. As the degree of integration increases, the wiring pitch has been decreasing. As the wiring pitch decreases, there has been a decrease in the minimum width of the interlayer insulator film existing between adjacent ones of contact holes that are running through wiring layers (the width by which the contact holes are separated from each other). In other words, there has been a decrease in the width by which adjacent plugs (made of a conductive material film filling the contact holes so as to connect the wiring layers to one another) are separated from each other.

For example, in a device designed under a 0.18 μm design rule, the wiring pitch is 0.47 μm, and the diameter of a contact hole (plug) is 0.26 μm. Thus, the contact hole separation width (the plug separation width) is 0.21 μm. When manufacturing a semiconductor device having such a small contact hole separation width, it is necessary to form a large number of closely arranged contact holes, which requires an etching mask having a large number of closely arranged contact hole patterns corresponding respectively to the contact holes. However, when a resist film is patterned to produce an etching mask, it is likely that each contact hole pattern is shaped so that an upper portion thereof is larger than a lower portion thereof. In other words, the contact hole pattern is likely to have a tapered cross section. For example, where a contact hole having a diameter of 0.26 μm is formed using a resist film having a thickness of 0.7 μm, if the upper portion of the contact hole pattern is enlarged by 10% (0.026 μm) in diameter during the resist film patterning process, the side surface of the contact hole pattern has an inclination angle (taper angle) of 89° with respect to the substrate surface.

Such an contact hole pattern having a tapered cross section is formed when, for example, the focus value is shifted from the intended median during a patterning process in the lithography step. When such an contact hole pattern having a tapered cross section is formed, the thickness of the resist film may decrease from the thickness of the resist film as applied in locations between adjacent contact hole patterns, whereby the adjacent contact hole patterns are connected to each other via the upper portions thereof.

When a contact hole is formed by etching an interlayer insulator film using such a resist film as an etching mask, the contact hole is likely to be shaped so that an upper portion thereof is larger than a lower portion. In other words, a contact hole whose upper portion has a tapered cross section is likely to be formed.

FIG. 11A to FIG. 11D are cross-sectional views and top views schematically illustrating a conventional method for manufacturing a semiconductor device. The cross-sectional views of FIG. 11A, FIG. 11B and FIG. 11D are taken along lines α 11-α11, β11-β11 and δ11-δ11, respectively, which are shown in the corresponding top views.

First, in the step of FIG. 11A, impurity diffusion regions (not shown) are formed in a

semiconductor substrate

1 to form switching transistors (not shown), etc. Then, a wiring layer 2 is formed on the semiconductor substrate 1, and an interlayer insulator film 3 is formed thereon.

Then, the

interlayer insulator film

3 is flattened by a chemical mechanical polishing (hereinafter referred to as “CMP”) method, and a resist film 4 is formed thereon. Then, contact hole patterns 5 corresponding respectively to contact holes are formed in the resist film 4 by photolithography. Ideally, each contact hole pattern 5 has a cross section such that a side wall 6 thereof is perpendicular to the substrate surface. In practice, however, the cross section of the contact hole pattern 5 is likely to be slightly tapered in the forward direction as described above.

Then, in the step of FIG. 11B,

contact holes

7 are formed by etching the interlayer insulator film 3 using the resist film 4 as an etching mask. After the etching process, an upper portion of each contact hole 7 is tapered.

Then, in the step of FIG. 11C, a conductive material film 8 (e.g., polysilicon, tungsten, copper, etc.) is deposited on the substrate.

Then, in the step of FIG. 11D, the

conductive material film

8 is flattened by a CMP method until the surface of the interlayer insulator film 3 is exposed, thus forming plugs 9 which are made of the conductive material film 8 filling the contact holes 7.

A

semiconductor device

100 is produced through these steps.

However, with the conventional method for manufacturing a semiconductor device as described above, adjacent contact holes may be connected to each other via the upper portions thereof, as illustrated in the plan view of FIG. 11B. Therefore, adjacent plugs are likely to be connected to each other via the upper portions thereof, as illustrated in the plan view of FIG. 11D, thereby causing a short-circuit between the plugs.

SUMMARY OF THE INVENTION

The present invention has been made to solve the problem described above, and has an object to provide a semiconductor device having a small wiring pitch and a method for manufacturing the same.

A method for manufacturing a semiconductor device of the present invention includes the steps of: (a) depositing an interlayer insulator film on a substrate including a plurality of conductive layers; (b) forming a plurality of contact holes running through the interlayer insulator film to reach respective ones of the plurality of conductive layers, each of the contact holes having a tapered portion (faceting portion) at an upper end thereof; (c) depositing a conductive material film on the interlayer insulator film so as to fill the plurality of contact holes; (d) removing the conductive material film until a surface of the interlayer insulator film is exposed so as to form a plurality of plugs made of the conductive material film filling the plurality of contact holes; and (e) removing a portion of the interlayer insulator film, which has been exposed in the step (d), so as to remove the tapered portions.

In this way, even if adjacent contact holes are connected to each other via the upper portions thereof in the step (b) of forming the plurality of contact holes, it is possible to prevent the plugs filling the contact holes from being short-circuited to each other.

Another method for manufacturing a semiconductor device of the present invention includes the steps of: (a) depositing an interlayer insulator film on a substrate including a plurality of conductive layers; (b) depositing a first conductive material film on the substrate; (c) forming a plurality of contact holes running through the first conductive material film and the interlayer insulator film to reach respective ones of the plurality of conductive layers; (d) depositing a second conductive material film on the first conductive material film so as to fill the plurality of contact holes; and (e) removing the second conductive material film and the first conductive material film until a surface of the interlayer insulator film is exposed so as to form a plurality of plugs which are made of the conductive material film filling the plurality of contact holes.

In this way, even if adjacent contact holes are connected to each other via the upper portions thereof in the step of forming the contact holes, it is possible to prevent the plugs filling the contact holes from being short-circuited to each other. Particularly, adjacent contact holes can be separated from each other only by flattening the first and second conductive material films. Thus, the interlayer insulator film is not flattened by a method that is adjusted to conditions according to the first and second conductive material films. Therefore, the method is particularly suitable for cases where flattening the interlayer insulator film by a method that is adjusted to conditions according to the first and second conductive material films may cause problems.

Still another method for manufacturing a semiconductor device of the present invention includes the steps of: (a) depositing an interlayer insulator film on a substrate including a plurality of conductive layers; (b) forming a plurality of contact holes running through the interlayer insulator film to reach respective ones of the plurality of conductive layers, each of the contact holes having a tapered portion at an upper end thereof; (c) removing a portion of the interlayer insulator film so as to remove the tapered portions; (d) depositing a conductive material film on the interlayer insulator film so as to fill the plurality of contact holes; and (e) removing the conductive material film until a surface of the interlayer insulator film is exposed so as to form a plurality of plugs which are made of the conductive material film filling the plurality of contact holes.

A portion of the interlayer insulator film is removed so as to remove the tapered portions, thereby separating adjacent contact holes from each other, before depositing the conductive material film. Therefore, it is possible to prevent the plugs filling the contact holes from being short-circuited to each other.

In the step (c), the tapered portions may be removed by etching or chemical mechanical polishing.

Still another method for manufacturing a semiconductor device of the present invention includes the steps of: (a) depositing an interlayer insulator film on a substrate including a plurality of conductive layers; (b) forming a plurality of contact holes running through the interlayer insulator film to reach respective ones of the plurality of conductive layers, each of the contact holes having a tapered portion at an upper end thereof; (c) forming an organic material film so as to fill the plurality of contact holes; (d) removing a portion of the interlayer insulator film so as to remove the tapered portions; (e) removing the organic material film; (f) depositing a conductive material film on the interlayer insulator film so as to fill the plurality of contact holes; (g) removing the conductive material film until a surface of the interlayer insulator film is exposed so as to form a plurality of plugs which are made of the conductive material film filling the plurality of contact holes.

A portion of the interlayer insulator film is removed so as to remove the tapered portions, thereby separating adjacent contact holes from each other, before depositing the conductive material film. Therefore, it is possible to prevent the plugs filling the contact holes from being short-circuited to each other. Particularly, when the entire surface of the substrate is flattened by a CMP method, a slurry may remain inside the contact holes. Removal of the slurry may be difficult when the contact hole has a high aspect ratio. However, according to the present invention, the slurry used in the CMP method will not remain in the contact holes because the contact holes are filled with the organic material film. Thus, it is possible to suppress/prevent a slurry from existing, as an impurity, in the conductive material film when forming the plugs.

In the step (d), the tapered portions may be removed by etching or chemical mechanical polishing.

Still another method for manufacturing a semiconductor device of the present invention includes the steps of: (a) depositing an interlayer insulator film on a substrate including a plurality of conductive layers; (b) applying a resist film on the interlayer insulator film and patterning the resist film so as to from an etching mask having a plurality of contact hole patterns therein; (c) performing an etching process using the etching mask so as to form a plurality of contact holes running through the interlayer insulator film to reach respective ones of the plurality of conductive layers; (d) depositing a conductive material film on the interlayer insulator film so as to fill the plurality of contact holes; and (e) removing the conductive material film until a surface of the interlayer insulator film is exposed so as to form a plurality of plugs which are made of the conductive material film filling the plurality of contact holes, wherein in the step (b), the resist film is applied to a thickness such that upper ends of the plurality of contact holes will not be tapered in the step (c).

According to the method, the resist film is applied to a thickness such that the upper ends of the plurality of contact holes will not be tapered in the step (c). Thus, adjacent contact holes are not connected via the upper portions thereof in the step of forming the contact holes by etching. In this way, it is possible to avoid an additional step of separating adjacent contact holes that have been connected to each other via the upper portions thereof, which would otherwise be required before or after forming a conductive material film so as to fill the contact holes. Therefore, it is possible to suppress/prevent a short-circuit between plugs while reducing the manufacturing cost.

Preferably, in the step (c), a ratio of an etch rate for the interlayer insulator film with respect to an etch rate for the resist film located on a side wall of each of the contact holes is 3.5 or more.

A semiconductor device of the present invention includes: a substrate including a plurality of conductive layers; an interlayer insulator film provided on the substrate; and a plurality of plugs running through the interlayer insulator film to reach respective ones of the plurality of conductive layers, wherein any adjacent two of the plurality of plugs are separated from each other by the interlayer insulator film, and a minimum width of the interlayer insulator film existing between two adjacent plugs is 0.30 μm or less.

In this way, it is possible to obtain a semiconductor device in which a short-circuit between plugs is suppressed/prevented.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A to FIG. 1E are cross-sectional views and top views schematically illustrating a method for manufacturing a [0030] semiconductor device 10 of Embodiment 1 of the present invention, wherein the cross-sectional views of FIG. 1A, FIG. 1B, FIG. 1D and FIG. 1E are taken along lines α1-α1, β1-β1, δ1-δ1 and ε1-ε1, respectively, which are shown in the corresponding top views.
FIG. 2A to FIG. 2D are cross-sectional views and top views schematically illustrating a method for manufacturing a [0031] semiconductor device 20 of Embodiment 2 of the present invention, wherein the cross-sectional views of FIG. 2A, FIG. 2B and FIG. 2D are taken along lines α2-α2, β2-β2 and δ2-δ2, respectively, which are shown in the corresponding top views.
FIG. 3A to FIG. 3E are cross-sectional views and top views schematically illustrating a method for manufacturing a [0032] semiconductor device 30 of Embodiment 3 of the present invention, wherein the cross-sectional views of FIG. 3A, FIG. 3B, FIG. 3C and FIG. 3E are taken along lines α3-α3, β3-β3, γ3-γ3 and ε3-ε3, respectively, which are shown in the corresponding top views.
FIG. 4A to FIG. 4F are cross-sectional views and top views schematically illustrating a method for manufacturing a [0033] semiconductor device 40 of Embodiment 4 of the present invention, wherein the cross-sectional views of FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D and FIG. 4F are taken along lines α4-α4, β4-β4, γ4-γ4, δ4-δ4 and ζ4-ζ4, respectively, which are shown in the corresponding top views.
FIG. 5A to FIG. 5D are cross-sectional views and top views schematically illustrating a method for manufacturing a [0034] semiconductor device 50 of Embodiment 5 of the present invention, wherein the cross-sectional views of FIG. 5A and FIG. 5D are taken along lines α5-α5 and δ5-δ5, respectively, which are shown in the corresponding top views.
FIG. 6A to FIG. 6D are cross-sectional views and top views schematically illustrating a conventional method for manufacturing a semiconductor, wherein the cross-sectional views of FIG. 6A and FIG. 6D are taken along lines α[0035] 6-α6 and δ6-δ6, respectively, which are shown in the corresponding top views.
FIG. 7 is an enlarged view illustrating an upper portion of an contact hole pattern used for forming a contact hole, and the contact hole. [0036]
FIG. 8 is a graph illustrating required selectivity ratios for various etching depths in a case where the initial resist film thickness is 700 nm in [0037] Embodiment 5.
FIG. 9 is a graph illustrating required selectivity ratios for various etching depths in a case where the initial resist film thickness is 500 nm in [0038] Embodiment 5.
FIG. 10 is a graph illustrating required selectivity ratios for various etching depths in a case where the initial resist film thickness is 900 nm in [0039] Embodiment 5.
FIG. 11A to FIG. 11D are cross-sectional views and top views schematically illustrating a conventional method for manufacturing a semiconductor, wherein the cross-sectional views of FIG. 11A, FIG. 11B and FIG. 11D are taken along lines α[0040] 11-α11, β11-β11 and δ11-δ11, respectively, which are shown in the corresponding top views.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Various embodiments of the present invention will now be described with reference to the drawings. For the sake of simplicity, like reference numerals denote like elements throughout the figures. [0041]
[0042] EMBODIMENT 1
FIG. 1A to FIG. 1E are cross-sectional views and top views schematically illustrating a method for manufacturing a [0043] semiconductor device 10 of Embodiment 1 of the present invention, wherein the cross-sectional views of FIG. 1A, FIG. 1B, FIG. 1D and FIG. 1E are taken along lines α1-α1, β1-β1, δ1-δ1 and ε1-ε1, respectively, which are shown in the corresponding top views.
First, in the step of FIG. 1A, impurity diffusion regions (not shown) are formed in a [0044] semiconductor substrate 1 to form switching transistors (not shown), etc. Then, a wiring layer 2 is formed on the semiconductor substrate 1. In the present embodiment, the wiring pitch of the wiring layer 2 is 0.47 μm.
Then, an [0045] interlayer insulator film 3 is formed on the semiconductor substrate 1. In the present embodiment, an oxide film is used as the interlayer insulator film 3. Then, the interlayer insulator film 3 is flattened by using a CMP method. Then, a resist film 4 is formed so as to cover the interlayer insulator film 3. Then, contact hole patterns 5 are formed in the resist film 4 by photolithography. The contact hole patterns 5 are formed so that a side wall 6 of each contact hole pattern 5 is tapered downwardly.
Then, in the step of FIG. 1B, the [0046] interlayer insulator film 3 is dry-etched using the resist film 4 having the contact hole patterns 5 therein as an etching mask so as to form contact holes 7 reaching the wiring layer 2 or the impurity diffusion regions (not shown). As described above, after the etching process, an upper portion of each contact hole 7 is likely to be tapered, as illustrated in the top view of FIG. 1B. Thus, adjacent contact holes 7 may be connected to each other via the upper portions thereof.
Then, in the step of FIG. 1C, a conductive material film [0047] 8 (e.g., polysilicon, a tungsten film, copper, etc.) is deposited on the substrate.
Then, in the step of FIG. 1D, the [0048] conductive material film 8 is flattened by a CMP method until the surface of the interlayer insulator film 3 is exposed, thus forming plugs 9 which are made of the conductive material film 8 filling the contact holes 7.
Then, in the step of FIG. 1E, a further polishing (over-polishing) process is performed by a CMP method so as to remove a portion of the [0049] interlayer insulator film 3 corresponding to the tapered upper portion of the contact hole 7. Thus, the upper portions of adjacent contact holes 7 are separated from each other.
The [0050] semiconductor device 10 is produced through these steps.
According to the present embodiment, even if [0051] adjacent contact holes 7 are connected to each other via the upper portions thereof when the contact holes 7 is formed while manufacturing the semiconductor device 10, it is possible to prevent the plugs 9 filling the contact holes 7 from being short-circuited to each other. The method of the present embodiment is advantageous in manufacturing a semiconductor device in which the minimum width of the interlayer insulator film existing between two adjacent plugs is 0.30 μm or less, and provides significant effects in manufacturing a semiconductor device in which the wiring pitch of the wiring layer 2 is 0.50 μm or less.
[0052] EMBODIMENT 2
FIG. 2A to FIG. 2D are cross-sectional views and top views schematically illustrating a method for manufacturing a [0053] semiconductor device 20 of Embodiment 2 of the present invention, wherein the cross-sectional views of FIG. 2A, FIG. 2B and FIG. 2D are taken along lines α2-α2, β2-β2 and δ2-δ2, respectively, which are shown in the corresponding top views.
First, in the step of FIG. 2A, impurity diffusion regions (not shown) are formed in the [0054] semiconductor substrate 1 to form switching transistors (not shown), etc. Then, the wiring layer 2 is formed on the semiconductor substrate 1. In the present embodiment, the wiring pitch of the wiring layer 2 is 0.47 μm.
Then, the [0055] interlayer insulator film 3 is formed on the semiconductor substrate 1. In the present embodiment, an oxide film is used as the interlayer insulator film 3. Then, the interlayer insulator film 3 is flattened by using a CMP method. Then, a conductive material film 11 is formed so as to cover the interlayer insulator film 3, after which the resist film 4 is formed so as to cover the conductive material film 11. Then, the contact hole patterns 5 are formed in the resist film 4 by photolithography. The contact hole patterns 5 are formed so that the side wall 6 of each contact hole pattern 5 is tapered downwardly, as illustrated in FIG. 2A.
Then, in the step of FIG. 2B, using the resist [0056] film 4 having the contact hole patterns 5 therein as an etching mask, the conductive material film 11 is first etched in a plasma etching process using a plasma containing an active species therein and having fluorine or chlorine as its main component. Then, the interlayer insulator film 3 is dry-etched so as to form the contact holes 7 reaching the wiring layer 2 or the impurity diffusion regions (not shown). As described above, after the etching process, an upper portion of each contact hole 7, i.e., a portion corresponding to the conductive material film 11, is likely to be tapered, as illustrated in the top view of FIG. 2B. Thus, adjacent contact holes 7 may be connected to each other via the upper portions thereof.
Then, in the step of FIG. 2C, the [0057] conductive material film 8 is deposited on the substrate.
Then, in the step of FIG. 2D, a flattening process is performed by a CMP method. The flattening process by a CMP method is performed to remove the [0058] conductive material film 11 until the surface of the interlayer insulator film 3 is exposed, thus forming the plugs 9 which are made of the conductive material film 8.
The [0059] semiconductor device 20 is produced through these steps.
While tungsten is used as the [0060] conductive material films 8 and 11 in the present embodiment, polysilicon, copper, etc., may alternatively be used instead of tungsten.
According to the present embodiment, even if [0061] adjacent contact holes 7 are connected to each other via the upper portions thereof when the contact holes 7 is formed while manufacturing the semiconductor device 20, it is possible to prevent the plugs 9 filling the contact holes 7 from being short-circuited to each other. The method of the present embodiment is advantageous in manufacturing a semiconductor device in which the minimum width of the interlayer insulator film existing between two adjacent plugs is 0.30 μm or less, and provides significant effects in manufacturing a semiconductor device in which the wiring pitch of the wiring layer 2 is 0.50 μm or less.
Moreover, in the present embodiment, [0062] adjacent contact holes 7 can be separated from each other only by flattening the conductive material films 8 and 11 by a CMP method. Thus, the interlayer insulator film 3 is not flattened by a CMP method that is adjusted to conditions according to the conductive material films 8 and 11. Therefore, the method of the present embodiment is particularly suitable for cases where flattening the interlayer insulator film 3 by a CMP method that is adjusted to conditions according to the conductive material films 8 and 11 may cause problems. Furthermore, employing the two-layer structure including the conductive material films 8 and 11 and the interlayer insulator film 3 makes it easier to determine the end point of the CMP process.
While the [0063] conductive material films 8 and 11 may be of different materials, the same material is preferably employed for the conductive material films 8 and 11, in which case it is possible to employ the same CMP conditions (slurry species, etc.).
[0064] EMBODIMENT 3
FIG. 3A to FIG. 3E are cross-sectional views and top views schematically illustrating a method for manufacturing a [0065] semiconductor device 30 of Embodiment 3 of the present invention, wherein the cross-sectional views of FIG. 3A, FIG. 3B, FIG. 3C and FIG. 3E are taken along lines α3-α3, β3-β3, γ3-γ3 and ε3-ε3, respectively, which are shown in the corresponding top views.
As illustrated in FIG. 3A and FIG. 3B, the method of the present embodiment is the same as that of [0066] Embodiment 1 up to the step of forming the contact holes 7 in the interlayer insulator film 3.
Then, in the step of FIG. 3C, an etchback process is performed on the entire surface of the substrate. In this process, the tapered upper portions of the contact holes [0067] 7 are removed. Thus, adjacent contact holes 7 can be separated from each other. While a CMP method is employed for the etchback process on the entire surface of the substrate in the present embodiment, the entire surface of the substrate may alternatively be etched by a plasma etching process instead of a CMP method. A CMP method is preferred particularly because the tapered upper portions can be removed effectively.
Then, in the step of FIG. 3D, the [0068] conductive material film 8 is deposited on the substrate.
Then, in the step of FIG. 3E, the [0069] conductive material film 8 is flattened by a CMP method until the surface of the interlayer insulator film 3 is exposed, thus forming the plugs 9 which are made of the conductive material film 8 filling the contact holes 7.
The [0070] semiconductor device 30 is produced through these steps.
According to the present embodiment, the tapered upper portions of the contact holes [0071] 7 are removed by an etchback process using a CMP method, or the like, thereby separating adjacent contact holes 7 from each other, before depositing the conductive material film 8. Thus, it is possible to prevent the plugs 9 filling the contact holes 7 from being short-circuited to each other. The method of the present embodiment is advantageous in manufacturing a semiconductor device in which the minimum width of the interlayer insulator film existing between two adjacent plugs is 0.30 μm or less, and provides significant effects in manufacturing a semiconductor device in which the wiring pitch of the wiring layer 2 is 0.50 μm or less.
Particularly, in the present embodiment, a CMP method whose conditions are optimized for the [0072] interlayer insulator film 3 can be used in the etchback process, which is performed before depositing the conductive material film 8.
Moreover, the method for manufacturing a semiconductor device of the present embodiment is particularly suitable for cases where a material that is difficult to etch in a plasma etching process, e.g., copper, is used as the conductive material film. [0073]
In order to etch copper in a plasma etching process, it is typically necessary to increase the temperature of the substrate to be 200° C. or more, whereby it is difficult to perform the etching process with a method in which a resist film is used. Therefore, it is often the case that a film that undergoes little deformation to temperature (e.g., a hard mask such as an oxide film) is used instead of a resist film. [0074]
According to the present embodiment, however, there is no such problem because the plasma etching process is not performed. [0075]
[0076] EMBODIMENT 4
FIG. 4A to FIG. 4F are cross-sectional views and top views schematically illustrating a method for manufacturing a [0077] semiconductor device 40 of Embodiment 4 of the present invention, wherein the cross-sectional views of FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D and FIG. 4F are taken along lines α4-α4, β4-β4, γ4-γ4, δ4-δ4 and ζ4-ζ4, respectively, which are shown in the corresponding top views.
As illustrated in FIG. 4A, the method of the present embodiment is the same as that of [0078] Embodiment 1 up to the step of forming the contact holes 7 in the interlayer insulator film 3.
Then, in the step of FIG. 4B, the resist [0079] film 4 is removed, and the substrate is washed. Then, an organic material film 12 (e.g., a resist film or an ARC (anti-reflective coating)) is formed so as to fill the contact holes 7.
Then, in the step of FIG. 4C, a portion of the [0080] interlayer insulator film 3 corresponding to the tapered upper portion of the contact hole 7 is removed by a CMP method. Thus, adjacent contact holes 7 are separated from each other. Then, the entire surface of the substrate is washed.
Then, in the step of FIG. 4D, the [0081] organic material film 12 is removed by a plasma etching process using a plasma having oxygen as its main component, or by using a solvent.
Then, in the step of FIG. 4E, the conductive material film [0082] 8 (e.g., polysilicon, a tungsten film, copper, etc.) is deposited on the substrate.
Then, in the step of FIG. 4F, the [0083] conductive material film 8 is flattened by a CMP method until the surface of the interlayer insulator film 3 is exposed, thus forming the plugs 9 which are made of the conductive material film 8 filling the contact holes 7.
The [0084] semiconductor device 40 is produced through these steps.
According to the present embodiment, the tapered upper portions of the contact holes [0085] 7 are removed by an etchback process using a CMP method, or the like, thereby separating adjacent contact holes 7 from each other, before depositing the conductive material film 8. Thus, it is possible to prevent the plugs 9 filling the contact holes 7 from being short-circuited to each other. The method of the present embodiment is advantageous in manufacturing a semiconductor device in which the minimum width of the interlayer insulator film existing between two adjacent plugs is 0.30 μm or less, and provides significant effects in manufacturing a semiconductor device in which the wiring pitch of the wiring layer 2 is 0.50 μm or less.
In a case where the tapered upper portions of the contact holes [0086] 7 are removed in an etchback process by a CMP method, or the like, with the contact hole 7 being open, a slurry may remain inside the contact holes 7 or a damage may be introduced due to the etchback process. Normally, a washing process is performed so as to remove the slurry. However, the removal of the slurry may be difficult when the contact hole 7 is a so-called “high aspect ratio” contact hole, where the ratio of the thickness of the interlayer insulator film 3 is high with respect to the diameter of the contact hole 7.
According to the present embodiment, a slurry used in a CMP method will not remain in the contact holes [0087] 7 because the contact holes 7 are filled with an organic material film. Thus, it is possible to suppress/prevent a slurry from existing, as an impurity, in a conductive material film when forming the plugs 9. Moreover, it is possible to suppress the damage due to an etchback process.
[0088] EMBODIMENT 5
As described above, with a conventional method for manufacturing a semiconductor device, contact holes may be connected to each other via upper portions thereof. The possible cause of the problem will be further discussed below with reference to FIG. 6A to FIG. 6D. FIG. 6A to FIG. 6D schematically illustrate a part of the conventional manufacturing method from the step of FIG. 11A to the step of FIG. 11B. [0089]
In a dry etching process in which the resist [0090] film 4 having the contact hole patterns 5 therein is used as an etching mask, as illustrated in FIG. 6A, the resist film 4 is also etched at the same time. Therefore, as the etching process proceeds, the thickness of the resist film 4 as a whole is reduced, and especially the contact hole patterns 5 are etched into a tapered shape, as illustrated in FIG. 6B. Thus, the contact hole patterns 5 may be connected to each other via the upper portions thereof at locations as that pointed by arrow B in FIG. 6B. AS the etching process further proceeds, the diameter of the contact hole pattern 5, being etched into a tapered shape, increases, as illustrated in FIG. 6C. As a result, an upper portion of the interlayer insulator film 3 located inside the contact hole pattern 5 is etched. Thus, a portion of the interlayer insulator film 3 that is not originally located in the contact hole pattern 5 is etched. Therefore, an upper portion of the contact hole 7 is tapered.
The small tapered portion in the upper portion of the [0091] contact hole 7 is enlarged in the following sputtering process using an inert gas (such as argon), which is performed before depositing the conductive material film 8. As a result, adjacent contact holes 7 may be connected via the upper portions thereof.
This phenomenon can be mathematically described as follows. Referring to FIG. 7, t0 denotes the initial thickness of the resist [0092] film 4, t1 denotes the thickness of a portion of the resist film 4 that forms the side wall 6, and θ denotes the taper angle of the tapered portion of the resist film 4. Then, t1 can be expressed by Expression (1) below:
t1=t0−RT/cosθ (1)
where R denotes the resist etch rate for a flat portion, and T denotes the etching time. [0093]
No tapered portion is formed if t1>tc, where tc denotes the critical thickness of the resist [0094] film 4 for the formation of a tapered portion in an upper portion of the contact hole 7. Thus, t0−RT/cosθ>tc. It has been experimentally found that tc has a value in the range of 150 to 200 nm. Therefore, when the resist film has a thickness of at least 150 nm, no tapered portion is formed in the upper portion of the contact hole 7. To be on the safe side, it is preferred that the thickness of the resist film is about 200 nm. Applying tc=200 nm to the above expression yields Expression (2) below:
(t0−200)cosθ>RT (2)
Thus, no tapered portion is formed in the upper portion of the [0095] contact hole 7 as long as Expression (2) is satisfied.
Expression (2) can be transformed into Expression (3) below: [0096]
s>L((t0−200)cosθ) (3)
where s denotes the ratio (selectivity ratio) of the etch rate for the [0097] interlayer insulator film 3 with respect to the etch rate for the resist film 4, and L denotes the depth (etching depth) of a contact hole to be made by etching with respect to the surface of the interlayer insulator film 3.
Now, L is the total depth including the depth gained through over-etching (OE), and the value OE is normally 30% to 70% of the actual depth of the [0098] contact hole 7. Thus, L=La(1+OE/100), where La denotes the actual depth of the contact hole 7.
Using Expression (3) above, it is possible to obtain the selectivity ratio that is required for preventing a tapered portion from being formed in the upper portion of the [0099] contact hole 7. FIG. 8, FIG. 9 and FIG. 10 illustrate the calculation results for t0=700 nm, t0=500 nm and t0=900 nm, respectively. Note that θ is significantly dependent on the etching conditions, and increases as the ion energy is increased. The ion energy is equal to the self bias value and is also equal to about ½ of the peak-to-peak voltage of a high frequency power that is applied to a cathode of a dry etching apparatus.
As can be seen from the results shown in FIG. 8, FIG. 9 and FIG. 10, the [0100] contact hole 7 of a typical depth (about 500 nm) can be formed as long as the selectivity ratio s is 3.5 or more, in any of the cases.
The present embodiment is based on the above consideration. A method for manufacturing a semiconductor device of the present embodiment will now be described with reference to FIG. 5A to FIG. 5D. [0101]
FIG. 5A to FIG. 5D are cross-sectional views and top views schematically illustrating a method for manufacturing a [0102] semiconductor device 50 of Embodiment 5 of the present invention, wherein the cross-sectional views of FIG. 5A and FIG. 5D are taken along lines α5-α5 and δ5-δ5, respectively, which are shown in the corresponding top views.
First, in the step of FIG. 5A, impurity diffusion regions (not shown) are formed in the [0103] semiconductor substrate 1 to form switching transistors (not shown), etc. Then, the wiring layer 2 is formed on the semiconductor substrate 1. In the present embodiment, the wiring pitch of the wiring layer 2 is 0.47 μm.
Then, the [0104] interlayer insulator film 3 is formed on the semiconductor substrate 1. In the present embodiment, an oxide film is used as the interlayer insulator film 3. Then, the interlayer insulator film 3 is flattened by using a CMP method. Then, the resist film 4 is formed so as to cover the interlayer insulator film 3. As described above, this process is performed so that the thickness of the resist film 4 satisfies Expression (2) above. Then, the contact hole patterns 5 are formed in the resist film 4 by photolithography. The contact hole patterns 5 are formed so that the side wall 6 of each contact hole pattern 5 is tapered downwardly.
Then, in the step of FIG. 5B, the [0105] interlayer insulator film 3 is dry-etched using the resist film 4 having the contact hole patterns 5 therein as an etching mask so as to form contact holes 7 reaching the wiring layer 2 or the impurity diffusion regions (not shown). The dry etching process is performed under conditions that satisfy Expression (3) above.
Then, in the step of FIG. 5C, the conductive material film [0106] 8 (e.g., polysilicon, a tungsten film, copper, etc.) is deposited on the substrate.
Then, in the step of FIG. 5D, the [0107] conductive material film 8 is flattened by a CMP method until the surface of the interlayer insulator film 3 is exposed, thus forming the plugs 9 which are made of the conductive material film 8 filling the contact holes 7.
The [0108] semiconductor device 50 is produced through these steps.
According to the present embodiment, adjacent contact holes are not connected to each other via upper portions thereof during the formation of the contact holes. The method of the present embodiment is advantageous in manufacturing a semiconductor device in which the minimum width of the interlayer insulator film existing between two adjacent plugs is 0.30 μm or less, and provides significant effects in manufacturing a semiconductor device in which the wiring pitch of the [0109] wiring layer 2 is 0.50 μm or less.
Particularly, in the present embodiment, the thickness of the resist [0110] film 4 and the etching conditions are adjusted so that adjacent contact holes are not connected to each other via upper portions thereof during the formation of the contact holes 7 by etching. In this way, it is possible to avoid an additional step of separating adjacent contact holes 7 that have been connected to each other via the upper portions thereof, which would otherwise be required before or after forming a conductive material film so as to fill the contact holes 7. Therefore, it is possible to suppress/prevent a short-circuit between plugs while reducing the manufacturing cost.

Claims

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising the steps of:

(a) depositing an interlayer insulator film on a substrate including a plurality of conductive layers;

(b) forming a plurality of contact holes running through the interlayer insulator film to reach respective ones of the plurality of conductive layers, each of the contact holes having a tapered portion at an upper end thereof;

(c) depositing a conductive material film on the interlayer insulator film so as to fill the plurality of contact holes;

(d) removing the conductive material film until a surface of the interlayer insulator film is exposed so as to form a plurality of plugs made of the conductive material film filling the plurality of contact holes; and

(e) removing a portion of the interlayer insulator film, which has been exposed in the step (d), so as to remove the tapered portions.

2. A method for manufacturing a semiconductor device, comprising the steps of:

(b) depositing a first conductive material film on the substrate;

(c) forming a plurality of contact holes running through the first conductive material film and the interlayer insulator film to reach respective ones of the plurality of conductive layers;

(d) depositing a second conductive material film on the first conductive material film so as to fill the plurality of contact holes; and

(e) removing the second conductive material film and the first conductive material film until a surface of the interlayer insulator film is exposed so as to form a plurality of plugs which are made of the conductive material film filling the plurality of contact holes.

3. A method for manufacturing a semiconductor device, comprising the steps of:

(c) removing a portion of the interlayer insulator film so as to remove the tapered portions;

(d) depositing a conductive material film on the interlayer insulator film so as to fill the plurality of contact holes; and

(e) removing the conductive material film until a surface of the interlayer insulator film is exposed so as to form a plurality of plugs which are made of the conductive material film filling the plurality of contact holes.

4. The method for manufacturing a semiconductor device of claim 3, wherein in the step (c), the tapered portions are removed by etching or chemical mechanical polishing.

5. A method for manufacturing a semiconductor device, comprising the steps of:

(c) forming an organic material film so as to fill the plurality of contact holes;

(d) removing a portion of the interlayer insulator film so as to remove the tapered portions;

(e) removing the organic material film;

(f) depositing a conductive material film on the interlayer insulator film so as to fill the plurality of contact holes;

(g) removing the conductive material film until a surface of the interlayer insulator film is exposed so as to form a plurality of plugs which are made of the conductive material film filling the plurality of contact holes.

6. The method for manufacturing a semiconductor device of claim 5, wherein in the step (d), the tapered portions are removed by etching or chemical mechanical polishing.

7. A method for manufacturing a semiconductor device, comprising the steps of:

(b) applying a resist film on the interlayer insulator film and patterning the resist film so as to from an etching mask having a plurality of contact hole patterns therein;

(c) performing an etching process using the etching mask so as to form a plurality of contact holes running through the interlayer insulator film to reach respective ones of the plurality of conductive layers;

(e) removing the conductive material film until a surface of the interlayer insulator film is exposed so as to form a plurality of plugs which are made of the conductive material film filling the plurality of contact holes,

wherein in the step (b), the resist film is applied to a thickness such that upper ends of the plurality of contact holes will not be tapered in the step (c).

8. The method for manufacturing a semiconductor device of claim 7, wherein in the step (c), a ratio of an etch rate for the interlayer insulator film with respect to an etch rate for the resist film located on a side wall of each of the contact holes is 3.5 or more.

9. A semiconductor device, comprising:

a substrate including a plurality of conductive layers;

an interlayer insulator film provided on the substrate; and

a plurality of plugs running through the interlayer insulator film to reach respective ones of the plurality of conductive layers,

wherein any adjacent two of the plurality of plugs are separated from each other by the interlayer insulator film, and a minimum width of the interlayer insulator film existing between two adjacent plugs is 0.30 μm or less.